Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
Independent Claims 1, 4, and 12 have been amended. Claims 2-3, 5-6, 14 and 16 are cancelled.
Response to Arguments
Applicant's arguments filed 11/20/2025 have been fully considered but they are not persuasive. Applicant argues that the amendments made to claim 1 fails to establish a prima facie case of anticipation or obviousness for the invention of claim 1 and its dependent claims in view of Zeng. The amendment introduces the limitation “wherein the second gate electrode has a first end and a second end opposite to each other in a direction parallel to a surface of the substrate, the first end is attached to the first gate insulating layer, and the second end is aligned with an end of the second active layer in a direction perpendicular to the surface of the substrate.” The applicant argues that Zeng fails to teach the added limitation, citing Fig. 1 of Zeng. However, the applicant fails to explain the reason why fig. 1 Zeng fails to teach the new limitation. The device of Zeng as exemplified by Fig. 1, clearly has a gate electrode 11 that functions as a second gate electrode on one end and therefore must be aligned with an end of the second active layer 13, while concurrently functioning as a source/drain electrode on an opposing end where it is both attached to the active layer 23 and the first gate insulating layer 22 via direct contact.
Applicant's arguments do not comply with 37 CFR 1.111(c) because they do not clearly point out the patentable novelty which he or she thinks the claims present in view of the state of the art disclosed by the references cited or the objections made. Further, they do not show how the amendments avoid such references or objections.
Claim Rejections - 35 USC § 102
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 1, 3, 8-11, 12-13, and 15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Zeng et al. (CN 111384071 A), hereinafter referred to as Zeng.
RE: Independent Claim 1.
Zeng teaches a display panel, comprising a plurality of pixel units arranged in an array (Zeng pg. 9, Line 36 “provides an array substrate including the above pixel structure arranged in an array”,
[AltContent: textbox (Exhibit 1: Zeng Fig. 1, depicting first transistor comprising 1st gate (21), 1st gate insulating layer (22), 1st gate active layer (23), 1st S/D electrodes (24, 25), and second transistor comprising 2nd gate (11), 2nd gate insulating layer (121, 123, 122), 2nd active layer (13), 2nd S/D electrode (14, 15))]
PNG
media_image1.png
421
863
media_image1.png
Greyscale
wherein at least one of the plurality of pixel units is provided with a first transistor and a second transistor (Zeng pg. 5, Line 37 “The driving circuit includes a first thin film transistor and a second thin film transistor”),
the first transistor comprises a first gate electrode (Zeng Fig. 1 first gate electrode 21, pg. 7 Line 31 “The first gate 21 of the first thin film transistor is provided on the substrate 10.”),
a first source electrode and a first drain electrode (Zeng Fig. 1 first source electrode 24, first drain electrode 25, pg. 8, Line 12 “The first source 24 and the first drain 25 of the first thin film transistor”),
and the second transistor comprises a second gate electrode, a second source electrode, and a second drain electrode (Zeng pg. 8 Line 16-23, pg. 9 Line 19, Fig. 1 Second gate electrode 11, second source electrode 14, second drain electrode 14, “the second thin film transistor also has a bottom-gate structure… second gate 11… second source 14 and the second drain 15 of the second thin film transistor are disposed on the second gate insulating layer 123”;
the first source electrode, the first drain electrode and the second gate electrode are arranged at intervals in a same layer (Zeng Fig. 1 pg. 8, Line 16-18, S/D (24, 25) and second gate (11) are in the same layer);
and the display panel further comprises: a substrate, wherein the first gate electrode is arranged on the substrate (Zeng Fig. 1 first gate electrode 21, pg. 7 Line 31 “The first gate 21 of the first thin film transistor is provided on the substrate 10.”);
a first gate insulating layer arranged on a side of the first gate electrode away from the substrate (Zeng Fig. 1, pg. 8 Line 1, first gate insulating layer 22);
a first active layer arranged on a side of the first gate insulating layer away from the substrate (Zeng Fig. 1, pg. 8 Line 5, “The first active layer 23 of the first thin film transistor is disposed on the gate insulating layer 22”),
wherein an orthographic projection of the first active layer on the substrate at least partially overlaps an orthographic projection of the first gate electrode on the substrate (Zeng Fig. 1, orthographic projection of first gate electrode 21 at least partially overlaps orthographic projection of the first active layer 23),
and the first source electrode and the first drain electrode are arranged on a side of the first active layer away from the substrate (Zeng Fig. 1, S/D electrode (24, 25) arranged on a side of first active layer (23) away from substrate);
a second gate insulating layer arranged on a side of each of the first source electrode, the first drain electrode and the second gate electrode away from the substrate (Zeng Fig. 1, second gate insulating layer (121, 122, 123) arranged on a side of each of the first source electrode (24), the first drain electrode (25) and the second gate electrode (11) away from the substrate. Where the multiple layers of dielectric material is interpreted by the examiner as being equivalent in function to an insulating layer.);
and a second active layer arranged on a side of the second gate insulating layer away from the substrate (Zeng Fig. 1, pg. 9 Line 11, second active layer 13 “The second active layer 13 of the second thin film transistor is disposed on the second gate insulating layer 123”),
wherein an orthographic projection of the second active layer on the substrate at least partially overlaps an orthographic projection of the second gate electrode on the substrate (Zeng Fig. 1, orthographic projection of the second active layer (23) on the substrate (10) at least partially overlaps an orthographic projection of the second gate electrode (11) on the substrate (10).).
and the second source electrode and the second drain electrode are arranged on a side of the second active layer away from the substrate (Zeng Fig. 1, pg. 9 Line 18-20, the second source electrode (14) and the second drain electrode (15) are arranged on a side of the second active layer (13) away from the substrate);
and a connection line arranged in the same layer as the second gate electrode to electrically connect the second gate electrode with one of the first source electrode and the first drain electrode (Zeng Fig. 1 depicts drain electrode 25 connected to gate electrode 11 in a continuous metal line),
wherein an end of the connection line is attached to the first active layer (Zeng Fig. 1, pg. 8 line 12-14, “the second gate 11 of the second thin film transistor that are disposed on the gate insulating layer 22, the first source 24 And the first drain 25 are electrically connected to the first active layer 23 respectively”),
and another end of the connection line is in contact with an end of the second gate electrode (ibid.)
wherein the second gate electrode has a first end and a second end opposite to each other in a direction parallel to a surface of the substrate (Zeng Fig. 1 depicting second gate electrode 11, having first end and second end in horizontal direction (parallel to the substrate)),
the first end is attached to the first gate insulating layer (Zeng Fig. 1, depicting first end attached to first gate insulating layer 22),
and the second end is aligned with an end of the second active layer in a direction perpendicular to the surface of the substrate (Zeng Fig. 1, depicting second end aligned with an end of second active layer 13 where alignment is interpreted as the second active layer and end of gate electrode, having overlapping orthogonal projection on the substrate).
RE: Claim 3. Zeng teaches the display panel of claim 1.
Zeng further teaches the display panel wherein an end of the second gate electrode is attached to the first gate insulating layer (Zeng Fig. 1, depicts second gate electrode (11) attached to first gate insulating layer (22)),
and another end of the second gate electrode is aligned with an end of the second active layer (Zeng Fig. 1, depicts an end of second gate electrode (11) aligned with an end of the second active layer (13)).
RE: Claim 8. Zeng teaches the display panel of claim 1.
Zeng further teaches the display panel wherein the first transistor is a photosensitive transistor for sensing external light to generate a sensing signal (Zeng pg. 6 line 7 “the first thin film transistor is turned on in response to the control signal input from the control line, and transmits the data signal input from the data line to the second thin film transistor” Where the examiner notes that transistor active regions are known in the art to be photosensitive where the control signal input can be an electromagnetic wave (light) of appropriate energy.).
RE: Claim 9: Zeng teaches the display panel of claim 8.
The display panel according to claim 8, wherein the second transistor is a drive transistor, and the sensing signal is transmitted to the second gate electrode of the drive transistor through the first source electrode or the first drain electrode of the photosensitive transistor and the connection line ( (Zeng pg. 5 Line 39, “The second thin film transistor is an oxide thin film transistor, which drives the electroluminescent device to emit light in response to the data signal” Where the examiner interprets this description as describing a drive transistor as is known in the art.).
RE: Claim 10: Zeng teaches the display panel of claim 1
Zeng further teaches the display panel wherein each of the first gate electrode, the first source electrode, the first drain electrode, the second gate electrode, the second source electrode, and the second drain electrode is made of a metal material (Zeng pg. 7 Line 35, pg. 12 Line 4 “material of the first gate may be Cu One of Al, Al, and Mo may also be a combined stack including at least two of Cu, Al, and Mo… a material layer is deposited on the gate insulating layer and patterned to form a first source electrode, a first drain electrode, and a second gate electrode. The material of the second gate electrode may be one of Cu, Al, and Mo” Where the examiner notes that the second gate electrode is made of the same material layer as the first source and drain and are therefore also made of metal).
RE: Claim 11. Zeng teaches the display device of claim 1.
Zeng further teaches the display panel wherein the first transistor is of N-type or P-type, and the second transistor is of N-type or P-type (Zeng pg. 3 Line 29, “a first thin film transistor and a second thin film transistor, wherein the first thin film transistor is an oxide thin film transistor, and transmits the input data signal to the input control signal in response to the input control signal” Where the examiner notes that a transistor is known in the art to have active layers that are either P-Type or N-Type).
RE: Independent Claim 12.
Zeng teaches a method of fabricating a display panel, comprising: providing a substrate; depositing a first gate electrode of a first transistor on the substrate (Zeng pg. 11 Line 17 “a gate material layer is deposited on the substrate and patterned to form a first gate”);
depositing a first gate insulating layer on a side of the first gate electrode away from the substrate (Zeng pg. 11 Lin 23 “a gate insulating layer 22 covering the first gate 21 and the substrate 10 is formed”;
depositing a first active layer of the first transistor on a side of the first gate insulating layer away from the substrate (Zeng pg. 11 Line 30, “he first active layer 23 of the first thin film transistor is formed on the gate insulating layer 22”);
depositing a second metal layer on a side of each of the first active layer and the first gate insulating layer away from the substrate (Zeng pg. 12 Line 4 “a material layer is deposited on the gate insulating layer and patterned to form a first source electrode, a first drain electrode, and a
second gate electrode. The material of the second gate electrode may be one of Cu, Al, and Mo”);
patterning the second metal layer to form a first source electrode of the first transistor, a first drain electrode of the first transistor and a second gate electrode of a second transistor that are arranged at intervals, and a connection line for electrically connecting the second gate electrode to the first source electrode or the first drain electrode (Zeng pg. 12 Line 4 “a material layer is deposited on the gate insulating layer and patterned to form a first source electrode, a first drain electrode, and a
second gate electrode. The material of the second gate electrode may be one of Cu, Al, and Mo”);
forming a second gate insulating layer on a side of each of the first source electrode, the first drain electrode and the second gate electrode away from the substrate (Zeng pg. 12 Line 10 “a first gate insulating layer 121 covering the first source electrode 24, the first drain electrode 25, the second gate electrode 11, the first active layer 23 and the gate insulating layer 22 is Formed”;
forming a second active layer on a side of the second gate insulating layer away from the substrate (Zeng pg. 12 Line 38 “a second active layer 13 of the second thin film transistor is formed on the second gate insulating layer 123,”);
depositing a third metal layer on a side of the second active layer away from the substrate (Zeng pg. 12 Line 5, where the examiner interprets that the same deposition process for the first source and drain electrodes applies to the second source and drain electrodes);
and patterning the third metal layer to form a second drain electrode of the second transistor and a second source electrode of the second transistor (Zeng pg. 13 Line 6 “the second source 14 and the second drain 15 of the second thin film transistor are formed on the second gate insulating layer 123, and the second source 14 and the second The drain 15 is electrically connected to the second active layer 13 respectively”).
wherein the second gate electrode has a first end and a second end opposite to each other in a direction parallel to a surface of the substrate (Zeng Fig. 1 depicting second gate electrode 11, having first end and second end in horizontal direction (parallel to the substrate)),
the first end is attached to the first gate insulating layer (Zeng Fig. 1, depicting first end attached to first gate insulating layer 22),
and the second end is aligned with an end of the second active layer in a direction perpendicular to the surface of the substrate (Zeng Fig. 1, depicting second end aligned with an end of second active layer 13 where alignment is interpreted as the second active layer and end of gate electrode, having overlapping orthogonal projection on the substrate).
RE: Claim 13: Zeng teaches the display panel of claim 12.
Zeng teaches the method of fabricating the display panel wherein the first active layer is formed using a first photomask (Zeng pg. 11 Line 33 “an active layer material layer is deposited on the gate insulating layer and patterned to form the first active layer of the first thin film transistor” see pg. 5 Line 30, "patterning process" generally includes the steps of photoresist coating, exposure, development, etching, and photoresist stripping. The expression "patterning process at one time" means a process of forming patterned layers, parts, components, etc., using one mask.”),
and the first source electrode, the first drain electrode ,and the second gate electrode and the connection line are formed using a second photomask (Zeng pg. 12 Line 4 “a material layer is deposited on the gate insulating layer and patterned to form a first source electrode, a first drain electrode, and a second gate electrode. The material of the second gate electrode may be one of Cu, Al, and Mo”).
Where the examiner interprets separate deposition and patterning steps as implementing different photomasks.
RE: Claim 15: Zeng teaches the display panel of claim 12.
Zeng further teaches the method of fabricating the display panel wherein the second drain electrode and the second source electrode are formed using a third photomask (Zeng pg. 13 Line 6, “the second source 14 and the second drain 15 of the second thin film transistor are formed on the second gate insulating layer 123, and the second source 14 and the second The drain 15 is electrically connected to the second active layer 13 respectively” Where the examiner interprets that a separate deposition step would require a separate mask or a third photomasks.),
and the third photomask is a halftone mask (Zeng pg. 13 Line 35 “the mask used in the mask process may be a halftone mask (HalfToneMask)”).
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 4, and 17-20, are rejected under 35 U.S.C. 103 as being unpatentable over Zeng and in further view of Luo (US 20240038783 A1), hereinafter referred to as Luo.
RE: Claim 4. Zeng teaches the display panel of claim 1.
Zeng further teaches the display panel wherein the display panel further comprises: a planarization layer arranged on a side of each of the second source electrode and the second drain electrode away from the substrate (Zeng Fig. 1, pg. 9 Line 25 “The planarization layer 16 covering the second source 14, the second drain 15, the second active layer 13 and the second gate insulating layer 122”),
Zeng fails to teach the display panel wherein the planarization layer is provided with a via hole exposing at least one of the second source electrode or the second drain electrode; and a first metal layer arranged on the planarization layer, wherein the first metal layer extends into the via hole to be connected to the at least one of the second source electrode or the second drain electrode.
However, in a similar field of endeavor, Luo teaches a planarization layer 50, wherein the planarization layer is provided with a via hole exposing at least one of the source electrode or the drain electrode (Luo Fig. 2G, planarization layer 50 with via hole 51, exposing source or drain electrode 24);
and a first metal layer arranged on the planarization layer (Luo Fig. 2H, a first metal layer 60 on the planarization layer 50),
wherein the first metal layer extends into the via hole to be connected to the at least one of the second source electrode or the second drain electrode (Luo fig. 2H, metal layer 60 extends into via ole 51, connecting to source or drain 24).
Therefore, it would have been obvious to a person having ordinary skill in the art, prior to the effective filing date of the claimed invention, to apply the teachings of Luo to the disclosure of Zeng, the planarization layer could have a via hole with a metallization layer to create electrical contact to the source and drain contacts with the obvious result of being able to establish an electrical connection. This is obvious to try as this is a known way of making interlevel connections using known methods in the art as taught by Luo (Luo Fig. 2H 2H).
RE: Claim 17: Zeng teaches the method of fabricating the display panel of 12.
Zeng further teaches the method of fabricating the display panel further comprising: depositing a planarization layer on a side of each of the second source electrode and the second drain electrode away from the substrate (Zeng pg. 13 Line 13 “a planarization layer 16 covering the second source electrode 14, the second drain electrode 15, the second active layer 13, and the second gate insulating layer 122 is formed”;
Zeng fails to teach the method further comprising etching a part of the planarization layer opposite to at least one of the second source electrode or the second drain electrode to form a via hole.
However, in a related field of endeavor, Luo teaches a method of fabricating a display panel including etching a part of the planarization layer opposite to at least one of the second source electrode or the second drain electrode to form a via hole (Luo Fig. 2C, formation of via hole 42 and 41, wherein the planarization layer 40 is patterned [0065], with patterning process disclosed to include etching [0062], where the etching is understood in the art as a process that usually initiates on a side opposite to at least one of the second source electrode or second drain electrode as etching is only possible through the exposure of the target surface with an etchant.)
Therefore, it would have been obvious to a person having ordinary skill in the art, prior to the effective filing date of the claimed invention, to apply the teachings of Luo to the disclosure of Zeng, in order to implement an etching step to form a via hole in the planarization layer. This is obvious to try as the invention of Zeng includes an electroluminescent display device 30 on top of the driving transistor, and a via hole is a well-known implementation in the art to establish an electrical connection as taught by Luo.
RE: Claim 18: The combined disclosure of Zeng and Luo teaches the method of fabricating the display panel of claim 17.
Zeng further teaches the method of fabricating the display panel wherein the planarization layer and the via hole are formed using a fourth photomask (Zeng pg. 5 Line 30 “"patterning process" generally includes the steps of photoresist coating, exposure, development, etching, and photoresist stripping. The expression "patterning process at one time" means a process of forming patterned layers, parts, components, etc., using one mask.” Where the examiner interprets this as an indication that each separate patterning process is using a separate mask).
RE: Claim 19: The combined disclosure of Zeng and Luo teaches the method of fabricating the display panel of claim 17.
Zeng fails to teach the method of fabricating the display panel further comprising: filling the via hole with a first metal layer.
However, in a related field of endeavor, Luo teaches filling a via hole with a first metal layer (Luo Fig. 2G to 2H).
Therefore, it would have been obvious to a person having ordinary skill in the art, prior to the effective filing date of the claimed invention, to apply the teachings of Luo to the disclosure of Zeng, in order to realize that via holes could be filled by metal layers to establish electrical connections. This is obvious to try as the invention of Zeng includes an electroluminescent display device 30 on top of the driving transistor, and a via hole is a well-known implementation in the art to establish an electrical connection as taught by Luo
RE: Claim 20: The combined disclosure of Zeng and Luo teaches the method of fabricating the display panel of claim 19.
Zeng further teaches the method of fabricating the display panel wherein the via hole is filled with the first metal layer using a fifth photomask (Zeng pg. 5 Line 30 “"patterning process" generally includes the steps of photoresist coating, exposure, development, etching, and photoresist stripping. The expression "patterning process at one time" means a process of forming patterned layers, parts, components, etc., using one mask.” Where the examiner interprets this as an indication that each separate patterning process is using a separate mask)..
Claim 7, is rejected under 35 U.S.C. 103 as being unpatentable over Zeng and in further view of Feng et al. (US 20200044092 A1), hereinafter referred to as Feng.
RE: Claim 7. Zeng teaches the display panel of claim 1.
Zeng further teaches the display panel wherein the second active layer is made of an oxide semiconductor material (Zeng pg. 9 Line 15 “second active layer is one of IGZO, IZO, and IGZTO”.
Zeng fails to teach the display panel wherein the first active layer is made of an amorphous silicon material.
However, in a related field of endeavor, Feng teaches the display panel wherein the first active layer is made of an amorphous silicon material, and the second active layer is made of an oxide semiconductor material (Feng [0039], [0054], [0059] “active layer ( e.g., polysilicon, amorphous silicon, or oxide semiconductor, etc.)”), where the examiner interprets this as Feng recognizing that the active layers of the transistors in a display pixel is known to be made of materials that included amorphous silicon and an oxide semiconductor.
Therefore, it would have been obvious to a person having ordinary skill in the art, prior to the effective filing date of the claimed invention, to apply the teaching of Feng to the disclosure of Zeng, in order to be able substitute an amorphous silicon active layer for an oxide semiconductor material as these are known material options for a transistor active layer as taught by Feng.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to EMILIO ARDEO whose telephone number is (703)756-1235. The examiner can normally be reached Mon-Fri EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Brent Fairbanks can be reached at 408-918-7532. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/EMILIO ARDEO/Examiner, Art Unit 2899
/Brent A. Fairbanks/Supervisory Patent Examiner, Art Unit 2899