DETAILED ACTION
This Notice is responsive to communication filed on 03/15/2022.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 09/27/2022 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Election/Restrictions
Applicant’s election without traverse of Group I, reading on claims 1-11, 13, and 16-17 in the reply filed on 03/24/2026 is acknowledged.
Claims 12, 14, 15, and 18-23 withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 03/24/2026.
Claims 12, 14, and 15 are cancelled.
Drawings
Figure 1 should be designated by a legend such as --Prior Art-- because only that which is old is illustrated. See MPEP § 608.02(g). Corrected drawings in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. The replacement sheet(s) should be labeled “Replacement Sheet” in the page header (as per 37 CFR 1.84(c)) so as not to obstruct any portion of the drawing figures. If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
Claim rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 9 recites the limitation "the overlaying electrode layer" in line 3. There is insufficient antecedent basis for this limitation in the claim.
The limitation will be interpreted as “the overlapping electrode layer” moving forward.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, and 9-11 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 20210202672) and further in view of Kishimoto et al. (US 20180047938).
Regarding claim 1, Kim teaches a driving substrate, comprising a component disposing area (Fig. 3C: annotated below), a circuit board binding area (annotated below) and a bending Fig. 3C: BA area located between the component disposing area and the circuit board binding area (shown in Fig. 3C); wherein,
the driving substrate located in the component disposing area and the circuit board binding area comprises a debonding layer Fig. 3C: 101 (para. 0037, “polyimide”), a first buffer layer Fig. 3C: 102, an organic material layer Fig. 3C: 410 (para. 0080, organic insulating material), a second buffer layer Fig. 3C: 800 (para. 0077, inorganic insulating material) and a wiring layer Fig. 3C: 920 (para. 0083, Mo, Ti, Cu) which are sequentially arranged in layer configuration;
the driving substrate located in the bending area Fig. 3C: BA comprises the first buffer layer Fig. 3C: 102, an overlapping electrode layer Fig. 3C: 910, the organic material layer Fig. 3C: 410 and the second buffer layer Fig. 3C: 800 which are sequentially arranged in layer configuration;
wherein two ends of the overlapping electrode layer Fig. 3C: 910 respectively extend to the component disposing area and the circuit board binding area (shown in Fig. 3C), and the wiring layer Fig. 3C: 920 of the component disposing area and the wiring layer Fig. 3C: 920 of the circuit board binding area are respectively connected to the overlapping electrode layer Fig. 3C: 910 through via holes (holes corresponding to middle connecting electrode Fig. 3C: 930).
Kim fails to explicitly teach a rigid substrate. However, Kishimoto teaches a driving substrate comprises a rigid substrate Fig. 3A: 301/303 (para. 0092 teaches “rigid glass substrate”; para. 0119 teaches rigid material of lower protection film). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine the teachings of Kim and Kishimoto for the purpose of creating a substrate with antistatic material and effectively reducing or removing static electricity problems (para. 0007), and for providing support for the formation of the semiconductor element (para. 0092).
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Regarding claim 2, Kim teaches the driving substrate according to claim 1, wherein the wiring layer Fig. 3C: 920 comprises a first wiring layer Fig. 3C: 920 formed on the second buffer layer Fig. 3C: 800 in the component disposing area and the circuit board binding area; wherein the first wiring layer Fig. 3C: 920 in the component disposing area is connected to one end of the overlapping electrode layer Fig. 3C: 910 through a first via hole passing through the second buffer layer Fig. 3C: 800 and the organic material layer Fig. 3C: 410; and the first wiring layer Fig. 3C: 920 in the circuit board binding area is connected to the other end of the overlapping electrode layer Fig. 3C: 910 through a second via hole passing through the second buffer layer Fig. 3C: 800 and the organic material layer Fig. 3C: 410 (holes corresponding to middle connecting electrode Fig. 3C: 930).
Regarding claim 3, Kim teaches the driving substrate according to claim 2, wherein the driving substrate located in the component disposing area and the circuit board binding area further comprises a planarization layer Fig. 3C: 890 covering the first wiring layer Fig. 3C: 920 and the second buffer layer Fig. 3C: 800 located in the component disposing area and the circuit board binding area.
Regarding claim 4, Kim teaches the driving substrate according to claim 3, wherein the driving substrate located in the component disposing area and the circuit board binding area further comprises a third buffer layer Fig. 3C: 890 (para. 0078 discloses the insulating layer 890 may have an organic and inorganic layer, i.e. 2 or more layers), covering the planarization layer Fig. 3C: 890, and the first wiring layer Fig. 3C: 920 is partially exposed (marked out by Fig. 3C: 804) out of the planarization layer Fig. 3C: 890 (organic) and the third buffer layer Fig. 3C: 890 (inorganic).
Regarding claim 9, Kim teaches the driving substrate according to claim 1, wherein the driving substrate located in the bending area Fig. 3C: BA further comprises the debonding layer Fig. 3C: 101, and the debonding layer Fig. 3C: 101 is located at a side, away from the overlapping electrode layer Fig. 3C: 910, of the first buffer layer Fig. 3C: 102.
Regarding claim 10, Kim teaches the driving substrate according to claim 4, wherein the driving substrate located in the bending area Fig. 3C: BA further comprises the third buffer layer Fig. 3C: 890, and the third buffer layer Fig. 3C: 890 is located at a side, away from the organic material layer Fig. 3C: 410, of the second buffer layer Fig. 3C: 800.
Regarding claim 11, Kishimoto teaches the driving substrate according to claim 1, wherein when the bending area Fig. 3A: 50 is in a non-bent state, the rigid substrate Fig. 3A: 301/303 located in the component disposing area Fig. 3A: 10 and the rigid substrate Fig. 3A: 301/303 located in the circuit board binding area Fig. 3A: 60 are disposed along a same horizontal plane (shown in Fig. 3A); and when the bending area Fig. 3A: 50 is in a bent state, the rigid substrate Fig. 3A: 301/303 located in the component disposing area Fig. 3A: 10 is bonded to the rigid substrate Fig. 3A: 301/303 located in the circuit board binding area Fig. 3A: 60 (shown in Fig. 3B). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combined the teachings of Kim and Kishimoto to develop a device that is capable of bending/folding a portion of a display device (para. 0004), while reducing static electricity generated that may cause a displayed image to be non-uniform (para. 0006).
Claims 5-8, 16, and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 20210202672) and Kishimoto et al. (US 20180047938) as applied to claim 1 above, and further in view of Park et al. (US 20190123114).
Regarding claim 5, although Kim and Kishimoto teach the substantial features of the claimed invention, they fail to explicitly teach the driving substrate according to claim 4, wherein a first opening passing through the third buffer layer and the planarization layer is formed in a position corresponding to the first wiring layer of the component disposing area, and the first opening is configured to connect light emitting components to the first wiring layer; and a second opening passing through the third buffer layer and the planarization layer is formed in a position corresponding to the first wiring layer of the circuit board binding area, and the second opening is configured to connect a circuit board to the first wiring layer. However, Park teaches wherein a first opening (annotated below) passing through the third buffer layer Fig. 2: 180 and the planarization layer Fig. 2: 160 is formed in a position corresponding to the first wiring layer Fig. 2: CLc of the component disposing area, and the first opening is configured to connect light emitting components Fig. 2: OLED to the first wiring layer Fig. 2: CLc (para. 0076 teaches all CL wires are connected; para. 0075 also teaches DL connections with connection lines CL and semiconductor layer 154); and a second opening (annotated below) passing through the third buffer layer Fig. 2: 180 and the planarization layer Fig. 2: 160 is formed in a position corresponding to the first wiring layer Fig. 2: CLa of the circuit board binding area, and the second opening is configured to connect a circuit board Fig. 2: 20 to the first wiring layer Fig. 2: CLa (para. 0047). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine the teachings of Kim, Kishimoto, and Park for the purpose of providing data signals to the pad portion of the display panel (para. 0015).
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Regarding claim 6, although Kim and Kishimoto teach the substantial features of the claimed invention, they fail to explicitly teach the driving substrate according to claim 3, wherein the wiring layer further comprises a second wiring layer formed on the planarization layer of the component disposing area, and the second wiring layer is connected to the first wiring layer through a third via hole passing through the planarization layer; and the driving substrate located in the component disposing area and the circuit board binding area further comprises a third buffer layer covering the planarization layer and the second wiring layer, and the second wiring layer is partially exposed out of the third buffer layer. However, Park teaches wherein the wiring layer Fig. 2: CL further comprises a second wiring layer Fig. 2: CLb formed on the planarization layer Fig. 2: 160 of the component disposing area, and the second wiring layer Fig. 2: CLb is connected to the first wiring layer Fig. 2: CLc through a third via hole (annotated Fig. 2 below) passing through the planarization layer Fig. 2: 160; and the driving substrate located in the component disposing area and the circuit board binding area further comprises a third buffer layer Fig. 2: 180 covering the planarization layer Fig. 2: 160 and the second wiring layer Fig. 2: CLb, and the second wiring layer Fig. 2: CLb is partially exposed out of the third buffer layer Fig. 2: 180 (exposed at the regions with Fig. 2: CB and 400).
Regarding claim 7, although Kim and Kishimoto teach the substantial features of the claimed invention, they fail to explicitly teach the driving substrate according to claim 6, wherein a third opening passing through the third buffer layer is formed in a position corresponding to the second wiring layer in the component disposing area, and the third opening is configured to connect the light emitting components to the second wiring layer. However, Park teaches wherein a third opening (annotated) passing through the third buffer layer Fig. 2: 180 is formed in a position corresponding to the second wiring layer Fig. 2: CLb in the component disposing area, and the third opening is configured to connect the light emitting components Fig. 2: OLED to the second wiring layer Fig. 2: CLb.
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Regarding claim 8, although Kim and Kishimoto teach the substantial features of the claimed invention, they fail to explicitly teach the driving substrate according to claim 7, wherein an orthographic projection of the third opening on the rigid substrate overlaps with an orthographic projection of a top surface of the second wiring layer on the rigid substrate; or the orthographic projection of the third opening on the rigid substrate is located within the orthographic projection of the top surface of the second wiring layer on the rigid substrate; wherein the top surface of the second wiring layer is a surface of the second wiring layer away from the first wiring layer. However, Park teaches wherein an orthographic projection of the third opening on the rigid substrate overlaps with an orthographic projection of a top surface of the second wiring layer on the rigid substrate; or the orthographic projection of the third opening on the rigid substrate is located within the orthographic projection of the top surface of the second wiring layer Fig. 2: CLb on the rigid substrate; wherein the top surface of the second wiring layer Fig. 2: CLb is a surface of the second wiring layer Fig. 2: CLb away from the first wiring layer Fig. 2: CLc. In Fig. 2, Park discloses the annotated third opening with a width that lies within the width of the top surface of the second wiring layer CLb.
Regarding claim 16, although Kim and Kishimoto teach the substantial features of the claimed invention, they fail to explicitly teach a light emitting apparatus, wherein the light emitting apparatus comprises a circuit board, light emitting components and the driving substrate according to claim 1, the light emitting components are connected to the wiring layer in the component disposing area, and the circuit board is connected to the wiring layer in the circuit board binding area. However, Park teaches a light emitting apparatus, wherein the light emitting apparatus comprises a circuit board Fig. 2: 20, light emitting components Fig. 2: OLED and the driving substrate according to claim 1 (as disclosed in section 8), the light emitting components Fig. 2: OLED are connected to the wiring layer Fig. 2: CLc in the component disposing area, and the circuit board Fig. 2: 20 is connected to the wiring layer Fig. CLa in the circuit board binding area. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine the teachings of Kim, Kishimoto, and Park for the purpose of displaying an image and generating/transferring electrical signals between the display and non-display area from outside the display device (para. 0042).
Regarding claim 17, although Kim and Kishimoto teach the substantial features of the claimed invention, they fail to explicitly teach the light emitting apparatus according to claim 16, wherein the light emitting apparatus further comprises a first adhesive layer disposed at a side, away from the rigid substrate, of the light emitting components and a second adhesive layer disposed on a side wall of the light emitting components; wherein the first adhesive layer is configured to protect the light emitting components, and the second adhesive layer is configured to avoid a cross color of rays emitted by the light emitting components. However, Park teaches wherein the light emitting apparatus further comprises a first adhesive layer Fig. 2: 390 disposed at a side, away from the rigid substrate, of the light emitting components Fig. 2: OLED and a second adhesive layer Fig. 2: 360 disposed on a side wall of the light emitting components Fig. 2: OLED; wherein the first adhesive layer Fig. 2: 390 is configured to protect the light emitting components (para. 0087), and the second adhesive layer Fig. 2: 360 is configured to avoid a cross color of rays emitted by the light emitting components Fig. 2: OLED. Para. 0084 teaches a pixel defining layer 360 that defines each pixel and acts as a barrier protecting the LED components and managing the light output/leakage.
Allowable Subject Matter
Claim 13 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: Regarding claim 13, the applied prior art neither anticipates no renders obvious the claimed debonding layer made of polyimide material wherein a thickness of the debonding layer is 30nm to 100nm, in combination with the remaining claimed limitations.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NKECHINYERE ESIABA whose telephone number is (571)272-0720. The examiner can normally be reached Monday - Friday 10am-5pm EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kretelia Graham can be reached at (571) 272-5055. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Nkechinyere Esiaba/Examiner, Art Unit 2817
/Kretelia Graham/Supervisory Patent Examiner, Art Unit 2817 April 10, 2026
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