DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The amendment filed 22 October 2025 has been entered. Claims 1-5, 8-14, 16-19 and 21-24 remain pending in the application. Applicant’s amendments to the specification have overcome the Abstract and specification objections previously set forth in the Non-Final Office Action mailed 05 August 2025.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3, 9, 11-14, 16-17, 19, 21-23 are rejected under 35 U.S.C. 103 as being unpatentable over US 10325120 B2 Suwald (hereinafter “Suwald”).
Regarding claim 1, Suwald teaches an electronic device comprising:
a substrate (Fig. 3, 302; Col. 4, lines 47-59) on which there is provided at least one electrically conductive connection pad (Fig. 3, 318; Col. 4, lines 54-59, 63-66);
an electronic circuit (Fig. 3, 300; Col. 4, lines 47-52) comprising memory circuitry (Fig. 11, 908 in 300; Col. 7, lines 64-67, Col. 8, lines 1-6, referred to as 1108) having a number of memory contacts (Fig. 3, 304, 306, lines 49-56); and
a layer (Fig. 3, 100; Col. 4, lines 47-59; Col. 4, lines 16-38, description with respect to Fig. 1), provided between the substrate and the electronic circuit (Fig. 3, 100 between 302 and 300), wherein the layer comprises an electrically insulating medium (Col. 4, lines 16-20, resin) containing a spatial distribution of conductive elements (Fig. 3, hexagonal shapes; Fig. 1, 102; Col. 4, lines 16-35) that is at least partially random (Col. 4, 18-26), whereby the layer is conductive through the thickness of the layer (Fig. 3, height of “100” extending from 302 to 312) at locations where a conductive element extends through the thickness of the layer (Col. 5, lines 10-21, conductive paths), and whereby the layer is non-conductive at locations where no conductive element extends through the thickness of the layer (Col. 5, lines 10-21, no conductive paths exist);
wherein each memory contact (Fig. 3, 304, 306, lines 49-56): is arranged for electrical connection (Fig. 3, 304 and 306 connected to 318 via layers 100, 312, 310, 308; Col. 4, lines 47-59) with the at least one connection pad (Fig. 3, 318; Col. 4, lines 54-59, 63-66), through the thickness of the layer (Fig. 3, height of “100” extending from 302 to 312), when at least one of the conductive elements extends a thickness of the layer (Col. 5, lines 10-21, conductive paths) between that memory contact (Fig. 3, 304 and 306 through extension of 314 and 316; Col. 4, lines 47-59) and the at least one connection pad (Fig. 3, 318); and is arranged for electrical insulation from the at least one connection pad when no conductive elements extend the thickness of the layer (Col. 5, lines 10-21, no conductive paths exist) between that memory contact (Fig. 3, 304 and 306 through extension of 314 and 316; Col. 4, lines 47-59) and the at least one connection pad (Fig. 3, 318).
In a separate embodiment, Suwald teaches:
whereby a selection of the memory contacts (Figs. 4, 5, 6, 7, 402, 404, 406; Col. 5, lines 7-21, 41-56), that is at least partially random (Col. 5, lines 31-35), have a connected electrical connection status in which they are electrically connected to the at least one connection pad (Figs. 4, 5, 6, 7, I1, I2; Col. 5, lines 7-21, 41-51, electrical contact established, status – current flows) and other memory contacts have a disconnected electrical connection status in which they are electrically insulated from the at least one connection pad (Figs. 4, 5, 6, 7, In; Col. 5, lines 14-31, electrical contact not established, status – no current flows), in dependence on the spatial distribution of conductive elements (Col. 5, lines 31-35); and
wherein the respective connected (Figs. 4, 5, 6, 7, I1, I2; Col. 5, lines 7-21, 41-51, electrical contact established, status – current flows) or disconnected electrical connection status of each of a plurality of the memory contacts (Figs. 4, 5, 6, 7, In; Col. 5, lines 14-31, electrical contact not established, status – no current flows) configures the memory circuitry (Fig. 9, 902; Col. 6, lines 44-45) to store a representation of the respective electrical connection status of each of the plurality of the memory contacts (Col. 6, lines 58-67; Fig. 10, 1008; Col. 7, lines 23-27).
It would have been obvious to modify with the alternative embodiments as by incorporating electrodes into the integrated circuit and substrate system allows it to develop conductive paths by applying drive currents (Col. 4, lines 66-67; Col. 5, lines 1-16). A common issue for integrated circuits of security controller chips is verifying the authenticity of assembly (Col. 3, lines 14-18). However, forming these conductive paths where electrical contacts are made, and sometimes not due to the distribution of conductive elements, allows Suwald’s original integrated circuit and substrate system to provide functionality of a physical unclonable function (Col. 6, lines 9-15; Col. 3, lines 50-58). The physical unclonable function may increase the probability the assembly identification is a unique signature for IC-substrate assembly identification, and thus can more easily verify the authenticity of the assembly by this derivation for security purposes (Col. 3, lines 50-58).
Regarding claim 3, in addition to the teachings addressed in the claim 1 analysis, the rejection of claim 1 is incorporated and Suwald teaches an electronic device wherein
the electronic circuit and the memory circuitry (see claim 1 mapping).
In a separate embodiment, Suwald teaches to generate a number (Figs. 5, 6, 7, currents accumulated in 318 and received by receiving electrode 408; Col. 5, lines 1-21, U in Fig. 5-6, Col. 5, lines 44-61; Voltage in Fig. 7; Col. 5, lines 62-67) corresponding to the representation of the respective electrical connection status (Figs. 4, 5, 6, 7, I1, I2; Col. 5, lines 7-21, 41-51, electrical contact established, status – current flows) (Figs. 4, 5, 6, 7, In; Col. 5, lines 14-31, electrical contact not established, status – no current flows) of each of the plurality of the memory contacts stored (Col. 6, lines 58-67; Fig. 10, 1008; Col. 7, lines 23-27).
It would have been obvious to modify with the alternative embodiments as by incorporating electrodes into the integrated circuit and substrate system allows it to develop conductive paths by applying drive currents (Col. 4, lines 66-67; Col. 5, lines 1-16). A common issue for integrated circuits of security controller chips is verifying the authenticity of assembly (Col. 3, lines 14-18). However, forming these conductive paths where electrical contacts are made, and sometimes not due to the distribution of conductive elements, allows Suwald’s original integrated circuit and substrate system to provide functionality of a physical unclonable function to generate the number (Col. 6, lines 9-15; Col. 3, lines 50-58). The physical unclonable function may increase the probability the assembly identification is a unique signature for IC-substrate assembly identification, and thus can more easily verify the authenticity of the assembly by this derivation for security purposes (Col. 3, lines 50-58).
Regarding claim 9, in addition to the teachings addressed in the claim 3 analysis, the rejection of claim 3 is incorporated and Suwald teaches an electronic device wherein:
the electronic circuit is configured to store an identifier wherein the identifier is based on the generated number (Col. 5 lines 16-21; Col. 7, lines 16-20, 36-40; Col. 8, lines 17-30).
Regarding claim 11, in addition to the teachings addressed in the claim 1 analysis, the rejection of claim 1 is incorporated and Suwald teaches an electronic device wherein:
the memory contacts (Fig. 3, 304, 306, lines 49-56) have a size and spacing that is preconfigured to provide, on average, a predetermined proportion of memory contacts (Col. 4, lines 25-38) that are electrically connected to the at least one connection pad (Fig. 3, 318; Col. 4, lines 54-59, 63-66) when the electronic device is assembled (Col. 5, lines 16-21).
Regarding claim 12, in addition to the teachings addressed in the claim 1 analysis, the rejection of claim 1 is incorporated and Suwald teaches an electronic device wherein:
the layer is formed of at least one anisotropic conductive material (Col. 3, lines 59-62).
Regarding claim 13, in addition to the teachings addressed in the claim 1 analysis, the rejection of claim 1 is incorporated and Suwald teaches an electronic device wherein:
each conductive element comprises at least one conductive particle (Col. 4, lines 16-25).
Regarding claim 14, in addition to the teachings addressed in the claim 13 analysis, the rejection of claim 13 is incorporated and Suwald teaches an electronic device wherein:
the conductive particles (Fig. 1, 102; Col. 4, lines 16-22) have at least one of: a concentration that is preconfigured to provide, on average (Col. 4, lines 22-26), a predetermined proportion of memory contacts (Fig. 3, 304, 306, lines 49-56) that are electrically connected to the at least one connection pad (Fig. 3, 318; Col. 4, lines 54-59, 63-66) when the electronic device is assembled (Col. 3, lines 44-58); or a concentration uniformity that is preconfigured to vary within the layer in a manner that is at least partially random (Col. 3, lines 47-58; Col. 4, lines 20-25).
Regarding claim 16, in addition to the teachings addressed in the claim 1 analysis, the rejection of claim 1 is incorporated and Suwald teaches an electronic device wherein:
said electronic circuit is an integrated circuit (Col. 3, lines 1-26; Col. 7, lines 60-64).
Regarding claim 17, in addition to the teachings addressed in the claim 1 analysis, the rejection of claim 1 is incorporated and Suwald teaches an electronic device wherein:
at least one application circuit is provided on the substrate (Col. 3, lines 65-67; Col. 4, lines 1-4).
Regarding claim 19, in addition to the teachings addressed in the claim 1 analysis, the rejection of claim 1 is incorporated and equally applies as claim 19 recites similar limitations.
Claim 21 is directed to a circuit which recites similar limitations to the apparatus of claim 1. The claim 1 analysis equally applies, and claim 21 is similarly rejected.
Claims 22-23 are directed to a method that would be performed by the apparatus of claims 1 and 12. The claims 1 and 12 analysis equally applies, and claims 22-23 are similarly rejected.
Additionally in claim 22, Suwald teaches:
depositing a material, on a respective surface of at least one of the substrate and the electronic circuit, for forming a layer (Col. 3, lines 1-5, 24-31, 59-62);
assembling the substrate, the material and the electronic circuit to form the layer between the substrate and the electronic circuit, whereby to form the electronic device (Col. 3, lines 12-14, 26-41, 50-58).
Additionally in claim 23, Suwald teaches:
wherein the method forms part of a procedure for securing the electronic circuit to the substrate using the anisotropic conductive adhesive (Col. 3, lines 22-31, 59-65).
Claims 2, 4, 5, 8 are rejected under 35 U.S.C. 103 as being unpatentable over Suwald as applied to claim 1 above, and further in view of US 10891366 B1 Wu et al. (hereinafter “Wu”).
Regarding claim 2, in addition to the teachings addressed in the claim 1 analysis, the rejection of claim 1 is incorporated and Suwald teaches an electronic device wherein:
the representation of the respective electrical connection status of each of the plurality of the memory contacts comprises a respective bit stored in the memory circuit representing the electrical connection status of each of the plurality of the memory contacts (see claim 1 mapping).
Although Suwald teaches the connections, they are silent with disclosing the statutes as respective bits.
Wu teaches a respective bit (Col. 55, lines 47-52, “1”s and “0”s).
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Suwald’s integrated circuit and substrate system with Wu’s binary techniques because they are in the claimed invention’s same field of endeavor of integrated circuit design [Abstract]. It would have been obvious to one of ordinary skill in the art to try the binary techniques, as it is a known representation in the art. By providing designers the capability of utilizing binary as a representation for their signals (Col. 55, lines 47-55), they are better equipped to effectively perform post-processing on the binary data through specialized binary post-processing modules as necessitated by the application. Further, it would have been obvious to try this representation as it is known in the art, and through having more control over the data types can positively affect the ease of computations following it.
Regarding claim 4, in addition to the teachings addressed in the claim 3 analysis, the rejection of claim 3 is incorporated and Suwald teaches an electronic device wherein:
the number corresponding to the representation of the respective electrical connection status of each of the plurality the memory contacts stored in the memory circuitry corresponds directly to a binary sequence corresponding to the representation of the respective electrical connection status of each of the plurality of the memory contacts (see claim 1 mapping).
Although Suwald teaches the connections, they are silent with disclosing the statutes as binary sequences.
Wu teaches a binary sequence (Col. 55, lines 53-55).
The motivation to combine provided with respect to claim 2 equally applies.
Regarding claim 5, in addition to the teachings addressed in the claim 3 analysis, the rejection of claim 3 is incorporated and Suwald teaches an electronic device wherein:
the electronic circuit is configured to generate the number corresponding to the representation of the respective electrical connection status of each of the plurality of the memory contacts by applying at least one of: a mathematical function either directly or indirectly to the representation (Fig. 5,
U
=
R
*
∑
n
=
1
n
I
i
; Fig. 6,
U
=
(
t
*
∑
n
=
1
n
I
i
)
/
C
; ); a cryptographic function directly or indirectly to the representation; or a random number generator directly or indirectly to the representation (see claim 1 mapping).
Although Suwald teaches the connections, they are silent with disclosing a cryptographic function directly or indirectly to the representation; or a random number generator directly or indirectly.
Wu teaches cryptographic function directly or indirectly to the representation (Col. 65, lines 50-58; Col. 33, lines 23-38); or a random number generator directly or indirectly (Fig. 7, 701; Col. 55, lines 26-29).
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Suwald’s integrated circuit and substrate system with Wu’s cryptographic function and random number generator feature because they are in the claimed invention’s same field of endeavor of integrated circuit design [Abstract]. Wu teaches it would have been obvious to try the cryptographic functions, as such is an extension of a particular mathematical formulation yielding a value based on the relationship with the circuit’s existing cryptographic components (Col. 65, lines 36-39), and would have been obvious to try with predictable results given the finite number of values that could be computed from formulations. Modifying Suwald’s integrated circuit and substrate system to be of the particular mathematical formulation would have been beneficial, as doing so would allow the designers to configure operations based on the data to be processed and circuitry already existing. Wu teaches it would be beneficial to utilize a random number generator as incorporating this additional hardware can be used for encryption purposes (Col. 65, lines 50-65), thus increasing the security on the chip and protecting it from any attacks.
Regarding claim 8, in addition to the teachings addressed in the claim 1 analysis, the rejection of claim 1 is incorporated and Suwald teaches an electronic device wherein the representation (see claim 1 mapping).
Although Suwald teaches the connections, they are silent with disclosing provided as at least one seed to a random number generator.
Wu teaches provided as at least one seed to a random number generator (Fig. 7, 701; Col. 55, lines 26-29).
The motivation to combine provided with respect to claim 5 equally applies.
Claims 10, 18, 24 are rejected under 35 U.S.C. 103 as being unpatentable over Suwald as applied to claims 1 and 22 above, and further in view of US 20140310515 A1 Kim et al. (hereinafter “Kim”).
Regarding claim 10, in addition to the teachings addressed in the claim 3 analysis, the rejection of claim 3 is incorporated and Suwald teaches an electronic device wherein the electronic circuit and based on the generated number (see claim 1 mapping).
Although Suwald teaches the electronic circuit, they are silent with disclosing transceiver circuitry for communicating with at least one communication device, wherein the transceiver circuitry is configured to time communications based on the generated number.
Kim teaches a transceiver circuitry (Fig. 1, 130, [0056]) for communicating with at least one communication device ([0056] “another device (not shown)”), wherein the transceiver circuitry is configured to time communications ([0052], [0056], [0061], [0111-0114] M2M communications) based on the generated number.
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Suwald’s integrated circuit and substrate system with Kim’s transceiver circuit because they are in the claimed invention’s same field of endeavor of integrated circuit design ([0086]). It would have been obvious to one of ordinary skill in the art to implement the transceiver, as it allows the system to perform more effective communications between components ([0002]). Making this modification would be beneficial, as Suwald’s integrated circuit and substrate system now has support for communicating data considered to be dangerous for humans to handle ([0003]) and ensuring that such data is safe from external security attacks ([0017-0018]), thus making it more flexible to processing different types of data and having a greater use in other applications.
Regarding claim 18, in addition to the teachings addressed in the claim 1 analysis, the rejection of claim 1 is incorporated and Suwald teaches an electronic device wherein the electronic circuit (see claim 1 mapping).
Although Suwald teaches the electronic circuit, they are silent with disclosing forming part of a radio frequency identification tag.
Kim teaches forming part of a radio frequency identification tag ([0007]).
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Suwald’s integrated circuit and substrate system with Kim’s radio frequency identification tag because they are in the claimed invention’s same field of endeavor of integrated circuit design ([0086]). It would have been obvious to one of ordinary skill in the art to implement the radio frequency identification tag as part of the transceiver, as it allows the system to perform more effective communications between components ([0002], [0007]). Making this modification would be beneficial, as Suwald’s integrated circuit and substrate system now has support for communicating data considered to be dangerous for humans to handle ([0003]) and ensuring that such data is safe from external security attacks ([0017-0018]), thus making it more flexible to processing different types of data and having a greater use in other applications via the radio frequency identification tag implementation through the communications.
Claim 24 is directed to a method that would be performed by the apparatus of claim 18. The claim 18 analysis equally applies and claim 24 is similarly rejected.
Response to Arguments
Abstract. The objections are withdrawn based on the amendment to the Abstract.
Specification. The objections are withdrawn based on the amendment to the specification.
35 USC 103. The rejections are maintained, Applicant argues the following in substance:
Argument 1. Applicant asserts Suwald does not disclose memory circuitry in which the respective connected or disconnected electrical connection status of each of a plurality of memory contacts, arising from a (pseudo)random distribution of conductive elements in a layer between the memory contacts and a substrate,
configures the memory circuitry to store a representation of the respective electrical connection status of each of the plurality of the memory contacts (see Remarks, Pg. 4, Para. 7; Pg. 5, Para. 1).
Examiner respectfully disagrees. Suwald discloses the limitation as recited in claim 1. Further, see response to Arguments 2 and 3 for details regarding particular portions of the cited limitation.
Argument 2. Applicant respectfully disagrees with this reasoning because the "sum of currents" does not (and cannot) provide an indication of the respective electrical connection status of each of the plurality of receiving electrodes (as recited in independent claim 1) and Suwald does not disclose that it does. More specifically, it is not possible to determine, from the "sum of currents" what the connection status is for any individual receiving electrode. In Suwald a respective "sum of currents" is simply measured for a number of different challenge codes to provide a 'response pattern, ' which can then be compared to a response code, to help authenticate the substrate-IC combination or detect tampering. Furthermore, the "sum of currents" of Suwald cannot be used to "[configure] the memory circuitry to store a representation of the respective electrical connection status of each of the plurality of the memory contacts" as claimed (see Remarks, Pg. 7, Para. 1).
Examiner respectfully disagrees. The connection status recited in claim 1 is limited to a connected electrical connection status (Figs. 4, 5, 6, 7, I1, I2; Col. 5, lines 7-21, 41-51, electrical contact established, status – current flows) or a disconnected electrical connection status (Figs. 4, 5, 6, 7, In; Col. 5, lines 14-31, electrical contact not established, status – no current flows). Suwald’s sum of currents is the measurement of these statuses based on the connected and disconnected connections, in which they are influenced by the conductive particles and may be measured or sensed by the receiving electrodes (Col. 7, lines 23-27). Given that the indication of status is based on whether a connection is made or not, the sum of currents is composed of connected and disconnected connections, where both are accounted for by measurement or sense of the electrodes, but the currents summed are those that are connected as they drive current to be summed.
Current is the flow of charges. Suwald’s sense receiving electrodes (Fig. 10, 1008; Col. 7, lines 23-27; Col. 6, lines 58-67) effectively stores the current’s charge by sensing or measuring this flow in the sense receiving electrodes, and generating a response (Fig. 10, 1010; Col. 7, lines 27-33).
Argument 3. Applicant respectfully disagrees with this reasoning because the "memory unit 1108" of Suwald does not include the "contact pads 304, 306" or the "driving electrodes 402, 404, 406" and Suwald does not disclose that it does. Moreover, it is pointed out that Suwald teaches away from this interpretation of these features as it teaches in Fig. 11 that a "memory unit 1108" may be required in addition to the "contact pads 304, 306" or the "driving electrodes 402,404,406" (see Remarks, Pg. 9, Para. 1).
Examiner respectfully disagrees. Claim 1 recites an electronic circuit comprising memory circuitry having a number of memory contacts. However, given the broadest reasonable interpretation of this claim limitation, and further to the extent that there is not a claim interpretation where structure is incorporated by invoking 35 USC 112(f), the term “having” does not appear to explicitly limit the memory circuitry as “including” as Applicant alleges. In light of the specification, there also does not appear to be a definition which one would refer to this meaning.
The memory contacts (Fig. 3, 304, 306, Col. 4, lines 49-56) are a part of the integrated chip (Fig. 3, 300; Col. 4, lines 47-59). The integrated chip which appears in Fig. 11 as ‘300’ contains the memory circuitry (Fig. 11, 908 in 300; Col. 7, lines 64-67, Col. 8, lines 1-6, referred to as 1108). The integrated chip ‘300’ has the memory contacts, and by extension of the integrated circuitry containing the RAM and/or ROM (‘908’ in the figures or ’1108’ in the description), so do they.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MARKUS A VILLANUEVA whose telephone number is (703)756-1603. The examiner can normally be reached M - F 8:30 am - 5:30 pm.
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/MARKUS ANTHONY VILLANUEVA/Examiner, Art Unit 2151
/James Trujillo/Supervisory Patent Examiner, Art Unit 2151
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