DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Status
Previous action: claims 13 through 16, 18, 19, 21 rejected
Present action: claims 13 through 16, 18, 19, 21 rejected
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Rejection Note: Italicized and struck through claim limitations indicate limitations that are not explicitly disclosed in the primary reference, but disclosed in the secondary reference(s).
Claim(s) 13 and 21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Schubert (US 2017/0288087) in view of Shu (US 9312434) in view of King (US 2004/0222357).
Regarding claim 13.
Schubert teaches:
A semiconductor light emitting element assembly comprising: ;
and a semiconductor light emitting element (fig 3d; [para 0058]) including a first etching layer (fig 3a,3d:315; [para 0063]), , a first conductivity-type semiconductor layer (fig 3a,3d:320; [para 0062]), an active layer (fig 3a,3d:325; [para 0063]) on the first conductivity-type semiconductor layer (fig 3a,3d:320; [para 0062]), and a second conductivity-type semiconductor layer (fig 3a,3d:330; [para 0064]) on the active layer (fig 3a,3d:325; [para 0063]), , wherein a concentration of impurities (fig 3a:n++; [para 0061]) in the first etching layer (fig 3a,3d:315; [para 0063]) is higher than the concentration of impurities (fig 3a:n-; [para 0062]) in the first conductivity-type semiconductor layer (fig 3a,3d:320; [para 0062]) , wherein the first etching layer (fig 3a,3d:315; [para 0063]) includes an uneven structure (partially removed porous network; [para 0033,0034]) , and wherein the uneven structure (partially removed porous network; [para 0033,0034]) is configured to prevent the semiconductor light emitting element from being assembled on a surface having the uneven structure during a self-assembly process in a fluid ([para 0032]) (the structure is made by a process that is substantially the same as that the process that the applicant uses to form the disclosed product, therefore the properties made by the process is expected to possess the properties. Uneven structure (roughness) is a property of the product that is dependent on the process and therefore the uneven structure (roughness) disclosed in the prior art is expected to possess the same properties as the uneven structure (roughness) disclosed by the applicant, because surface uneven structure (roughness) is due to the effect of etching on the semiconductor material. Where the claimed and prior art products are identical or substantially identical in structure or composition, or are produced by identical or substantially identical processes, a prima facie case of either anticipation or obviousness has been established. In re Best, 562 F.2d 1252, 1255, 195 USPQ 430, 433 (CCPA 1977). MPEP 2112.III, 2112.0,1.I).
Schubert does not teach an etching protection layer.
Shu teaches:
A semiconductor light emitting element assembly comprising: and a semiconductor light emitting element (fig 3; [column 2 lines 50-55]) including a first etching layer (fig 3:2; [column 3 line 2]), an etching protection layer (fig 3:3-1; [column 3 line 13]) on the first etching layer (fig 3:2; [column 3 line 2]), a first conductivity-type semiconductor layer (fig 3:3-2; [column 3 line 12]) on the etching protection layer (fig 3:3-1; [column 3 line 13]), wherein a concentration of impurities (undoped; [column 3 line 15]) in the etching protection layer (fig 3:3-1; [column 3 line 13]) is lower than a concentration of impurities in the first conductivity-type semiconductor layer (fig 3:3-2; [column 3 line 12]), wherein a concentration of impurities (aluminum) in the first etching layer (fig 3:2; [column 3 line 2]) is higher than the concentration of impurities (undoped) in the concentration of impurities in the etching protection layer (fig 3:3-1; [column 3 line 13]), wherein the first etching layer (fig 3:2; [column 3 line 2])is separated from first conductivity-type semiconductor layer (fig 3:3-2; [column 3 line 12])by the etching protection layer (fig 3:3-1; [column 3 line 13]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide and etching protection layer between the first conductivity type layer and the etching layer in order to buffer the first conductivity type layer and thereby avoid damaging the first conductivity type layer and thereby avoid forming unwanted recombination centers that would reduce device efficiency.
Schubert does not teach an assembly substrate.
King teaches:
An assembly substrate (fig 2b:10; [para 0015])
a semiconductor light emitting element (fig 2c:30; [para 0015])wherein the [etched] structure (fig 2h; [para 0015]) is configured to prevent the semiconductor light emitting element (fig 2c:30; [para 0015]) from being assembled on the assembly substrate (fig 2b:10; [para 0015]) on a surface having the [etched] structure (fig 2h; [para 0015])during a self-assembly process in a fluid (fig 2i,2j; [para 0016]).
It would have been obvious to one of ordinary skill in the before the effective filing date of the claimed invention to provide an assembly substrate so that the devices can be assembled into a large array of light emitters that can the be integrated with other devices
Regarding claim 21
Schubert in view of Shu in view of King teaches the semiconductor light emitting element assembly of claim 13, further:
Shu teaches:
the semiconductor light emitting element further includes a first conductivity-type electrode (fig 3:8; [column 2 line 59]) directly connected to the first conductivity-type semiconductor layer (fig 3:3-2; [column 2 line 57]), and a second conductivity-type electrode (fig 3:7; [column 2 line 55]) connected to the second conductivity-type semiconductor layer (fig 3:6; [para 0059]), and wherein the first conductivity-type semiconductor layer (fig 3:8; [column 2 line 59]) is disposed between the etching protection layer (fig 3:3-1; [column 2 line 56]) and both of the first conductivity-type electrode (fig 3:8; [column 2 line 59]) and the second conductivity-type electrode (fig 3:7; [column 2 line 59]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide electrodes on the semiconductor layers in order to provide voltage to the diode and thereby energize the device.
Claim(s) 14, 15, and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Schubert (US 2017/0288087) in view of Shu (US 9312434) in view of King (US 2004/0222357) as applied to claim 13 and further in view of Horng (US 2010/0136728)
Regarding claim 14.
Schubert in view of Shu in view of King teaches the semiconductor light emitting element assembly of claim 13, above
Schubert in view of Shu in view of King does not teach prominences in a plurality of bands.
Horng teaches:
the uneven structure (fig 9:235; [para 0047]) is configured such that prominences of the uneven structure extend to form a plurality of bands in a direction from a center of a surface of the uneven structure towards an edge of the surface of the uneven structure (fig 9:235; [para 0047]).
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It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for the uneven surface to comprise bands of prominences around a center because the etching process of forming a partially removed porous structure will result in high points (prominences) which will be around the center of the surface
Regarding claim 15.
Schubert in view of Shu in view of King in view of Horng teaches the semiconductor light emitting element assembly of claim 14, above
Horng teaches:
an average thickness of the uneven structure (fig 9:235; [para 0047]) is equal to or greater than an effective distance under which dielectrophoresis force acts during a self-assembly process of the semiconductor light emitting element.
Dielectrophorisis effective distance is variable depending upon the electric charge used. The limitation must distinguish from the prior art in terms of structure rather than function, In re Schreiber, 128 F.3d 1473, 1477-78, 44 USPQ2d 1429, 1431-32 (Fed. Cir. 1997); See also In re Swinehart, 439 F.2d210, 212-13, 169 USPQ 226, 228-29 (CCPA 1971). Claims directed to apparatus must be distinguished from the prior art in terms of structure rather than function. In re Danly, 263 F. 2d 844, 847, 120 USPQ 528, 531 (CCPA 1959). “Apparatus claims cover what a device is, not what a device does.” Hewlett-Packard Co. v. Bausch & Lomb Inc., 909 F. 2d 1464, 1469, 15 USPQ2d 1525, 1528 (Fed. Cir. 1990).
Further, the minimum distance over which dielectrophorisis is effective approaches 0, therefore a thickness greater than 0 (fig 2d) satisfies the claim.
Regarding claim 16.
Schubert in view of Shu in view of King in view of Horng teaches the semiconductor light emitting element assembly of claim 14, above
Schubert teaches:
wherein the first etching layer (fig 3a,3d:315; [para 0063]) includes a surface having a specific pattern, or a rough surface having irregularities (partially removed porous network [para 0033,0034]).
Claim(s) 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Schubert (US 2017/0288087) in view of Shu (US 9312434) in view of King (US 2004/0222357)
Regarding claim 18.
A semiconductor light emitting element assembly comprising: ;
and a semiconductor light emitting element (fig 3d; [para 0058]) including a first etching layer (fig 3a,3d:315; [para 0063]), , a first conductivity-type semiconductor layer (fig 3a,3d:320; [para 0062]) , an active layer (fig 3a,3d:325; [para 0063]) on the first conductivity-type semiconductor layer (fig 3a,3d:320; [para 0062]), and a second conductivity-type semiconductor layer (fig 3a,3d:330; [para 0064]) on the active layer (fig 3a,3d:325; [para 0063]),wherein a concentration of impurities (fig 3a:n++; [para 0061]) in the first etching layer (fig 3a,3d:315; [para 0063]) is higher than the concentration of impurities (fig 3a:n-; [para 0062]) in the first conductivity-type semiconductor layer (fig 3a,3d:320; [para 0062]) , wherein the first etching layer (fig 3a,3d:315; [para 0063]) includes an uneven structure (partially removed porous network; [para 0033,0034]) the uneven structure (partially removed porous network; [para 0033,0034]) including an outermost surface having a specific pattern with protrusions or a rough surface having irregularities, and wherein the uneven structure is configured to prevent the semiconductor light emitting element from being assembled on a surface having the uneven structure during a self-assembly process in a fluid ([para 0032]) (the structure is made by a process that is substantially the same as that the process that the applicant uses to form the disclosed product, therefore the properties made by the process is expected to possess the properties. Uneven structure (roughness) is a property of the product that is dependent on the process and therefore the uneven structure (roughness) disclosed in the prior art is expected to possess the same properties as the uneven structure (roughness) disclosed by the applicant, because surface uneven structure (roughness) is due to the effect of etching on the semiconductor material. Where the claimed and prior art products are identical or substantially identical in structure or composition, or are produced by identical or substantially identical processes, a prima facie case of either anticipation or obviousness has been established. In re Best, 562 F.2d 1252, 1255, 195 USPQ 430, 433 (CCPA 1977). MPEP 2112.III, 2112.0,1.I).)
Schubert does not teach an etching protection layer.
Shu teaches:
A semiconductor light emitting element assembly comprising: a semiconductor light emitting element (fig 3; [column 2 lines 50-55]) including a first etching layer (fig 3:2; [column 3 line 2]), an etching protection layer (fig 3:3-1; [column 3 line 13]) on the first etching layer (fig 3:2; [column 3 line 2]), a first conductivity-type semiconductor layer (fig 3:3-2; [column 3 line 12]) on the etching protection layer (fig 3:3-1; [column 3 line 13]), wherein a concentration of impurities (undoped; [column 3 line 15]) in the etching protection layer (fig 3:3-1; [column 3 line 13]) is lower than a concentration of impurities in the first conductivity-type semiconductor layer (fig 3:3-2; [column 3 line 12]), wherein a concentration of impurities (aluminum) in the first etching layer (fig 3:2; [column 3 line 2]) is higher than the concentration of impurities (undoped) in the first conductivity-type semiconductor layer (fig 3:3-2; [column 3 line 12])and the concentration of impurities in the etching protection layer (fig 3:3-1; [column 3 line 13]),wherein the first etching layer (fig 3:2; [column 3 line 2]) is separated from first conductivity-type semiconductor layer (fig 3:3-2; [column 3 line 12]) by the etching protection layer (fig 3:3-1; [column 3 line 13])
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide and etching protection layer between the first conductivity type layer and the etching layer in order to buffer the first conductivity type layer and thereby avoid damaging the first conductivity type layer and thereby avoid forming unwanted recombination centers that would reduce device efficiency.
Schubert does not teach an assembly substrate.
King teaches:
An assembly substrate (fig 2b:10; [para 0015])
a semiconductor light emitting element (fig 2c:30; [para 0015])wherein the [etched] structure (fig 2h; [para 0015]) is configured to prevent the semiconductor light emitting element (fig 2c:30; [para 0015]) from being assembled on the assembly substrate (fig 2b:10; [para 0015]) on a surface having the [etched] structure (fig 2h; [para 0015])during a self-assembly process in a fluid (fig 2i,2j; [para 0016]).
It would have been obvious to one of ordinary skill in the before the effective filing date of the claimed invention to provide an assembly substrate so that the devices can be assembled into a large array of light emitters that can the be integrated with other devices
Claim(s) 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Schubert (US 2017/0288087) in view of Shu (US 9312434) in view of King (US 2004/0222357) as applied to claim 18 and further in view of Horng (US 2010/0136728)
Regarding claim 19.
Schubert in view of Shu in view of King teaches the semiconductor light emitting element assembly of claim 18 above.
Schubert in view of Shu in view of King does not teach prominences in a plurality of bands.
Horng teaches:
a specific pattern (fig 9:235; [para 0047]) forms a plurality of bands in a direction from a center towards an edge of the surface.
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It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for the uneven surface to comprise bands of prominences around a center because the etching process of forming a partially removed porous structure will result in high points (prominences) which will be around the center of the surface and spread out to the edge.
Response to Arguments
Applicant's arguments filed 5/20/26 have been fully considered but they are not persuasive.
The applicant argues that the prior art does not teach the uneven structure is configured to prevent the semiconductor light emitting element from being assembled on the assembly substrate on a surface having the uneven structure during a self-assembly process in a fluid.
In response to applicant's argument that the prior art does not recognize the effect of an uneven surface on self-assembly, the fact that the inventor has recognized another advantage which would flow naturally from following the suggestion of the prior art cannot be the basis for patentability when the differences would otherwise be obvious. See Ex parte Obiaya, 227 USPQ 58, 60 (Bd. Pat. App. & Inter. 1985).
Further, Schubert teaches that the uneven structure is produced using a similar semiconductor etching process, therefore one of ordinary skill in the art would expect the disclosed surface roughness (uneven structure) to possess similar properties. MPEP 2112.01.I In re Best, 562 F.2d 1252, 1255, 195 USPQ 430, 433 (CCPA 1977), In re Spada, 911 F.2d 705, 709, 15 USPQ2d 1655, 1658 (Fed. Cir. 1990).
Further, the recognition that uneven structure (surface roughness) resulting from etching affects the self-assembly properties does not confer patentability. MPEP 2112.I
Additionally, King teaches that the self-assembly of light emitting elements detached by an etching process results in the etched surface not assembling onto the assembly surface, fig 2h-2j.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID J GOODWIN whose telephone number is (571)272-8451. The examiner can normally be reached Monday - Friday, 11:00 - 19:00.
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/D.J.G/Examiner, Art Unit 2817
/Kretelia Graham/Supervisory Patent Examiner, Art Unit 2817
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