DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed 9/16/2025 have been fully considered but they are moot in view of the new grounds of rejection.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 9/16/2025 has been entered.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1, 2, 5-16, 18-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites “the surface layer portion of the second main surface” at lines 4-5. It is unclear as to what element said limitation is referring to. Line 9-10 recites “a surface layer portion of the second main surface” seems to recite the same limitation and should be merged to align with antecedent basis requirements.
Claim 1 recites “an FET structure formed in the first main surface at the active region” at lines 10-11. It is unclear as to how a three dimensional object would be able to be formed in a two dimensional surface.
Claim 1 recites “collector region and the … cathode region are each formed in a surface layer portion closer to the second main surface in the buffer region” at lines 15-17. It is unclear whether the recited surface layer portion is the same or different than the other recitations of “a surface layer portion of the first main surface” or “a surface layer portion of the second main surface.” Further, when the claim recites “closer to,” it is a relative term, therefore it is unclear because the claim requires the collector region and cathode region to be closer to the second main surface relative to some undefined element.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 2, 5-16, 18-20 is/are rejected under 35 U.S.C. 102(a)(1), as best understood, as being anticipated by Takahashi et al. (US PGPub 2018/0226400; hereinafter “Takahashi”).
Re claim 1: Takahashi teaches (e.g. figs. 1, 2, 3, 6) semiconductor device comprising: a first-conductivity-type (n-type) semiconductor substrate (n- substrate 10; e.g. paragraph 18) that has a first main surface (upper surface of 10; hereinafter “1MS”) on one side and a second main surface (lower surface of 10; hereinafter “2MS”) on another side; a first-conductivity-type buffer region (n-type buffer layer 30; e.g. paragraph 24) that is formed in the surface layer portion (bottom portion of 10) of the second main surface (2MS); a second-conductivity-type (p-type) well region (P+ type well region 40; e.g. paragraph 22) that is formed in a surface layer portion (upper portion of 10) of the first main surface (1MS) and that demarcates an active region (R1) and an outer region (R3) in the semiconductor substrate (10); an IGBT (IGBTs within section R1; e.g. paragraph 18-20) including a second-conductivity-type (p-type) collector region (p+ collector layer 32; e.g. paragraph 21) formed in a surface layer portion of the second main surface (2MS) at the active region (R1) and an FET structure (trench gate 20; p-base 14; N+ emitter 16, and p+ contact region 18 within R1; e.g. paragraph 20) formed in the first main surface (1MS) at the active region (R1); and a diode (diode D1 formed from anode 40, and cathode 42; e.g. paragraph 24) that includes a first-conductivity-type cathode region (cathode 42; e.g. paragraph 24) formed only (cathode 42 is only formed in R3) at the outer region (R3) in the surface layer portion of the second main surface (2MS) and that has the second-conductivity-type well region (40) serving as an anode region (anode 40), wherein the second-conductivity-type collector region (32) and the first-conductivity-type cathode region (42) are each formed in a surface layer portion closer to the second main surface (2MS) in the buffer region (30), the second-conductivity-type collector region (32) is formed in a whole region of the surface layer portion (R1) of the second main surface (2MS) at the active region (R1), the first-conductivity-type cathode region (42) has an impurity concentration exceeding (42 has a higher concentration; e.g. paragraph 24) an impurity concentration of the first-conductivity-type buffer region (30) and is formed only in a region overlapping with the second-conductivity-type well region (40) at the outer region (R3), and no first-conductivity-type cathode region (42) is formed in a region directly under the FET structure (20, 14, 16, 18 within R1) in the surface layer portion of the second main surface (2MS) at the active region (R1).
Re claim 2: Takahashi teaches the semiconductor device according to Claim 1, wherein the second-conductivity-type collector region (32) is formed in a whole area (whole area of R1) of the surface layer portion of the second main surface (2MS), and the first-conductivity-type cathode region (42) is formed in a mode in which a second-conductivity-type (p-type) impurity of the collector region (32) is offset by a first-conductivity-type impurity (n-type).
Re claim 5: Takahashi teaches the semiconductor device according to Claim 1, wherein the first-conductivity-type cathode region (42) has a plane area (there exists a plane area within 42 that is between 1-10%) that is not less than 1% and not more than 10% of a plane area of the active region (R1).
Re claim 6: Takahashi teaches the semiconductor device according to Claim 1, wherein the first-conductivity-type cathode region (42) has a plane area (there exists a plane area within 42 that is between 1-5%) that is not less than 1% and not more than 5% of a plane area of the active region (R1).
Re claim 7: Takahashi teaches the semiconductor device according to Claim 1, wherein the second-conductivity-type well region (40) extends in a linear shape (40 has linear portions as shown in fig. 1), and the first-conductivity-type cathode region (42) extends in a linear shape (42 has linear portions as shown in fig. 1) along the second-conductivity-type well region (40).
Re claim 8: Takahashi teaches the semiconductor device according to Claim 1, wherein the second-conductivity-type well region (40) is formed in an endless shape (40 has a loop shape within it).
Re claim 9: Takahashi teaches the semiconductor device according to Claim 1, wherein the first-conductivity-type cathode region (42) is formed in an ended shape (42 are shown as having ends).
Re claim 10: Takahashi teaches the semiconductor device according to Claim 1, wherein the second-conductivity-type well region (40) includes a pad well region (region of 40 in R3 as shown in fig. 8; hereinafter “PWR”) formed in an island shape and a line well region (region of 40 in R3 connected to PWR; hereinafter “LWR”) drawn out from the pad well region (PWR) in a linear shape, and the first-conductivity-type cathode region (42) is formed in a region overlapping with the line well region (LWR) in a plan view.
Re claim 11: Takahashi teaches the semiconductor device according to Claim 10, wherein the first-conductivity-type cathode region (42) is not formed in a region overlapping (fig. 8 shows regions which do not overlap with PWR where 42 is formed) with the pad well region (PWR) in a plan view.
Re claim 12: Takahashi teaches the semiconductor device according to Claim 10, wherein the first-conductivity-type cathode region (42) is formed only in a region overlapping (fig. 8 shows regions which form 42 where only with LWR is formed) with the line well region (LWR) in a plan view.
Re claim 13: Takahashi teaches the semiconductor device according to Claim 10, further comprising: a gate pad (gate pad 50 in gate region R4; e.g. paragraph 42) that covers the pad well region (PWR) on the first main surface (1MS).
Re claim 14: Takahashi teaches the semiconductor device according to Claim 10, further comprising: an emitter pad (emitter pad 24; e.g. paragraph 20) that covers the active region (R1) on the first main surface (1MS).
Re claim 15: Takahashi teaches the semiconductor device according to Claim 1, further comprising: a second-conductivity-type (p-type) FL region (40 within field limit region R5; e.g. paragraph 26) that is formed in the surface layer portion of the first main surface (1MS) at the outer region (R5) and that is at a distance from the first-conductivity-type cathode region (42) in a direction opposite to the active region (R1) in a plan view.
Re claim 16: Takahashi teaches the semiconductor device according to Claim 15, wherein the second-conductivity-type FL region (40 within R5) surrounds the second-conductivity-type well region (40 within R3) in a plan view.
Re claim 18: Takahashi teaches the semiconductor device according to Claim 1, further comprising: an insulation layer (26; e.g. paragraph 20) that covers the first main surface (1MS) at the active region (R1) and the outer region (R5); a gate wiring layer (gate line 52; e.g. paragraph 41) that is arranged within the insulation layer (26) at the outer region (R5) and overlaps the second-conductivity-type well region (40) in a thickness direction of the semiconductor substrate (10); an emitter pad electrode (emitter pad 24; e.g. paragraph 22) that is arranged on the insulation layer (26) so as to be electrically connected to the FET structure (20, 14, 16, 18 within R1) at the active region (R1) and has a portion that is electrically connected to an inner peripheral edge side of the second-conductivity-type well region (40) at the outer region (R5); a gate finger electrode (gate electrode 22 are provided with runners; e.g. paragraph 39) that is arranged on the insulation layer (26) at the outer region (R5) at an interval from the emitter pad electrode (24) toward a peripheral edge side of the semiconductor substrate (10) and is electrically connected to the gate wiring layer (52); an emitter finger electrode (portion of 24 passing through 26) that is arranged on the insulation layer (26) at the outer region (R5) at an interval from the gate finger electrode (22) toward the peripheral edge side of the semiconductor substrate (10) and is electrically connected to an outer peripheral edge side of the second-conductivity-type well region (40); and a collector electrode (34) that is arranged on the second main surface (2MS) and is electrically connected to the second-conductivity-type collector region (32) of the IGBT and the first-conductivity-type cathode region (42) of the diode (D1).
Re claim 19: Takahashi teaches the semiconductor device according to Claim 1, wherein the first-conductivity-type cathode region (42) extends in a horizontal direction along the second main surface (2MS) in a region directly under the second-conductivity-type well region (40) in a cross-sectional view, and an occupancy ratio of the first-conductivity-type cathode region (42) in the region directly under the second-conductivity-type well region (40) is larger than an occupancy ratio of the second-conductivity-type collector region (32) in the region directly under the second-conductivity-type well region (40) in the cross-sectional view.
Re claim 20: Takahashi teaches the semiconductor device according to Claim 1, further comprising: a collector electrode (34) that is arranged on the second main surface (2MS) and is electrically connected to the second-conductivity-type collector region (32) of the IGBT and the first- conductivity-type cathode region (42) of the diode (D1). wherein the collector electrode (34) is electrically connected to the first-conductivity-type buffer region (30) via the first-conductivity-type cathode region (42).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JESSE Y MIYOSHI whose telephone number is (571)270-1629. The examiner can normally be reached M-F, 8:30AM-5:00PM.
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/JESSE Y MIYOSHI/
Primary Examiner, Art Unit 2898