DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Applicant’s arguments with respect to claim(s) 1, 3 – 7, and 9 – 23 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 6, 7, 9 – 14, 16 – 23 are rejected under 35 U.S.C. 103 as being unpatentable over DAVID US 2017/0109646 (hereinafter DAVID) in view of Halliyal US 2002/0142493 (hereinafter Halliyal).
Regarding claim 1, DAVID teaches: a method of predicting substrate geometry associated with a semiconductor manufacturing process, the method comprising:
receiving input information including geometry information and manufacturing process information for a substrate, wherein the substrate comprises a layer thereon ([0162] - - input data includes upstream metrology measurements; and data from process equipment (such as temperature); upstream metrology measurements is geometry information; [0088] - - input data include film thickness and in-situ measurements; [0122] - - predicting etch depth using previous step thickness and process variables); and
predicting, using a machine learning prediction model, at least a thickness of the layer as output substrate geometry, based on the input information (Fig. 8, [0162] - - using a supervised learning algorithm, a model is trained to predict film thickness).
But DAVID does not explicitly teach:
input information including geometry information of a metrology target or mark formed, or to be formed, on a substrate.
However, Halliyal teaches:
input information including geometry information of a metrology target or mark formed, or to be formed, on a substrate ([0057] - - thickness profile is measured using gratings; grating is a metrology target).
DAVID and Halliyal are analogous art because they are from the same field of endeavor. They all relate semiconductor manufacturing system.
Therefore before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify the above method, as taught by DAVID, and incorporating measuring thickness of previous step using a grating, as taught by Halliyal.
One of ordinary skill in the art would have been motivated to do this modification in order to achieve a desired feature thickness, as suggested by Halliyal ([0009]).
Claim 16 is substantially similar to claim 1 and is rejected for the same reasons and rationale as above.
Regarding claim 6, the combination of DAVID and Halliyal teaches all the limitations of the base claims as outlined above.
DAVID further teaches: predicting, using a machine learning prediction model, an overlay signal based on the output substrate geometry (Fig. 8, [0090] - - overlay offset prediction using a model; [0046] - - machine learning algorithm is used).
Regarding claim 7, the combination of DAVID and Halliyal teaches all the limitations of the base claims as outlined above.
DAVID further teaches: predicting, using the machine learning prediction model, an alignment signal based on the output substrate geometry (Fig. 8, [0090] - - overlay offset prediction using a model; overlay offset is a an alignment signal; [0046] - - machine learning algorithm is used)
Regarding claim 9, the combination of DAVID and Halliyal teaches all the limitations of the base claims as outlined above.
DAVID further teaches: the geometry information comprises one or more dimensions of a target or mark design for one or more layers of a semiconductor device ([0056] - - box-in-box or line-in-line alignment marks; [0061] - - the dimension between features is designed to be “x”).
Regarding claim 10, the combination of DAVID and Halliyal teaches all the limitations of the base claims as outlined above.
DAVID further teaches: the manufacturing process information comprises one or more parameters for one or more manufacturing processes performed on one or more layers of a semiconductor device ([0162] - - data from process equipment (such as temperatures and run times).
Regarding claim 11, the combination of DAVID and Halliyal teaches all the limitations of the base claims as outlined above.
DAVID further teaches: training the machine learning prediction model with training information comprising geometry, pattern, and manufacturing process parameters for training substrates (Fig. 8, [0162] - - using a supervised learning algorithm, a model is trained to predict film thickness; The input data can be upstream metrology measurements, or data from process equipment (such as temperatures and run times)), and corresponding physical substrate measurements and/or predictions from a non-machine learning prediction model (Fig. 8, [0162] - - measured targets are corresponding physical substrate measurements).
Regarding claim 12, the combination of DAVID and Halliyal teaches all the limitations of the base claims as outlined above.
DAVID further teaches: determining, with the prediction model, variation in a manufacturing process based on inputs (Fig. 8, [0162] - - predicting film thickness with a prediction model; [0050] – in case of CMP, if the predicted dielectric film thickness will be 100 Angstroms thicker than the target thickness if the wafer was to be polished at the nominal polish time, then lengthen the polish time; [0068] - - the target is lithography apparatus parameters such as, reticle position).
Regarding claim 13, the combination of DAVID and Halliyal teaches all the limitations of the base claims as outlined above.
DAVID further teaches: determining an adjustment for a semiconductor device manufacturing apparatus based on the variation in the manufacturing process, wherein the determining the adjustment is performed in substantially real time with receiving an overlay signal and/or an alignment signal during the semiconductor device manufacturing process (Fig. 8, [0090] - - determine an adjustment to be made to a lithographic apparatus based on overlay offset prediction).
Regarding claim 14, the combination of DAVID and Halliyal teaches all the limitations of the base claims as outlined above.
DAVID further teaches: the variation in the manufacturing process comprises one or more selected from: variation in one or more processing parameters of the manufacturing process (Abstract - - measuring and/or compensating for process variations), variation in one or more material properties of one or more materials used in the manufacturing process, or variation in one or more optical properties of the one or more materials
Regarding claim 17, DAVID teaches: a method for monitoring performance of a manufacturing process, the method comprising:
receiving one or more input signals that convey information related to geometry of a substrate in the manufacturing process (Fig. 8, [0088] - [0090] - - input data includes process variables and metrology data and parametric data); and
determining, by a hardware computer using a prediction model, variation in a physical characteristic of the substrate processed by the executed manufacturing process based on the one or more input signals, wherein the substrate is associated with a semiconductor device, and the manufacturing process comprises a semiconductor device manufacturing process ([0090] - - the score generated by the model will correspond to whatever metric; [0050] – in case of CMP, if the predicted dielectric film thickness will be 100 Angstroms thicker than the target thickness if the wafer was to be polished at the nominal polish time, then lengthen the polish time.).
But DAVID does not explicitly teach:
input signals that convey information related to geometry of a metrology target or mark formed, or to be formed, on a substrate.
However, Halliyal teaches:
input signals that convey information related to geometry of a metrology target or mark formed, or to be formed, on a substrate ([0057] - - thickness profile is measured using gratings; grating is a metrology target).
DAVID and Halliyal are analogous art because they are from the same field of endeavor. They all relate semiconductor manufacturing system.
Therefore before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify the above method, as taught by DAVID, and incorporating measuring thickness of previous step using a grating, as taught by Halliyal.
One of ordinary skill in the art would have been motivated to do this modification in order to achieve a desired feature thickness, as suggested by Halliyal ([0009]).
Claim 23 is substantially similar to claim 17 and is rejected for the same reasons and rationale as above.
Regarding claim 18, the combination of DAVID and Halliyal teaches all the limitations of the base claims as outlined above.
DAVID further teaches: determining an adjustment for a semiconductor device manufacturing apparatus based on the variation in the physical characteristic of the substrate ([0050] – in case of CMP, if the predicted dielectric film thickness will be 100 Angstroms thicker than the target thickness if the wafer was to be polished at the nominal polish time, then lengthen the polish time.)
Regarding claim 19, the combination of DAVID and Halliyal teaches all the limitations of the base claims as outlined above.
DAVID further teaches: the receiving and the determining are performed in real time or near real time during the semiconductor device manufacturing process (Fig. 8, [0088]-[0090] - - the input data is collected during wafer fabrication, the score is used to determine an adjustment to be made; thus it is performed in real time).
Regarding claim 20, the combination of DAVID and Halliyal teaches all the limitations of the base claims as outlined above.
DAVID further teaches: the one or more input signals comprise an overlay signal or an alignment signal ([0111] - - parameters of other overlay measurements such as DBO and IBO are used as inputs).
Regarding claim 21, the combination of DAVID and Halliyal teaches all the limitations of the base claims as outlined above.
DAVID further teaches: the variation in the physical characteristic of the substrate comprises one or more selected from: variation in one or more geometric dimensions of one or more structures on the substrate (Fig. 8, [0090] - - the score is predicted overlay offset prediction), variation in one or more material properties of one or more materials used in the manufacturing process ([0049] - - metal layer characteristics), or variation in one or more optical properties of the one or more materials ([0122] - - optical n and k values of the film).
Regarding claim 22, the combination of DAVID and Halliyal teaches all the limitations of the base claims as outlined above.
DAVID further teaches: a machine learning model ([0166] - - machine learning model) .
Claims 3 – 5 are rejected under 35 U.S.C. 103 as being unpatentable over DAVID US 2017/0109646 (hereinafter DAVID) in view of Halliyal US 2002/0142493 (hereinafter Halliyal) and further in view of BANNA US 2020/0110390 (hereinafter BANNA).
Regarding claim 3, the combination of DAVID and Halliyal teaches all the limitations of the base claims as outlined above.
But the combination of DAVID and Halliyal does not explicitly teach:
tuning the predicted output substrate geometry based on the predicting, the tuning comprising: comparing the output substrate geometry to corresponding physical substrate measurements and/or predictions from a non-machine learning prediction model; and generating a loss function based on the comparison; and optimizing the loss function.
However, BANNA teaches:
tuning the predicted output substrate geometry based on the predicting, the tuning comprising: comparing the output substrate geometry to corresponding physical substrate measurements and/or predictions from a non-machine learning prediction model; and generating a loss function based on the comparison; and optimizing the loss function ([0052] - - “The model's performance is optimized using a penalty function or cost function 105, such as root mean square error (rMSE).” The cost function is a loss function. The cost function is designed to allow optimization of dimensions of interest).
DAVID, Halliyal and BANNA are analogous art because they are from the same field of endeavor. They all relate semiconductor manufacturing system.
Therefore before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify the above method, as taught by the combination of DAVID and Halliyal, and incorporating a loss function, as taught by BANNA.
One of ordinary skill in the art would have been motivated to do this modification in order to improve semiconductor manufacturing process, as suggested by BANNA ([0005]).
Regarding claim 4, the combination of DAVID, Halliyal and BANNA teaches all the limitations of the base claims as outlined above.
DAVID further teaches: the tuning comprises stack tuning, wherein: stack tuning inputs comprise (1) a signal associated with a measurement from a corresponding physical stack (Fig. 8, [0088] - - input data includes a measurement),
(2) the geometry information, the geometry information including nominal geometry of the physical stack ([0050] - - in case of CMP, if the predicted dielectric film thickness will be 100 Angstroms thicker than the target thickness if the wafer was to be polished at the nominal polish time, then lengthen the polish time. The target thickness is a nominal geometry), and
(3) the manufacturing process information ([0088] – process variables such as temperature), and
a stack tuning output comprises the output substrate geometry (Fig. 8, [0162] - - using a supervised learning algorithm, a model is trained to predict film thickness).
Regarding claim 5, the combination of DAVID, Halliyal and BANNA teaches all the limitations of the base claims as outlined above.
BANNA further teaches: the output substrate geometry is tuned such that a simulated signal determined based on the output substrate geometry corresponds to the signal associated with the measurement from the physical stack and/or the nominal geometry of the physical stack ([0041] - - use machine learning model to predict dimensions on the wafer; [0052] - - “The model's performance is optimized using a penalty function or cost function 105, such as root mean square error (rMSE).”).
DAVID and BANNA are combinable for the same rationale as set forth.
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over DAVID US 2017/0109646 (hereinafter DAVID) in view of Halliyal US 2002/0142493 (hereinafter Halliyal) and further in view of WARNAAR EP 3441819 (hereinafter WARNAAR).
Regarding claim 15, the combination of DAVID and Halliyal teaches all the limitations of the base claims as outlined above.
But the combination of DAVID and Halliyal does not explicitly teach:
training a prediction model based on known perturbations in the manufacturing process.
However, WARNAAR teaches:
training a prediction model based on known perturbations in the manufacturing process ([0149] - - a certain amount of perturbations are used in prediction).
DAVID, Halliyal and WARNAAR are analogous art because they are from the same field of endeavor. They all relate semiconductor manufacturing system.
Therefore before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify the above method, as taught by the combination of DAVID and Halliyal, and incorporating training a prediction model based on known perturbations, as taught by WARNAAR.
One of ordinary skill in the art would have been motivated to do this modification in order to more accurately simulate the manufacturing process, as suggested by WARNAAR ([0149]).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to YUHUI R PAN whose telephone number is (571)272-9872. The examiner can normally be reached Monday-Friday 8AM-5PM EST.
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/YUHUI R PAN/Primary Examiner, Art Unit 2116