DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This office action is in response to the amendment filed on 9/12/25. Claims 1-6 and 8 are pending.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-6 and 8 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Shibuki (US PGPub 2012/0217604, hereinafter referred to as “Shibuki”).
Shibuki discloses the semiconductor device as claimed. See figures 1-39, and corresponding text, where Shibuki teaches, in claim 1, a semiconductor device, comprising:
a semiconductor chip (CA) which includes:
a first region (SA, PA) that has a first integration density of a first set of electronic circuits of a plurality of electronic circuits (110H); and
a second region (PAD) that has a second integration density of a second set of electronic circuits of the plurality of electronic circuits, wherein the first integration density is higher than the second integration density, the semiconductor chip (1) has four sides (SC, SA, PAD) which correspond to an outer edge of the semiconductor chip, the first region (SA, PA) is along a first side of the four sides, the second region (PAD) is along a second side of the four sides, and the first side is opposite to the second side in a plan view; (figure 1; [0078-0085])
a substrate (SK), wherein the semiconductor chip (CA) is on the substrate (SK); and
a die-bonding material (201) between the first region of the semiconductor chip (CA) and the substrate (SK), wherein a shape of the die-bonding material is a partially opened annular shape (111) in the plan view (figures 1 and 2; [0086-0103], the examiner views that the die bonding material is covers the entire surface of the wiring layer (110) and the support substrate (SK) and that within the bonding material (201) there is a partially opened annular shape underneath the wiring layer (110P) as shown in figure 3, [0156-0158]).
Shibuki teaches, in claim 2, wherein the semiconductor chip has four sides which correspond to an outer edge of the semiconductor chip, the second region is along at least one side of the four sides of the semiconductor chip, the first region is along a set of sides of the four sides, the set of sides includes the first side, the set of sides is different from the second other than the at least one side of the four sides of the semiconductor chip, and a part of the partially opened annular shape, of the die-bonding material in the plan view, is opened in a portion between the second region and the substrate. (figure 2; [0086-0103])
Shibuki teaches, in claim 3, wherein the semiconductor chip further includes an image capturing region of an image sensor in a center region of the semiconductor chip in the plan view, the image capturing region is surrounded by the first region and the second region, and the die-bonding material is directly below the first region. (figure 2; [0086-0103])
Shibuki teaches, in claim 4, wherein the image capturing region is in a plane same as that of the plurality of electronic circuits. (figure 2; [0086-0103])
Shibuki teaches, in claim 5, wherein the semiconductor chip further includes: a circuit layer that comprises the plurality of electronic circuits; and an image capturing layer on the circuit layer, wherein the image capturing layer includes the image capturing region, and the die-bonding material is between the circuit layer and the substrate. (figure 2; [0086-0103])
Shibuki teaches, in claim 6, wherein the substrate is an interposer substrate (110, SK). (figure 2; [0086-0103])
Shibuki teaches, in claim 8, wherein the first region is along the first side and a third side two sides of the four sides of the semiconductor chip, the four sides correspond to an outer edge of the semiconductor chip, and the first side of the two sides is adjacent to the third a second side of the two sides. (figure 2; [0086-0103])
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-6 and 8 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Applicant’s amendment has necessitated new grounds of rejection.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to STANETTA D ISAAC whose telephone number is (571)272-1671. The examiner can normally be reached M-F 11-8.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio Maldonado can be reached at 571-272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/STANETTA D ISAAC/Examiner, Art Unit 2898 September 19, 2025
/JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898