DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The Amendment filed 05/27/2025 has been entered.
Response to Arguments
Applicant's arguments filed 05/27/2025 have been fully considered but they are not persuasive. The prior art rejections below map to the limitations that are claimed in the applicant where the specification by Schultz recites a first and second die using different Group III-V semiconductor fabrication processes. The action is also final due to the new limitation in the independent claims stating “different than the first Group III-V semiconductor fabrication process,” which was not previously claimed in claim 5.
Claim Objections
Claims 5 and 16 are objected to because of the following informalities:
Claim 5: should say “gallium nitride (GaN)”
Claim 16: should say “comprises a Gallium Arsenide (GaAs) process…. Gallium Nitride (GaN) process.”
Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 5, and 8-11 is/are rejected under 35 U.S.C. 102(a)(1) and (a)(2) as being anticipated by US 10250197 by Schultz et al.
Regarding claim 1, Schultz teaches a power amplifier device (Fig. 1), comprising:
a driver amplifier (140) formed on a first semiconductor die (110) using a first Group III-V semiconductor fabrication process (par. 139, the first die includes a III-V semiconductor substrate);
an output amplifier (182) formed on a second semiconductor die (180) using a second Group III-V semiconductor fabrication process (Abstract) different than the first Group III-V semiconductor fabrication process (Abstract: the first die and the second die are different types of semiconductor substrates); and
an inter-stage matching network (Fig. 1 #150) formed between the driver amplifier (140) on the first semiconductor die (110) and the output amplifier (182) on the second semiconductor die (180).
Regarding claim 5, Schultz teaches the power amplifier device of claim 1, wherein: the first Group III-V semiconductor fabrication process comprises a Gallium Arsenide (GaAs) process (Col. 2 lines 30-31 state that GaAs is a known and possible fabrication process); and the second Group III-V semiconductor fabrication process comprises a Gallium Nitride process (Abstract).
Regarding claim 8, Schultz teaches the power amplifier device according to claim 1, wherein the inter-stage matching network (150) comprises at least one wire bond between the driver amplifier on the first semiconductor die and the output amplifier on the second semiconductor die (Fig. 1).
Regarding claim 9, Schultz teaches the power amplifier device according to claim 1 wherein: the power amplifier device comprises a Doherty amplifier; the output amplifier comprises a main output and a peak output (Col. 29 lines 5-24); and the inter-stage matching network comprises a first plurality of wire bonds for the main output and a second plurality of wire bonds for the peak output (Fig. 4-9 show a plurality of wire bonds between the different stages).
Regarding claim 10, Schultz teaches the power amplifier device of claim 1, further comprising: a first supply of power at a first voltage for the driver amplifier; and a second supply of power at a second voltage for the output amplifier, wherein the second voltage is greater than the first voltage (Col. 12 lines 65-67).
Regarding claim 11, Schultz teaches the power amplifier device of claim 1, wherein the driver amplifier operates at a lower voltage and the output amplifier operates at a higher voltage for line-up efficiency between the driver amplifier and the output amplifier (Col. 12 lines 65-67).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 6-7, 12, and 16-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 10250197 by Schultz et al.
Regarding claim 6, Schultz teaches the power amplifier device of claim 1, wherein: the first Group III-V semiconductor fabrication process comprises one of a Gallium Arsenide (GaAs) pseudomorphic high electron mobility transistor (PHEMT), or GaAs heterojunction bipolar transistor (HBT) process (while not specified in Schultz, these are well known semiconductor fabrication processes in power amplifier circuits as shown in par. 19 of US 20180219563 Tormanen et al.); and
the second Group III-V semiconductor fabrication process comprises one of a Gallium Nitride (GaN) on silicon carbide (SiC), or GaN on silicon (Si) process (Schultz Col. 4 lines 49-51).
Regarding claim 7, Schultz teaches the power amplifier device according to claim 1, further comprising: an input amplifier formed on the first semiconductor die using the first semiconductor fabrication process; and a second inter-stage matching network formed between the input amplifier and the driver amplifier on the first semiconductor die. The prior art by Schultz teaches a two stage cascade amplifier with an interstage matching network in between, however, multi-stage amplifiers with more than one interstage matching network are very well known in the art as shown in fig. 4 of US 9294046 by Scott et al. Matching network 78 is formed between input amplifier 36a and a second stage (driver) amplifier 36b. Cascode configurations like this provide more power.
Regarding claim 12, Schultz teaches the power amplifier device (Fig. 1), comprising:
an input amplifier formed on a first semiconductor die using a first Group III-V semiconductor fabrication process;
a driver amplifier (140) formed on the first semiconductor die (110) using the first Group III-V semiconductor fabrication process (par. 139, the first die includes a III-V semiconductor substrate);
a first inter-stage matching network formed between the input amplifier and the driver amplifier on the first semiconductor die;
an output amplifier (182) formed on a second semiconductor die (180) using a second Group III-V semiconductor fabrication process different than the first Group III-V semiconductor fabrication process (Abstract: the first die and the second die are different types of semiconductor substrates); and
a second inter-stage matching network (150) comprising at least one wire bond between the driver amplifier (140) on the first semiconductor die and the output amplifier (182) on the second semiconductor die.
The prior art by Schultz teaches a two stage cascade amplifier with an interstage matching network in between, however, multi-stage amplifiers with more than one interstage matching network are very well known in the art as shown in fig. 4 of US 9294046. A first inter-stage matching network 78 is formed between input amplifier 36a and a second stage (driver) amplifier 36b. Cascode configurations like this provide higher gain.
Regarding claim 16, Schultz teaches the power amplifier device of claim 12, wherein: the first Group III-V semiconductor fabrication process comprises a Gallium Arsenide (GaAs) (Col. 2 lines 30-31 state that GaAs is a known and possible fabrication process); and the second Group III-V semiconductor fabrication process comprises a Gallium Nitride (Abstract).
Regarding claim 17, Schultz teaches the power amplifier device of claim 12, wherein: the first Group III-V semiconductor fabrication process comprises one of a Gallium Arsenide (GaAs) pseudomorphic high electron mobility transistor (PHEMT), or GaAs heterojunction bipolar transistor (HBT) process (while not specified in Schultz, these are well known semiconductor fabrication processes in power amplifier circuits as shown in par. 19 of US 20180219563 Tormanen et al.); and the second Group III-V semiconductor fabrication process comprises one of a Gallium Nitride (GaN) on silicon carbide (SiC)[[,]] or GaN on silicon (Si) process (Col. 4 lines 49-51).
Regarding claim 18, Schultz teaches the power amplifier device of claim 12, wherein: the power amplifier device comprises a Doherty amplifier; the output amplifier comprises a main output and a peak output (Col. 29 lines 5-24); and the second inter-stage matching network comprises a first plurality of wire bonds for the main output and a second plurality of wire bonds for the peak output (Fig. 4-9 show a plurality of wire bonds between the different stages).
Regarding claim 19, Schultz teaches the power amplifier device of claim 12, further comprising: a first supply of power at a first voltage for the driver amplifier; and a second supply of power at a second voltage for the output amplifier, wherein the second voltage is greater than the first voltage (Col. 12 lines 65-67).
Regarding claim 20, Schultz teaches the power amplifier device of claim 12, wherein the driver amplifier operates at a lower voltage and the output amplifier operates at a higher voltage for line-up efficiency between the driver amplifier and the output amplifier (Col. 12 lines 65-67).
Allowable Subject Matter
Claims 2-4 and 13-15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NAREH SHAMIRYAN whose telephone number is (703)756-4616. The examiner can normally be reached M-F: 7:00AM-4:00PM PT.
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/NAREH SHAMIRYAN/Examiner, Art Unit 2843
/ANDREA LINDGREN BALTZELL/Supervisory Patent Examiner, Art Unit 2843
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