COLOR OPTOELECTRONIC SOLID STATE DEVICE

DETAILED ACTION Notice of AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Continued Examination Under 37 CFR 1.114 A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 04/24/2026 has been entered. Information Disclosure Statement The information disclosure statement (IDS) filed on 04/30/2026, and 06/17/2026 is/are in compliance with provisions of 37 CFR 1.97. Accordingly, the information disclosure is being considered by the Examiner. Drawings objection The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the claimed feature, current confinement structures must be shown or the feature(s) canceled from the claim(s). No new matter should be entered. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance. Response to Amendment The amendment with respect to claim(s) 1 filed on 04/24/2026 has been fully considered for examination based on their merits. The previously presented claim(s) 2-40 have been considered. Response to Arguments Applicant’s arguments, see Remarks, pages 5-8, filed 04/24/2026, with respect to the rejection(s) of claim(s) 1-6, 13, 22-23, 25-26, 33, and 38-40 under 35 U.S.C. 102(a)(1) and claim(s) 7-12, 14-21, 24, 27-32, 34-37, under 35 U.S.C. 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of MCGRODDY. Regarding Claim 1. Applicant argues that ENGLAND fails to disclose or suggest the amended features to claim 1 recites, “a microdevice array having a microdevice comprising: wherein the stacked layers include one or more current confinement structures configured to confine current in at least one area of the stacked layers to isolate the sub pixels.” Examiner agrees that the arguments are persuasive and therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made as mentioned in the above paragraph. For instance, the prior-art of MCGRODDY teaches a microdevice array having a microdevice comprising: wherein the stacked layers include the current spreading layer pillar to confine current equally from the sidewalls of the LED for achieving the desired efficiency of the device. Regarding Claims 2-40: The claims 2-40 depends on claim 1, thus follow similar arguments as Claim 1, upon further consideration, a new-grounds of rejection is made based on the prior-art mentioned above. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. Claim(s) 1-6, 13, 22-23, 25-26, 33, and 38-40 is/are rejected under 35 U.S.C. 103 as being unpatentable over ENGLAND, in view Kelly McGroddy et al, (hereinafter MCGRODDY), US 20150187991 A1. Regarding Claim 1, ENGLAND teaches a microdevice array (Figs. 2/5, 20, micro-LED display assemblies) having a microdevice (Figs. 2/5, 20, micro-LED display assemblies) comprising: stacked layers of a semiconductor (Figs. 2/3, 100a-100f, plurality of layers, [0025]) bonded to a backplane (Fig. 2, 22, substrate); pads (Fig. 2, 26a, pads) in the backplane (Fig. 2, 22, substrate)defining sub pixels (Fig. 2, 14a/14b), with multiple sub pixels (Fig. 2, 14a/14b) for a pixel in an array of pixels (Fig. 1, 10a/10b, pixels, [0023]); and the stacked layers (Figs. 2/3, 100a-100f, plurality of layers, [0025]) bonded to the pads (Fig. 2, 26a, pads) in the backplane (Fig. 2, 22, substrate) defining sub pixels (Fig. 2, 14a/14b). ENGLAND does not explicitly disclose a microdevice array having a microdevice comprising: wherein the stacked layers include one or more current confinement structures configured to confine current in at least one area of the stacked layers to isolate the sub pixels. MCGRODDY teaches a microdevice array (Fig. 2A, forming an array of LED devices, which may be micro LED devices [0078]) having a microdevice (Fig. 35, 156, LED device, may be a micro LED device, [0016], [0069]) comprising: wherein the stacked layers (annotated Figure 35) include one or more current confinement structures (Fig. 35, 190, current spreading layer pillars) configured to confine current in at least one area (Fig. 35, 190, current spreading layer pillars to confine current equally from the sidewalls of the LED devices, [0016], [0072-0073], [0095-0096]) of the stacked layers (annotated Figure 35) to isolate the sub pixels (Figs. 35/37A, 328). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have modified ENGLAND to incorporate the teachings of MCGRODDY such that a microdevice array having a microdevice comprising: wherein the stacked layers include one or more current confinement structures configured to confine current in at least one area of the stacked layers to isolate the sub pixels. The above arrangement with the effect of current confinement, the desired efficiency of the microLED can be achieved (MCGRODDY, [0148]). Regarding Claim 2, ENGLAND as modified by MCGRODDY teaches the microdevice array of claim 1. ENGLAND further teaches the microdevice array (Figs. 2/5, 20, micro-LED display assemblies), where there are more than one set of stacked layers (Figs. 2/3, 100a-100f) associated with the pads (Fig. 2, 26a, pads) in the backplane (Fig. 2, 22, substrate) defining sub pixels (Fig. 2, 14a/14b). Regarding Claim 3, ENGLAND as modified by MCGRODDY teaches the microdevice array of claim 1. ENGLAND further teaches the microdevice array (Figs. 2/5, 20, micro-LED display assemblies), wherein one or more of top layers in the stacked layers (Figs. 2/3, 100a-100f, plurality of layers, [0025]) are etched (etching the films, [0018]). Regarding Claim 4, ENGLAND as modified by MCGRODDY teaches the microdevice array of claim 1. ENGLAND further teaches the microdevice array (Figs. 2/5, 20, micro-LED display assemblies), wherein the stacked layers (Figs. 2/3, 100a-100f, plurality of layers, [0025]) have VIA's (Figs. 2/3, 24, TSVs) before bonding to the backplane (Fig. 3, 22, substrate). Regarding Claim 5, ENGLAND as modified by MCGRODDY teaches the microdevice array of claim 4. ENGLAND further teaches the microdevice array (Figs. 2/5, 20, micro-LED display assemblies), wherein the VIA's (Figs. 2/3, 24, TSVs) are at least partially filled with a conductive layer separated from walls of the VIA's with a dielectric ([0026]). Regarding Claim 6, ENGLAND as modified by MCGRODDY teaches the microdevice array of claim 4. ENGLAND further teaches the microdevice array (Figs. 2/5, 20, micro-LED display assemblies), wherein the VIA's (Figs. 2/3, 24, TSVs) couple a pad (Figs. 2, 26/26a, metal pad/pads) from the backplane (Fig. 2, 22, substrate) to the top of the stack layer (Fig2. 2/3, 100a-100f, plurality of layers, [0025]). Regarding Claim 13, ENGLAND as modified by MCGRODDY teaches the microdevice array of claim 1. ENGLAND further teaches the microdevice array (Figs. 2/5, 20, micro-LED display assemblies), wherein the stacked layers (Figs. 2/3, 100a-100f, plurality of layers, [0025]) are red epitaxial light emitting layers (Table 1, [0021-0023]). Regarding Claim 22, ENGLAND as modified by MCGRODDY teaches the microdevice array of claim 1. ENGLAND further teaches the microdevice array (Figs. 2/5, 20, micro-LED display assemblies), wherein the microdevice array is a part of more than one microdevice array (Fig. 5, 20, micro-LED assemblies). Regarding Claim 23, ENGLAND as modified by MCGRODDY teaches the microdevice array of claim 22. ENGLAND further teaches the microdevice array (Figs. 2/5, 20, micro-LED display assemblies), wherein the stacked layers (Figs. 2/3, 100a-100f, plurality of layers, [0025]) are red, green or blue epitaxial light emitting layers (Table 1, [0021-0023]). Regarding Claim 25, ENGLAND as modified by MCGRODDY teaches the microdevice array of claim 22. ENGLAND further teaches the microdevice array (Figs. 2/5, 20, micro-LED display assemblies), wherein a second stacked layer (Figs. 2/3, 100a-100f, plurality of layers, [0025]) is bonded to the backplane (Figs. 2/3, 22, substrate) on top of a first stacked layer where the pads (Figs. 26/26a, metal pad/pads) in the backplane define the sub pixels (Figs. 2/3, 14a/14b). Regarding Claim 26, ENGLAND as modified by MCGRODDY teaches the microdevice array of claim 25. ENGLAND further teaches the microdevice array (Figs. 2/5, 20, micro-LED display assemblies), wherein one or more of top layers (Figs. 2/3, 100a-100f, plurality of layers, [0025]) in the second stacked layers (Figs. 2/3, 100a-100f, plurality of layers, [0025]) are etched (etching the films, [0018]). Regarding Claim 33, ENGLAND as modified by MCGRODDY teaches the microdevice array of claim 22. ENGLAND further teaches the microdevice array (Figs. 2/5, 20, micro-LED display assemblies), wherein the third stacked layer (Figs. 2/3, 100a-100f, plurality of layers, [0025]) is bonded to the backplane (Fig. 2, 22, substrate) on top of the second stacked layer (Figs. 2/3, 100a-100f, plurality of layers, [0025]) where the pads (Figs. 2, 26/26a, metal pad/pads) in the backplane (Fig. 3, 22, substrate) define the sub pixels (Figs. 2/3, 14a/14b). Regarding Claim 38, ENGLAND as modified by MCGRODDY teaches the microdevice array of claim 33. ENGLAND further teaches the microdevice array (Figs. 2/5, 20, micro-LED display assemblies), wherein the microdevices (Figs. 2/5, 20, micro-LED display assemblies) in the second and third stacked layer (Figs. 2/3, 100a-100f, plurality of layers, [0025]) are bonded to the backplane (Fig. 3, 22, substrate) prior to the bonding of the first stacked layers (Figs. 2/3, 100a-100f, plurality of layers, [0025]). Regarding Claim 39, ENGLAND as modified by MCGRODDY teaches the microdevice array of claim 33. ENGLAND further teaches the microdevice array (Figs. 2/5, 20, micro-LED display assemblies), wherein there is a conductive layer on top (Fig. 2, 30, conductive terminal for each pixel, [0024]) of the microdevices (Figs. 2/5, 20, micro-LED display assemblies) of the second and third stacked layers or the first stacked layer (Figs. 2/3, 100a-100f, plurality of layers, [0025]). Regarding Claim 40, ENGLAND as modified by MCGRODDY teaches the microdevice array of claim 33. ENGLAND further teaches the microdevice array (Figs. 2/5, 20, micro-LED display assemblies), wherein there are more than one pads (Figs. 26/26a, metal pad/pads), or more than two VIAs (Figs. 2/3, 24/50, TSVs) for each microdevice array (Figs. 2/5, 20, micro-LED display assemblies). Claim(s) 7-12, and 24 is/are rejected under 35 U.S.C. 103 as being unpatentable over ENGLAND, in view of MCGRODDY as applied to claim(s) 1-6, 13, 22-23, 25-26, 33, and 38-40 above, and further in view of Hsin-Chieh Huang, (hereinafter HUANG), US 20110198609 A1. Regarding Claim 7 ENGLAND as modified by MCGRODDY teaches the microdevice array of claim 1. ENGLAND further teaches the microdevice array (Figs. 2/5, 20, micro-LED display assemblies), wherein electrical VIA's (Figs. 2/3, 24, TSVs) are formed in the stacked layers (Figs. 2/3, 100a-100f, plurality of layers, [0025]) after the stacked layers are bonded (ILED wafer formation, [0026]) into the backplane (Fig. 3, 22, substrate). Though ENGLAND teaches the TSVs formation by backside grinding process followed by a deep Si etch [0026], ENGLAND as modified by MCGRODDY does not explicitly disclose the microdevice array, wherein electrical VIA's are formed in the stacked layers after the stacked layers are bonded into the backplane. HUANG teaches the microdevice array (Figs. 2A/2B, LED, [0010]), wherein electrical VIA's (Figs. 2A/2B, 34/38, TSV openings) are formed (Figs. 2-7, formation of TSV opening, [0014-0015]) in the stacked layers (Figs. 2A/2B, 22, LED with layers 26, 28, 30, [0012]) after the stacked layers are bonded into the (Figs. 2A/2B, 20, substrate). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have ENGLAND as modified by MCGRODDY to incorporate the teachings of HUANG such that the microdevice array, wherein electrical VIA's are formed in the stacked layers after the stacked layers are bonded into the backplane, so that TSV opening may be formed by penetrating various LED layers and enable to create an ohmic contact (HUANG, [0014-0015]). Regarding Claim 8, ENGLAND as modified by MCGRODDY and HUANG teaches, the microdevice array of claim 7. ENGLAND further teaches the microdevice array (Figs. 2/5, 20, micro-LED display assemblies), wherein the VIA's (Figs. 2/3, 24, TSVs) are aligned (annotated Figure 32) with the pads (Figs. 2, 26/26a, metal pad/pads) in the other sub pixels (Fig. 2, 14a/14b) in the back plane (Fig. 3, 22, substrate). Regarding Claim 9, ENGLAND as modified by MCGRODDY and HUANG teaches, the microdevice array of claim 8. ENGLAND further teaches the microdevice array (Figs. 2/5, 20, micro-LED display assemblies), wherein VIA's (Figs. 2/3, 24, TSVs) have passivated sidewalls (The vias are coated with dielectric liner such as SiO2, [0026]) and the pads (Fig. 2, 26/26a, metal pad/pads) are either inside the VIA's or on the walls of the VIA's (Fig. 2, [0024, 0026]). Regarding Claim 10, ENGLAND as modified by MCGRODDY and HUANG teaches, the microdevice array of claim 9. ENGLAND further teaches the microdevice array (Figs. 2/5, 20, micro-LED display assemblies), wherein additional microdevices (Fig. 5, 20, micro-LED assemblies) are bonded to the pads (Fig. 2, 26/26a, metal pad/pads, [0024], [0026; exposing the pads formed on the front side of the wafer, which are in electrical contact with the pixels of the micro-LED assemblies]). Regarding Claim 11, ENGLAND as modified by MCGRODDY and HUANG teaches, the microdevice array of claim 10. ENGLAND further teaches the microdevice array (Figs. 2/5, 20, micro-LED display assemblies), wherein there are more than one pads (Fig. 2, 26/26a, metal pad/pads), or more than two VIAs (Fig. 4, 24/50, TSVs) for each micro device (Fig. 4, 20, micro-LED assemblies). Regarding Claim 12, ENGLAND as modified by MCGRODDY and HUANG teaches, the microdevice array of claim 10. ENGLAND further teaches the microdevice array (Figs. 2/5, 20, micro-LED display assemblies), wherein the micro devices (Fig. 20, micro-LED assemblies) or stacked layers (Figs. 2/3, 100a-100f, plurality of layers, [0025]) have a conductive layer on top (Fig. 2, 30, conductive terminal for each pixel, [0024]). Regarding Claim 24, ENGLAND as modified by MCGRODDY and HUANG teaches the microdevice of claim 7. ENGLAND further teaches the microdevice array (Figs. 2/5, 20, micro-LED display assemblies), wherein the VIA's (Figs. 2/3, 24, TSVs) are aligned with the additional microdevices (Figs. 2/5, 20, micro-LED display assemblies) in additional stacked layers (Figs. 2/3, 100a-100f, plurality of layers, [0025]) and the pads (Figs. 2, 26/26a, metal pad/pads) in the other sub pixels (Fig. 2, 14a/14b) in the backplane (Fig. 3, 22, substrate). Claim(s) 14, 27-28 and 34 is/are rejected under 35 U.S.C. 103 as being unpatentable over ENGLAND, in view of MCGRODDY as applied to claim(s) 1-6, 13, 22-23, 25-26, 33, and 38-40 above, and further in view of Christopher Bower et al, (hereinafter BOWER), US 20160351539 A1. Regarding Claim 14, ENGLAND as modified by MCGRODDY teaches the microdevice array (Figs. 2/5, 20, micro-LED display assemblies), of claim 4. Though ENGLAND teaches the through-silicon vias or TSVs, ENGLAND as modified by MCGRODDY does not explicitly disclose the microdevice array, wherein the VIA's are optical. BOWER teaches the microdevice array (micro-LEDs, [0292]), wherein the VIA's are optical (Fig. 26, 28, optical vias, [0162-0163]). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have ENGLAND as modified by MCGRODDY to incorporate the teachings of BOWER such that the microdevice array, wherein the VIA's are optical, so that through optical vias, the light is emitted from the light emitting areas of the inorganic light emitters (30); the light emitters (30) are then disposed in the optical vias, for example using micro transfer printing, and electrically connected using photolithography (BOWER, [03150, [0322]). Regarding Claim 27, ENGLAND as modified by MCGRODDY teaches the microdevice array (Figs. 2/5, 20, micro-LED display assemblies) of claim 25. ENGLAND further teaches the microdevice array (Figs. 2/5, 20, micro-LED display assemblies), wherein the second stacked layer (Figs. 2/3, 100a-100f, plurality of layers, [0025]) has electrical and optical VIA's (Figs. 2/3, 24, TSVs) before bonding (Fig. 6, flowchart of the fabrication processes) to the backplane (Figs. 2/3, 22, substrate). Though ENGLAND teaches the through-silicon vias or TSVs, ENGLAND as modified by MCGRODDY does not explicitly disclose the microdevice array, wherein the second stacked layer has electrical and optical VIA's before bonding to the backplane. BOWER teaches the microdevice array (micro-LEDs, [0292]), wherein the second stacked layer has electrical and optical VIA's (electrical vias, [0321-0322]; Fig. 26, 28, optical vias, [0162-0163]). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have ENGLAND as modified by MCGRODDY to incorporate the teachings of BOWER such that the microdevice array, wherein the second stacked layer has electrical and optical VIA's before bonding to the backplane, so that through optical vias, the light is emitted from the light emitting areas of the inorganic light emitters (30); the light emitters (30) are then disposed in the optical vias, for example using micro transfer printing, and electrically connected using photolithography. The electrical cum optical vias can be formed in the light-absorbing material (42) and the electrically insulating layer, as needed, for example to make electrical connections to the light emitter (30) (BOWER, [0315], [0321-0322]). Regarding Claim 28, ENGLAND as modified by MCGRODDY and BOWER teaches the microdevice array of claim 27. ENGLAND further teaches, the microdevice (Figs. 2/5, 20, micro-LED display assemblies), wherein the electrical VIA (Figs. 2/3, 24, TSVs) couple associated pads (Fig. 2, 26/26a, metal pad/pads) to a third stacked layer (Figs. 2/3, 100a-100f, plurality of layers, [0025]). Regarding Claim 34, ENGLAND as modified by MCGRODDY teaches the microdevice array (Figs. 2/5, 20, micro-LED display assemblies) of claim 33. ENGLAND further teaches, the microdevice (Figs. 2/5, 20, micro-LED display assemblies), wherein the third stacked layers (Figs. 2/3, 100a-100f, plurality of layers, [0025]) has optical VIA's (Figs. 2/3, 24, TSVs) before bonding (Fig. 6, flowchart of the fabrication processes) to the backplane (Figs. 2/3, 22, substrate). Though ENGLAND teaches the through-silicon vias or TSVs, ENGLAND as modified by MCGRODDY does not explicitly disclose the microdevice array, wherein the second stacked layer has electrical and optical VIA's before bonding to the backplane. BOWER teaches the microdevice array (micro-LEDs, [0292]), wherein the second stacked layer has electrical and optical VIA's (electrical vias, [0321-0322]; Fig. 26, 28, optical vias, [0162-0163]). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have ENGLAND as modified by MCGRODDY to incorporate the teachings of BOWER such that the microdevice array, wherein the second stacked layer has electrical and optical VIA's before bonding to the backplane, so that through optical vias, the light is emitted from the light emitting areas of the inorganic light emitters (30); the light emitters (30) are then disposed in the optical vias, for example using micro transfer printing, and electrically connected using photolithography. The electrical cum optical vias can be formed in the light-absorbing material (42) and the electrically insulating layer, as needed, for example to make electrical connections to the light emitter (30) (BOWER, [0315], [0321-0322]). Claim(s) 15-21, 29-30 and 35-37 is/are rejected under 35 U.S.C. 103 as being unpatentable over ENGLAND, in view of MCGRODDY, HUANG as applied to claim(s) 7-12 and 24 and BOWER as applied to claim(s) 14, 27-28 and 34 above. Regarding Claim 15, ENGLAND as modified by MCGRODDY and HUANG teaches the microdevice array, of claim 7. Though ENGLAND as modified by MCGRODDY and HUANG teaches the through-silicon vias or TSVs, ENGLAND as modified by MCGRODDY, and HUANG does not explicitly disclose the microdevice array, wherein electrical VIA's are optical. BOWER teaches the microdevice array (micro-LEDs, [0292]), wherein electrical VIA's are optical (electrical vias, [0321-0322]; Fig. 26, 28, optical vias, [0162-0163]). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have ENGLAND as modified by MCGRODDY, and HUANG to incorporate the teachings of BOWER such that the microdevice array, wherein electrical VIA's are optical, so that through optical vias, the light is emitted from the light emitting areas of the inorganic light emitters (30); the light emitters (30) are then disposed in the optical vias, for example using micro transfer printing, and electrically connected using photolithography. The electrical cum optical vias can be formed in the light-absorbing material (42) and the electrically insulating layer, as needed, for example to make electrical connections to the light emitter (30) (BOWER, [0315], [0321-0322]). Regarding Claim 16, ENGLAND as modified by MCGRODDY, HUANG and BOWER teaches the microdevice of claim 15. ENGLAND further teaches the microdevice array (Figs. 2/5, 20, micro-LED display assemblies), wherein the VIA's (Figs. 2/4, 24/50, TSVs) are aligned ([0026]) with the pads (Fig. 2, 26/26a, metal pad/pads) in the other sub pixels (Fig. 2, 14a/14b) in the back plane (Fig. 2, 22, substrate). Regarding Claim 17, ENGLAND as modified by MCGRODDY, HUANG and BOWER teaches the microdevice of claim 16. HUANG further teaches the microdevice array (Figs. 2A/2B, LED, [0010]), wherein VIA's (Fig. 7A, 42/44, TSVs) have passivated sidewalls (Fig. 7A, 39, isolation layers, [0017]) with reflective layers on the sidewalls ([0004], [0022]). Regarding Claim 18, ENGLAND as modified by MCGRODDY, HUANG and BOWER teaches the microdevice of claim 17. ENGLAND further teaches the microdevice array (Figs. 2/5, 20, micro-LED display assemblies), wherein additional microdevices (Fig. 2, 20, micro-LED assemblies) are bonded to the pads (Fig. 2, 26/26a, metal pad/pads). Regarding Claim 19, ENGLAND as modified by MCGRODDY, HUANG and BOWER teaches the microdevice of claim 18. ENGLAND further teaches the microdevice array (Figs. 2/5, 20, micro-LED display assemblies), wherein there are more than one pads (Fig. 2, 26/26a, metal pad/pads), or more than two VIAs (Fig. 4, 24/50, TSVs) for each micro device (Fig. 4, 20, micro-LED assemblies). Regarding Claim 20, ENGLAND as modified by MCGRODDY, HUANG and BOWER teaches the microdevice of claim 18. ENGLAND further teaches the microdevice array (Figs. 2/5, 20, micro-LED display assemblies), wherein the micro devices (Figs. 2/5, 20, micro-LED display assemblies), or stacked layers (Figs. 2/3, 100a-100f, plurality of layers, [0025]) have a conductive layer on top (Fig. 2, 30, conductive terminal for each pixel, [0024]). Regarding Claim 21, ENGLAND as modified by MCGRODDY, HUANG and BOWER teaches the microdevice of claim 19. ENGLAND further teaches the microdevice array (Figs. 2/5, 20, micro-LED display assemblies), wherein a bump (Figs. 4/5, 55, solder connections) comprising a microdevice (Figs. 2/5, 20, micro-LED display assemblies) couples the backplane (Figs. 2/5, 22/35, substrate/BEOL wiring ) to a pad (Figs. 2, 26/26a, metal pad/pads) formed on top of the microdevice. Regarding Claim 29, ENGLAND as modified MCGRODDY teaches the microdevice array (Figs. 2/5, 20, micro-LED display assemblies) of claim 25, wherein the second stacked layer (Figs. 2/3, 100a-100f, plurality of layers, [0025]) has electrical and optical VIA's (Figs. 2/3, 24, TSVs) after bonding (Fig. 6, flowchart of the fabrication processes) the second stacked layer to the backplane (Figs. 2/3, 22, substrate). Though ENGLAND teaches the TSVs formation by backside grinding process followed by a deep Si etch [0026], ENGLAND as modified MCGRODDY does not explicitly disclose the microdevice array, wherein the second stacked layer has electrical and optical VIA's after bonding the stacked layers to the backplane. HUANG teaches the microdevice array (Figs. 2A/2B, LED, [0010]), wherein the second stacked layer (Figs. 2A/2B, 22, LED with layers 26, 28, 30, [0012]) has electrical and optical VIA's (Figs. 2A/2B, 34/38, TSV openings) after bonding the stacked layers are bonded to the backplane (Figs. 2A/2B, 20, substrate). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have ENGLAND as modified MCGRODDY to incorporate the teachings of HUANG such that the microdevice array, wherein the second stacked layer has electrical and optical VIA's after bonding the stacked layers to the backplane, so that TSV opening may be formed by penetrating various LED layers and enable to create an ohmic contact (HUANG, [0014-0015]). Though ENGLAND as modified by MCGRODDY, and HUANG teaches the through-silicon vias or TSVs, ENGLAND as modified by MCGRODDY, and HUANG does not explicitly disclose the microdevice array, wherein the second stacked layer has electrical and optical VIA's after bonding the stacked layers to the backplane. BOWER teaches the microdevice array (micro-LEDs, [0292]), wherein the second stacked layer has electrical and optical VIA's (electrical vias, [0321-0322]; Fig. 26, 28, optical vias, [0162-0163]), after bonding the stacked layers to the backplane. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have ENGLAND as modified by MCGRODDY, and HUANG to incorporate the teachings of BOWER such that the microdevice array, wherein the second stacked layer has electrical and optical VIA's after bonding the stacked layers to the backplane, so that through optical vias, the light is emitted from the light emitting areas of the inorganic light emitters (30); the light emitters (30) are then disposed in the optical vias, for example using micro transfer printing, and electrically connected using photolithography. The electrical cum optical vias can be formed in the light-absorbing material (42) and the electrically insulating layer, as needed, for example to make electrical connections to the light emitter (30) (BOWER, [0315], [0321-0322]). Regarding Claim 30, ENGLAND as modified by MCGRODDY, HUANG and BOWER teaches the microdevice array of claim 29. ENGLAND further teaches the microdevice array (Figs. 2/5, 20, micro-LED display assemblies) wherein the VIA's (Figs. 2/4, 24/50, TSVs) are aligned with the additional microdevices (Figs. 2/5, 20, micro-LED display assemblies) in the first and third stacked layers (Figs. 2/3, 100a-100f, plurality of layers, [0025]) and the pads (Fig. 2, 26/26a, metal pad/pads) in the other sub pixels (Fig. 2, 14a/14b) in the backplane (Fig. 2, 22, substrate). Regarding Claim 35, ENGLAND as modified by MCGRODDY teaches the microdevice array (Figs. 2/5, 20, micro-LED display assemblies) of claim 33. ENGLAND further teaches the microdevice array (Figs. 2/5, 20, micro-LED display assemblies), wherein the third stacked layers (Figs. 2/3, 100a-100f, plurality of layers, [0025]) have optical VIA's (Figs. 2/4, 24/50, TSVs) after bonding (Fig. 6, flowchart of the fabrication processes) to the backplane (Fig. 2, 22, substrate). Though ENGLAND teaches the TSVs formation by backside grinding process followed by a deep Si etch [0026], ENGLAND as modified by MCGRODDY does not explicitly disclose the microdevice array, wherein the second stacked layer has electrical and optical VIA's after bonding the stacked layers to the backplane. HUANG teaches the microdevice array (Figs. 2A/2B, LED, [0010]), wherein the second stacked layer (Figs. 2A/2B, 22, LED with layers 26, 28, 30, [0012]) has electrical and optical VIA's (Figs. 2A/2B, 34/38, TSV openings) after bonding the stacked layers are bonded to the backplane (Figs. 2A/2B, 20, substrate). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have ENGLAND as modified by MCGRODDY to incorporate the teachings of HUANG such that the microdevice array, wherein the second stacked layer has electrical and optical VIA's after bonding the stacked layers to the backplane, so that TSV opening may be formed by penetrating various LED layers and enable to create an ohmic contact (HUANG, [0014-0015]). Though ENGLAND as modified by MCGRODDY, and HUANG teaches the through-silicon vias or TSVs, ENGLAND as modified by MCGRODDY, and HUANG does not explicitly disclose the microdevice array, wherein the second stacked layer has electrical and optical VIA's after bonding the stacked layers to the backplane. BOWER teaches the microdevice array (micro-LEDs, [0292]), wherein the second stacked layer has electrical and optical VIA's (electrical vias, [0321-0322]; Fig. 26, 28, optical vias, [0162-0163]), after bonding the stacked layers to the backplane. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have modified ENGLAND as modified by MCGRODDY and HUANG to incorporate the teachings of BOWER such that the microdevice array, wherein the second stacked layer has electrical and optical VIA's after bonding the stacked layers to the backplane, so that through optical vias, the light is emitted from the light emitting areas of the inorganic light emitters (30); the light emitters (30) are then disposed in the optical vias, for example using micro transfer printing, and electrically connected using photolithography. The electrical cum optical vias can be formed in the light-absorbing material (42) and the electrically insulating layer, as needed, for example to make electrical connections to the light emitter (30) (BOWER, [0315], [0321-0322]). Regarding Claim 36, ENGLAND as modified by MCGRODDY, HUANG and BOWER teaches the microdevice array of claim 35. ENGLAND further teaches the microdevice array (Figs. 2/5, 20, micro-LED display assemblies), wherein the VIA's (Figs. 2/3, 24, TSVs) are aligned with microdevices (Figs. 2/5, 20, micro-LED display assemblies) in first and second stacked layers (Figs. 2/3, 100a-100f, plurality of layers, [0025]) and the pads (Figs. 2, 26/26a, metal pad/pads) in the other sub pixels (Fig. 2, 14a/14b) in the backplane (Fig. 3, 22, substrate). Regarding Claim 37, ENGLAND as modified by MCGRODDY, HUANG and BOWER teaches the microdevice array of claim 36. ENGLAND further teaches the microdevice array (Figs. 2/5, 20, micro-LED display assemblies) wherein VIA's (Figs. 2/4, 24/50, TSVs) have passivated sidewalls ([0026]) with reflective layers on the sidewalls. HUANG further teaches the microdevice array (Figs. 2A/2B, LED, [0010]), wherein electrical VIA's (Fig. 7A, 42/44, TSVs) have passivated sidewalls (Fig. 7A, 39, isolation layers, [0017]) and conductive layers formed on the walls or a pad with reflective layers on the sidewalls ([0004], [0022]) from inside the electrical VIA. Claim(s) 31-32 is/are rejected under 35 U.S.C. 103 as being unpatentable over ENGLAND, in view of MCGRODDY, BOWER as applied to claim(s) 14, 27-28 and 34, and HUANG as applied to claim(s) 7-12 and 24 above. Regarding Claim 31, ENGLAND as modified by MCGRODDY and BOWER teaches the microdevice array of claim 27. ENGLAND further teaches the microdevice array (Figs. 2/5, 20, micro-LED display assemblies) wherein electrical VIA's (Figs. 2/4, 24/50, TSVs) have passivated sidewalls ([0026]) and the conductive layers formed on the walls of electrical VIA’s or pad (Fig. 2, 26/26a, metal pad/pads). ENGLAND as modified by MCGRODDY and BOWER does not explicitly disclose the microdevice array, wherein electrical VIA's have passivated sidewalls and conductive layers formed on the walls or a pad with reflective layers on the sidewalls from inside the electrical VIA. HUANG teaches the microdevice array (Figs. 2A/2B, LED, [0010]), wherein electrical VIA's (Fig. 7A, 42/44, TSVs) have passivated sidewalls (Fig. 7A, 39, isolation layers, [0017]) and conductive layers formed on the walls or a pad with reflective layers on the sidewalls ([0004], [0022]) from inside the electrical VIA. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have ENGLAND as modified by MCGRODDY and BOWER to incorporate the teachings of HUANG such that the microdevice array, wherein electrical VIA's have passivated sidewalls and conductive layers formed on the walls or a pad with reflective layers on the sidewalls from inside the electrical VIA, so that to achieve the efficient light reflecting characteristics of the micro-LEDs (HUANG, [0004]). Regarding Claim 32, ENGLAND as modified by MCGRODDY and BOWER teaches the microdevice array of claim 27. BOWER further teaches the microdevice array (micro-LEDs, [0292]), with optical VIA's (Fig. 26, 28, optical vias, [0162-0163]). ENGLAND as modified by MCGRODDY and BOWER does not explicitly disclose the microdevice array, wherein optical VIA's have passivated sidewalls with reflective layers on the sidewalls. HUANG teaches the microdevice array (Figs. 2A/2B, LED, [0010]), wherein optical VIA's (Fig. 7A, 42/44, TSVs) have passivated sidewalls (Fig. 7A, 39, isolation layers, [0017]) with reflective layers ([0004], [0022]) on the sidewalls. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have ENGLAND as modified by BOWER to incorporate the teachings of HUANG such that the microdevice array, wherein optical VIA's have passivated sidewalls with reflective layers on the sidewalls, so that to achieve the efficient light reflecting characteristics of the micro-LEDs (HUANG, [0004]). Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US 20170345867 A1 – Figures 55A-55D STATEMENT OF RELEVANCE – A structure with color conversion for defining pixel color while the pixelation is done with current confinement methods. US 20180090058 A1 – Figure 16 STATEMENT OF RELEVANCE – A cross section view of array of micro-LEDs with integrated micro reflectors and microlenses. Any inquiry concerning this communication or earlier communications from the examiner should be directed to SESHA SAIRAMAN SRINIVASAN whose telephone number is (703)756-1389. The examiner can normally be reached Monday-Friday 7:30 AM -5:30 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, MARLON T FLETCHER can be reached at (571)272-2063. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /SESHA SAIRAMAN SRINIVASAN/ Examiner, Art Unit 2817 /BRADLEY SMITH/ Primary Examiner, Art Unit 2817