DETAILED ACTION
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on June 11, 2026, has been entered.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the to separate1 a region where the direct-current block device is present and a region where the optical communication element and the electronic circuit element are present, must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
Claim Rejections - 35 USC § 112
The prior §12 rejection is with withdrawn in view of the amended claims.
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-8 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 1 is currently amended to recite “…to separate a region where the direct-current block device is present and a region where the optical communication element and the electronic circuit element are present…”. The amended claim language adds new matter and is not found in the original disclosure. This amendment is different in scope than what the originally filed specification disclosed, to separately define is to simply make two regions distinguishable in some manner. However, to separate… one region and another region2, when the two regions are still clearly next to one another in the same locations on the same continuous substrate, is not supported. The claimed regions are not separated.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-8 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 is amended to recite “…to separate a region where the direct-current block device is present and a region where the optical communication element and the electronic circuit element are present…”. The metes and bounds are unclear with respect to the claimed to separate one region and another region in view of the conventional/plain meaning of to separate one region and another region (also see rejection above), since Fig. 6 of the instant application shows the regions have not been separated. It is unclear how to interpret this limitation in view of the specification and Applicant’s remarks. For the purpose of examination this will be treated as two regions having the projecting portion between them.
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 1-7 are rejected under 35 U.S.C. 103 as being unpatentable over Ding et al. (US 2017/0261708) in view of Hiroshi (JP 2005-136272), all of record.
(Re Claim 1) Ding teaches an optical communication component comprising:
a package substrate having a flat plate shape (see Figs. 1-3, package substrate 101 PCB); an optical communication element (123) mounted on an upper surface of the package substrate; an electronic circuit element (124) mounted on the upper surface of the package substrate and located at a position different from that of the optical communication element (see Figs. 1-3, ¶¶27-29); a direct-current block device (capacitor 131 or 132) mounted on the upper surface of the package substrate and located at a position different from those of the optical communication element and the electronic circuit element to cut off a direct-current signal included in a high-frequency signal transmitted to the electronic circuit element via a conductive pattern (105) provided on the package substrate (see Figs. 1-3, ¶¶27-29).
Ding fails to teach the claimed lid and its separating projecting portion contacting a ground conducting pattern on the upper surface of the package substrate between the region where the direct-current block device is present and a region where the optical communication element and the electronic circuit element are present. Ding clearly teaches multiple ground planes with respect to 110 and 123 which are connected to 101 through interposer 125, thus the wiring 105 at/in the surface of the substrate 101 between 125 and 131 contains at least one ground conducting pattern, e.g. a ground electrode, as this is the only possible ground connection between the chip(s), interposer, and substrate (see Fig. 2, ¶¶42-45 and claims 3, 5, 9, and 11).
Related art from Hiroshi teaches a lid (Figs. 1-2, lid 12) provided over an upper portion of the package substrate to cover the electronic circuit element (Figs.1-2, 11, 14, lines 231-234) and the direct-current block device (passive element, lines 85-92, lines 98-100, lines 132-135), the lid 12 having a separation projecting portion 12b that projects toward the upper surface of the package substrate to separately define a region where the direct-current block device (passive element, lines 85-92, lines 98-100, lines 132-135) is present and a region where the electronic circuit element are present (Figs. 1-2, 11, 14, lines 231-234). Hiroshi teaches a ground electrode 9 is provided in a surface layer of the metal via wire (7a, 7b) and the ground electrode is electrically connected 13 to a tip surface of the separation projecting portion 12b of the lid 12 (Figs. 1 & 2). A PHOSITA would find it obvious to incorporate the teachings of Hiroshi to provide a ground electrode in a surface layer of the metal via wire, i.e. a ground conducting pattern, and the ground electrode is electrically connected to a tip surface of the separation projecting portion of the lid to function as the connection between the ground and grounded optical communication component package.
Hiroshi teaches when noisy high frequency components are present in a multi-component package, high frequency noise is an issue leading to unwanted crosstalk between the components, especially if they are close together. Hiroshi solves this problem by using a lid having a projecting partition to shield the components from each other. The partition prevents noise and crosstalk between the components. A PHOSITA would recognize this would be advantageous to Ding’s multi-component package also having high frequency components mounted together on a package substrate.
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Ding to incorporate the teachings of Hiroshi to provide the lid over an upper portion of the package substrate to cover the optical communication element, the electronic circuit element, and the direct-current block device, the lid having a separation projecting portion that projects toward the upper surface of the package substrate to separately define a region where the direct-current block device is present and a region where the optical communication element and the electronic circuit element are present to provide physical protection, EMI shielding, heat dissipation, and isolate the devices from one another thereby reducing noise between adjacent devices in the package (also see Hiroshi lines 157-223). Also, when placing Hiroshi’s lid onto Ding’s package substrate PCB 101, the projecting portion 12b will contact the upper surface of PCB 101, in particular at a location between 131 and 123 where wiring 105 is already present, thereby partitioning the components to mitigate noise and crosstalk. Noting Hiroshi’s lid is grounded through the surface wiring 1/13 connected to the ground through-holes 7a/7b (lines 260-261, lines 284-293) to provide EMI shielding, a PHOSITA would recognize the lid having the projecting portion should similarly connect to Ding’s surface wiring to similarly provide a ground connection to similarly provide EMI shielding. Thus, a PHOSITA would find it obvious to similarly connect the lid in Ding’s device such that the projecting portion contacts the conducting pattern on the upper surface of the package substrate to provide a grounded lid.
(Re Claim 2) wherein the lid is at a ground potential.
Ding in view of Hiroshi teaches the lid is at a ground potential, see claim 1 rejection above. Ding notes the package substrate having a ground plane (¶¶42-45 and claims 3, 5, 9, and 11). Hiroshi teaches wherein the lid is at a ground potential (lid 12, lines 260-261, lines 284-293). When adding Hiroshi’s lid to Ding’s package substrate, a PHOSITA would find it obvious to it connect the lid to ground as taught by Hiroshi as this will provide for conventional EMI shielding and provide a path to ground for ESD protection.
(Re Claim 3) the conductive pattern on the package substrate includes RF wires placed to connect, as a whole, the direct-current block device, the electronic circuit element, and the optical communication element such that the direct-current block device is interposed between the RF wires (see Fig. 2, direct-current block device 131, electronic circuit element 124, optical communication element 123, RF wires 105, ¶¶27,36).
(Re Claim 4) a portion of each of the RF wires has a wiring structure in which the portion of the RF wire temporarily extends into an inner layer of the package substrate via one metal via wire and then returns again to a surface layer via another metal via wire at another position (RF wires 105, see annotated Fig. from Ding).
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(Re Claim 5) wherein the ground conducting pattern includes a ground electrode that is provided in a surface layer of the metal via wire and the ground electrode is electrically connected to a tip surface of the separation projecting portion of the lid.
Ding in view of Hiroshi teaches the ground conducting pattern includes a ground electrode electrically connected to a tip surface of the separation projecting portion of the lid as discussed above (see claim 1 rejection).
(Re Claim 6) the ground electrode 9 and the tip surface of the separation projecting portion 12b of the lid 12 are maintained in an electrically connected state by adhesive 13 fixation using an adhesive (Figs. 1 & 2).
(Re Claim 7) the adhesive is a non-conductive adhesive adhesively fixing a side wall of the separation projecting portion in the vicinity of the tip surface thereof to a top surface of the package substrate or a conductive adhesive adhesively fixing the ground electrode to the tip surface of the separation projecting portion (conductive adhesive 13 adhesively fixing the ground electrode 9 to the tip surface of the separation projecting portion 12b, lines 282-296, lines 296-302, lines 239-245).
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Ding and Hiroshi as applied above and further on view of Thacker et al. (US 2014/0321803), newly cited.
(Re Claim 8) Hiroshi teaches material of the lid is a metal material having a high thermal conductivity (copper, lines 273, lines 186-192).
Hiroshi and Ding are silent regarding connecting the package to a PCB, however it is noted Hiroshi’s package substrate would be conventionally mounted on a PCB using solder bumps 6. Related art form Thacker specifically teaches a chip package substrate 136, corresponding to Ding’s 101, is attached to another PCB (¶¶51, 61, 68). This would be obvious to a PHOSITA as this allows the package to connect to power, ground, I/O, and other components for functionality.
A material of the package substrate is a metal and a material of a conventional PCB is also metal, and the CTEs of metals will be “close”.
Response to Arguments
Applicant's arguments filed 6/11/2026 have been fully considered but they are not persuasive. Applicant argues the combination of Ding and Hiroshi do not teach the limitations of claim 1. The Examiner respectfully disagrees, see claim 1 rejection above.
Ding teaches essentially everything except for the lid with the protrusion, while Hiroshi teaches the lid with the protrusion that connects to ground wiring of the package substrate. The modification is to place a lid like Hiroshi’s onto Ding’s package shown in Fig. 2, and in doing so, the partition will be between the devices 123/124 and 131 and/or 132 as claimed and the tip connects to the wiring already available at the surface for a ground connection just like Hiroshi discloses. Ding fails to teach the claimed lid and its separating projecting portion contacting a ground conducting pattern on the upper surface of the package substrate between the region where the direct-current block device is present and a region where the optical communication element and the electronic circuit element are present. Ding clearly teaches multiple ground planes with respect to 110 and 123 which are connected to 101 through interposer 125, thus the wiring 105 at/in the surface of the substrate 101 between 125 and 131 contains at least one ground conducting pattern, e.g. a ground electrode, as this is the only possible ground connection between the chip(s), interposer, and substrate (see Fig. 2, ¶¶42-45 and claims 3, 5, 9, and 11). Related art from Hiroshi teaches a lid (Figs. 1-2, lid 12) provided over an upper portion of the package substrate to cover the electronic circuit element (Figs.1-2, 11, 14, lines 231-234) and the direct-current block device (passive element, lines 85-92, lines 98-100, lines 132-135), the lid 12 having a separation projecting portion 12b that projects toward the upper surface of the package substrate to separately define a region where the direct-current block device (passive element, lines 85-92, lines 98-100, lines 132-135) is present and a region where the electronic circuit element are present (Figs. 1-2, 11, 14, lines 231-234). Hiroshi teaches a ground electrode 9 is provided in a surface layer of the metal via wire (7a, 7b) and the ground electrode is electrically connected 13 to a tip surface of the separation projecting portion 12b of the lid 12 (Figs. 1 & 2). A PHOSITA would find it obvious to incorporate the teachings of Hiroshi to provide a ground electrode in a surface layer of the metal via wire, i.e. a ground conducting pattern, and the ground electrode is electrically connected to a tip surface of the separation projecting portion of the lid to function as the connection between the ground and grounded optical communication component package. Hiroshi teaches when noisy high frequency components are present in a multi-component package, high frequency noise is an issue leading to unwanted crosstalk between the components, especially if they are close together. Hiroshi solves this problem by using a lid having a projecting partition to shield the components from each other. The partition prevents noise and crosstalk between the components. A PHOSITA would recognize this would be advantageous to Ding’s multi-component package also having high frequency components mounted together on a package substrate. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Ding to incorporate the teachings of Hiroshi to provide the lid over an upper portion of the package substrate to cover the optical communication element, the electronic circuit element, and the direct-current block device, the lid having a separation projecting portion that projects toward the upper surface of the package substrate to separately define a region where the direct-current block device is present and a region where the optical communication element and the electronic circuit element are present to provide physical protection, EMI shielding, heat dissipation, and isolate the devices from one another thereby reducing noise between adjacent devices in the package (also see Hiroshi lines 157-223). Also, when placing Hiroshi’s lid onto Ding’s package substrate PCB 101, the projecting portion 12b will contact the upper surface of PCB 101, in particular at a location between 131 and 123 where wiring 105 is already present, thereby partitioning the components to mitigate noise and crosstalk. Noting Hiroshi’s lid is grounded through the surface wiring 1/13 connected to the ground through-holes 7a/7b (lines 260-261, lines 284-293) to provide EMI shielding, a PHOSITA would recognize the lid having the projecting portion should similarly connect to Ding’s surface wiring to similarly provide a ground connection to similarly provide EMI shielding. Thus, a PHOSITA would find it obvious to similarly connect the lid in Ding’s device such that the projecting portion contacts the conducting pattern on the upper surface of the package substrate to provide a grounded lid.
The test for obviousness is not whether the features of a secondary reference may be bodily incorporated into the structure of the primary reference; nor is it that the claimed invention must be expressly suggested in any one or all of the references. Rather, the test is what the combined teachings of the references would have suggested to those of ordinary skill in the art. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981).
In response to applicant's argument that the examiner's conclusion of obviousness is based upon improper hindsight reasoning, it must be recognized that any judgment on obviousness is in a sense necessarily a reconstruction based upon hindsight reasoning. But so long as it takes into account only knowledge which was within the level of ordinary skill at the time the claimed invention was made, and does not include knowledge gleaned only from the applicant's disclosure, such a reconstruction is proper. See In re McLaughlin, 443 F.2d 1392, 170 USPQ 209 (CCPA 1971).
In response to applicant's argument that Ding and Hiroshi do not recognize the problem addressed by Applicant, the fact that the inventor has recognized another advantage which would flow naturally from following the suggestion of the prior art cannot be the basis for patentability when the differences would otherwise be obvious. See Ex parte Obiaya, 227 USPQ 58, 60 (Bd. Pat. App. & Inter. 1985).
In response to applicant's arguments against the references individually, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986).
Ding modified to include a lid like Hiroshi’s lid with a protruding portion connected to ground as discussed above, such that the separation projecting portion 12b contacts the ground conductive pattern on the upper surface of the package substrate (Ding’s wiring/ground discussed above, and obvious to provide ground in wiring 105 at surface as the ground planes of the two dies connected to the interposer must be connected to ground in the substrate 101 and this is the only available location for this, Hiroshi’s ground 9 connected to wiring 7/7a and 13 on 12b), and such that the protruding portion 12b contacts the surface of the substrate 101 where wiring 105 is located between 131 and 123/124 and/or on the opposite side between 132 and 123/124 thereby separately defining a region containing the direct-current block device 131/132 from a region containing the optical communication element and the electronic circuit element 123/124 while the direct-current block device 131/132 remains part of the high-frequency signal path (see Ding’s Fig. 2, 131 and 132 remain in the circuit, placing Hiroshi’s lid over the structure shown in Fig. 2 does not remove or disconnect components 131/132 from the circuit.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIK T. K. PETERSON whose telephone number is (571)272-3997. The examiner can normally be reached M-F, 9-5 pm (CST).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Manno can be reached at 571-272-2339. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ERIK T. K. PETERSON/ Primary Examiner, Art Unit 2898
1 To separate one region and another region means to divide, disconnect, detach, or split the regions, so that they are no longer joined or connected. Also see §112 rejections in the Final mailed 3/19/2025.
2 i.e. to cause to move apart, disconnect, sever, etc. e.g. to separate a wafer into individual dies.
Prosecution Insights