DETAILED ACTION
This Office Action is sent in response to Applicant’s Communication received 19 Feb 2026 for application number 17/768,746. The Office hereby acknowledges receipt of the following and placed of record in file: Applicant Arguments/Remarks, and Claims.
Claims 1-6 and 11-17 are presented for examination. Non-elected claims 7-10 have been cancelled.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant contends that the prior art does not teach, “a top cut particle diameter…defined as a particle diameter (D100) where the cumulative frequency in particle size distribution of the filler becomes 100%”; Examiner respectfully disagrees. This definition essentially suggests that particle size is equal to or below a certain threshold. Therefore, the particle size taught Yamada, for instance, reads on this definition because Yamada’s particle size indicates a value in which the size of the particles is a certain value; meaning, the particles are equal to or below that value. Therefore, the prior art teaches, “a top cut particle diameter…defined as a particle diameter (D100) where the cumulative frequency in particle size distribution of the filler becomes 100%.”
Further, Applicant contends that the motivation to combine Yamada and Suryakumar is improper; Examiner respectfully disagrees. The Examiner recognizes that obviousness may be established by combining or modifying the teachings of the prior art to produce the claimed invention where there is some teaching, suggestion, or motivation to do so found either in the references themselves or in the knowledge generally available to one of ordinary skill in the art. See In re Fine, 837 F.2d 1071, 5 USPQ2d 1596 (Fed. Cir. 1988), In re Jones, 958 F.2d 347, 21 USPQ2d 1941 (Fed. Cir. 1992), and KSR International Co. v. Teleflex, Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007). In this case, one of ordinary skill in the art would be motivated to obtain a method of manufacturing a device with a D/G ratio less than 1.5 to provide the predictable result of improving device quality by providing reliable connections by increasing filling properties of resin into gaps between connections thereby reinforcing connection portions.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-2, 5, and 11-17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yamada et al. [hereinafter as Yamada] (US 2013/0234308 A1) in view of Suryakumar (US 2007/0231951 A1).
In reference to claim 1, Yamada teaches A method for manufacturing an electronic component device, the method comprising, in the stated order:
a step of providing a carrier substrate [base material 155/adhesion layer 154; Fig. 15B, para 0095] comprising a support [155] and a temporary fixing material layer [154] provided on the support [155];
a step of disposing an IC chip [chip 153; Fig. 15B, para 0095] and a chip-type passive component [semiconductor package 152; Fig. 15B, para 0095] on the temporary fixing material layer [154], the passive component [152] having a main body part [152] and a connection part [soldered ball electrode 150; Fig. 15B, para 0095] provided on an outer surface of the main body part [152], the connection part [150] being interposed between the main body part [152] and the temporary fixing material layer [154] to form a gap [gap, hereinafter as “GP”, exists between 152 and 154] between the main body part [152] and the temporary fixing material layer [154];
a step of forming a sealing layer [resin layer 156; Fig. 15C, para 0095] sealing the IC chip [153] and the passive component [152] on the temporary fixing material layer [154] by a sealing material comprising a curable resin and a filler [156 is a resin with filler particles, hereinafter as “FP”; para 0095];
a step of curing [156 is baked, and thus cured; para 0095] the sealing layer [156] to form a sealed structure [structures shown in Figs. 15C-D] having the IC chip [153], the passive component [152], and the cured sealing layer [156]; and
a step of peeling off [sealed structure removed from 154/155] the carrier substrate [154/155] from the sealed structure [structures shown in Figs. 15C-D], wherein
when a top cut particle diameter of the filler [FP], defined as a particle diameter (D100) where the cumulative frequency in particle size distribution of the filler becomes 100% [Yamada teaches a particle diameter which satisfies the definition of having a particle size equal to or below a threshold], is designated as D [FP diameter may be 20 to 50 µm; para 0095] and a width of the gap [GP] between the main body part [152] and the temporary fixing material layer [154] is designated as G, and wherein
the sealing layer [156] is formed so as to entirely cover [156 entirely covers 153 and 152] the IC chip [153] and the passive components [152], and to fill the gap [GP] with the sealing material [material of 156].
However, Yamada does not explicitly teach D/G is 1.5 or less; in which the top cut particle diameter of the filler satisfies D/G being 1.5 or less.
Suryakumar teaches D/G is 1.5 or less; in which the top cut particle diameter of the filler satisfies D/G being 1.5 or less [para 0031 discloses that the particle diameter is one third the size of the gap; therefore, the D/G ratio would be 1/3 or approximately 0.333].
It would have been obvious to one of ordinary skill in art, absent unexpected results, having the teachings of Yamada and Suryakumar before the effective filing date of the claimed invention, to include the D/G ratio as disclosed by Suryakumar into the method of manufacturing the device of Nakamura in order to obtain a method of manufacturing a device with a D/G ratio less than 1.5.
One of ordinary skill in the art would be motivated to obtain a method of manufacturing a device with a D/G ratio less than 1.5 to provide the predictable result of improving device quality by providing reliable connections by increasing filling properties of resin into gaps between connections thereby reinforcing connection portions.
In reference to claim 2, Yamada and Suryakumar teach the invention of claim 1.
Yamada teaches The method according to claim 1, wherein D is 30 µm or less [FP diameter may be 20 to 50 µm].
In reference to claim 5, Yamada and Suryakumar teach the invention of claim 1.
Yamada teaches The method according to claim 1, further comprising a step of forming a redistribution layer [redistribution layer 246; Figs. 22-23, paras 0075-0076] having a wiring connected to the IC chip [semiconductor chip or passive component 241, 242; analogously, 153] and the connection part [ball electrode 243/232; Fig. 22, paras 0075-0076; analogously, 150] on one main surface side [246 formed on one side of structure] of the sealed structure [structure sealed in 244 in Fig. 22, analogously, the sealed structure shown in Fig. 15D, without 154/155] after the step of peeling off [this is done after the peeling step, as the sealed structure does not have 154/155] the carrier substrate [154/155] from the sealed structure [structure sealed in 244 in Fig. 22, analogously, the sealed structure shown in Fig. 15D, without 154/155].
In reference to claim 11, Yamada and Suryakumar teach the invention of claim 1.
Yamada teaches The method according to claim 1, wherein the sealing layer is formed in a mold by compression molding or transfer molding using the sealing material comprising the curable resin and the filler [although the embodiment of Fig. 15C discloses a first resin layer 156 formed by printing (para 0095), Yamada teaches forming an encapsulating resin by molding (paras 0042, 0048, 0056, 0127); it would have been obvious to one of ordinary skill in the art to modify the embodiment of Fig. 15C to use a molding resin to provide the predicable result of providing reliable connections by increasing filling properties using known methods, thereby providing predictable results; Examiner notes that compression molding and transfer molding are known methods of encapsulation using molding resin].
In reference to claim 12, Yamada and Suryakumar teach the invention of claim 1.
Suryakumar teaches The method according to claim 1, wherein the filler satisfies D/G is 1.5 or less and 0.1 or more [para 0031 discloses that the particle diameter is one third the size of the gap; therefore, the D/G ratio would be 1/3 or approximately 0.333].
In reference to claim 13, Yamada and Suryakumar teach the invention of claim 1.
Suryakumar teaches The method according to claim 1, wherein the filler satisfies D/G is 1.5 or less and 0.2 or more [para 0031 discloses that the particle diameter is one third the size of the gap; therefore, the D/G ratio would be 1/3 or approximately 0.333].
In reference to claim 14, Yamada and Suryakumar teach the invention of claim 1.
Suryakumar teaches The method according to claim 1, wherein the filler satisfies D/G is 1.5 or less and 0.3 or more [para 0031 discloses that the particle diameter is one third the size of the gap; therefore, the D/G ratio would be 1/3 or approximately 0.333].
In reference to claim 15, Yamada and Suryakumar teach the invention of claim 1.
Suryakumar teaches The method according to claim 1, wherein the filler satisfies D/G is 1.3 or less and 0.1 or more [para 0031 discloses that the particle diameter is one third the size of the gap; therefore, the D/G ratio would be 1/3 or approximately 0.333].
In reference to claim 16, Yamada and Suryakumar teach the invention of claim 1.
Suryakumar teaches The method according to claim 1, wherein the filler satisfies D/G is 1.3 or less and 0.2 or more [para 0031 discloses that the particle diameter is one third the size of the gap; therefore, the D/G ratio would be 1/3 or approximately 0.333].
In reference to claim 17, Yamada and Suryakumar teach the invention of claim 1.
Suryakumar teaches The method according to claim 1, wherein the filler satisfies D/G is 1.3 or less and 0.3 or more [para 0031 discloses that the particle diameter is one third the size of the gap; therefore, the D/G ratio would be 1/3 or approximately 0.333].
Claim(s) 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yamada in view of Suryakumar further in view of Lee et al. [hereinafter as Lee] (US 2008/0251940 A1).
In reference to claim 3, Yamada and Suryakumar teach the invention of claim 1.
However, Yamada and Suryakumar do not explicitly teach The method according to claim 1, wherein G is 10 µm or less.
Lee teaches G is 10 µm or less [Fig. 8C, para 0220 discloses that bumps may be 10 µm or less, i.e. the gap would be 10 µm or less].
It would have been obvious to one of ordinary skill in art, absent unexpected results, having the teachings of Yamada, Suryakumar, and Lee before the effective filing date of the claimed invention, to include the particular G value as disclosed by Lee into the method of manufacturing the device of Yamada and Suryakumar in order to obtain a method of manufacturing a device with a G value 10 µm or less.
One of ordinary skill in the art would be motivated to obtain a method of manufacturing a device with a G value 10 µm or less to provide the predictable result of cost reduction and space efficiency by creating a more compact device.
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yamada in view of Suryakumar further in view of Yamashita et al. [hereinafter as Yamashita] (US 2010/0265663 A1).
In reference to claim 4, Yamada and Suryakumar teach the invention of claim 1.
However, Yamada and Suryakumar do not explicitly teach The method according to claim 1, wherein a maximum width of the passive component is 6500 µm or less.
Yamashita teaches wherein a maximum width of the passive component is 6500 µm or less [passive component 25 may have width of 0.3 mm (300 µm) or 0.4 mm (400 µm), i.e. 6500 µm or less; Fig. 5, para 0098].
It would have been obvious to one of ordinary skill in art, absent unexpected results, having the teachings of Yamada, Suryakumar, and Yamashita before the effective filing date of the claimed invention, to include the particular width of passive components as disclosed by Yamashita into the method of manufacturing the device of Yamada and Suryakumar in order to obtain a method of manufacturing a device with a passive component with maximum width of 6500 µm or less.
One of ordinary skill in the art would be motivated to obtain a method of manufacturing a device with a passive component with maximum width of 6500 µm or less to provide the predictable result of cost reduction and space efficiency by creating a more compact device.
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yamada in view of Suryakumar further in view of Wang et al. [hereinafter as Wang] (US 2020/0083131 A1).
In reference to claim 6, Yamada and Suryakumar teach the invention of claim 5.
Yamada The method according to claim 5, wherein the IC chip [153] and the passive component [152] that constitute each of a plurality of electronic component devices are disposed on the temporary fixing material layer [154] of one sheet [one sheet of 155/154, as can be seen in Figs. 15B-C] of the carrier substrate [155/154].
However, Yamada and Suryakumar do not explicitly teach the method further comprises a step of dividing the sealed structure and the redistribution layer into individual electronic component devices after the step of forming the redistribution layer.
Wang teaches the method further comprises a step of dividing the sealed structure and the redistribution layer into individual electronic component devices after the step of forming the redistribution layer [Fig. 12, para 0105 discloses that an encapsulated structure with a redistribution layer 3 is divided, creating individual electronic component devices; 3 is clearly formed before the dividing; para 0103].
It would have been obvious to one of ordinary skill in art, absent unexpected results, having the teachings of Yamada, Suryakumar, and Wang before the effective filing date of the claimed invention, to include the dividing of a structure after forming a redistribution layer as disclosed by Wang into the method of manufacturing the device of Yamada and Suryakumar in order to obtain a method of manufacturing a device by dividing of a structure after forming a redistribution layer.
One of ordinary skill in the art would be motivated to obtain a method of manufacturing a device by dividing of a structure after forming a redistribution layer to provide the predictable result of creating smaller, more manageable, and more functional electronic components.
Conclusion
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/ANDREW CHUNG/
Examiner, Art Unit 2898