DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Action is FINAL and is in response to the amendment filed December 26th, 2025. Claims 1 and 7-8 are pending, of which claims 1 and 7-8 are currently rejected. Claims 2-6 have been cancelled by Applicant.
Response to Arguments
The amendment filed December 26th, 2025 has been entered. Claims 1 and 7-8 remain pending in the application. Applicant’s amendments and arguments to the Claims and Specification have overcome each and every objection and 112(b) rejection previously set forth in the Non-Final Office Action mailed September 30th, 2025.
Specification
Applicant has amended the specification to address the informalities. Therefore, the previous objections to the Specification have been withdrawn.
Claim Objections
Applicant has canceled the claims that were objected to, rendering the claim objections moot. Therefore, objections to the Claims have been withdrawn.
Claim Rejections – 35 USC § 112
Examiner has considered Applicant’s arguments with respect to interpretation under 112(f) and agrees. Therefore, the invocation of 35 U.S.C. 112(f) has been withdrawn.
Applicant has presented arguments with regards to the 112(b) rejection of claim 1, pointing to the antecedent basis of “a second input terminal”. Examiner agrees with Applicant and therefore has withdrawn 112(b) rejection of claim 1 and dependent claims. With regards to claim 5, claim 5 has been cancelled by Applicant rendering 112(b) rejection of claim 5 moot. Therefore, the previous rejection of claim 5 under 112(b) has been withdrawn.
Prior Art Rejections
Applicant’s arguments regarding the previously cited art have been fully considered and are persuasive. New grounds of rejection have been made by Examiner that are necessitated by the amendments. See Claim Rejections - 35 USC § 102.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 10/22/2025 is in compliance with the provisions of 37 CFR 1.97. It has been placed in the application file, and the information referred to therein has been considered as to the merits.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim 1 and 8 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Henry et al. (US 2017/0103304 A1) as included in the IDS filed 10/22/2025 (hereinafter “Henry”).
Regarding claim 1, Henry teaches:
An operation circuit comprising:
a first register (Fig. 23 208A), a second register (Fig. 23 208B), a third register (Fig. 23 202b), a fourth register (Fig. 30 3038), an adder (Fig. 23 2344A), a multiplier (Fig. 23 242A), a selector (Fig. 23 1896A), and a first memory unit (Fig. 23 data RAM),
wherein an output terminal of the first register is electrically connected to an input terminal of the second register (Fig. 23 mux-register 208A output terminal connected to input terminal of second mux-register 208B),
wherein an output terminal of the second register is electrically connected to a first input terminal of the multiplier (Fig. 23 mux-register 208B output terminal is connected to first input terminal of multiplier 242A through operand selection logic 1898),
wherein an output terminal of the multiplier is electrically connected to a first input terminal of the adder (Fig. 23 multiplier 242A output terminal is connected to first input terminal of adder 2344A through multiplexer 1896A),
wherein an output terminal of the adder is electrically connected to an input terminal of the third register (Fig. 23 adder 2344A output terminal connected to accumulator 202A i.e., third register),
wherein an output terminal of the third register is electrically connected to a first input terminal of the selector (Fig. 23 accumulator 202A has output terminal connected to AFU 212A, 212A being expanded upon in Fig. 30; within Fig. 30, connection 217 from third register connects output terminal to the selector MUX 3006, through 3002) and to an input terminal of another adder (and the another adder softplus 3026 (as known in the art softplus activation requires an adder) through 3008 and 3012),
wherein an output terminal of the selector is electrically connected to an input terminal of the fourth register (Fig. 30 input terminal of selector 3006 is connected to input terminal of fourth register output register 3038 through 3008, 3012, 3026, 3032, 3034, 3036, and 3037), wherein an output terminal of the fourth register is electrically connected to an input terminal of another selector (and input terminal to other selector, through output register connection 133, also seen in Fig. 7 133 leads to data RAM and weight RAM, which later comes through to another PE having another MUX-REG (other selector) as input),
wherein the first memory unit is electrically connected to a second input terminal of the multiplier (Fig. 23 narrow multiplier 242B takes input through MUX REG 208B/208A, both of which take input from data RAM or weight ram i.e., memory unit (connection 207A/B) as seen in Fig. 7), and
wherein the first memory unit is configured to read out first data corresponding to a context signal input to the first memory unit and to input the first data to the second input terminal of the multiplier (Fig. 7 first memory unit data RAM/weight RAM takes data word i.e., context signal received from memory through 207 as discussed in ¶ 0060).
Regarding claim 8, Henry teaches:
The operation circuit according to claim 1, wherein the another adder and the another selector are located outside the operation circuit (the another adder 3026 of Fig. 30 is part of the internal adder of activation circuit softplus as described at ¶ 0101 and thus is outside of the operation circuit; the another selector as described above would reside in a neighboring PE element, and thus is outside of the operation circuit).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 7 is rejected under Henry further in view Kurokawa (WO 2018/122658 A1) (hereinafter “Kurokawa”).
While Henry teaches the operation circuit of claim 1, Henry does not explicitly teach a housing.
However, Kurokawa teaches the product-sum operation circuits being employed in a variety of electronic devices (Kurokawa: ¶ 0337), these electronic devices having a housing (Kurokawa: ¶ 0338).
It would be obvious to combine the housing as taught by Kurokawa with the operation circuit as taught by Henry as all teachings are directed towards product sum operations. The improvement of Kurokawa lies in the semiconductor device being able to be used in a variety of applications and for a variety of purposes (Kurokawa: ¶ 0337 - ¶ 0338).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MARIA DE JESUS RIVERA whose telephone number is (571)272-2793. The examiner can normally be reached Monday-Friday 7:30AM-5PM.
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/M.D.R./Examiner, Art Unit 2151
/James Trujillo/Supervisory Patent Examiner, Art Unit 2151
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