Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Response to Amendment
Applicant’s amendments filed 11/13/2025 have been fully considered. The amendment of claims 11, 29, and 30 and the new claims 31-34 are acknowledged. The rejection of claim 30 under 35 U.S.C. 112 is withdrawn.
Drawings
The drawings are objected to because FIG. 3 steps VI and VII are the same figure and FIG. 5 steps VI and VII are the same figure. Both sets of new figures still show the ALD layer on the first hardmask already removed. The examiner acknowledges the added line with the tag “ALD layer” but no ALD layer is seed in the undercut structure in step VI as formed in step V. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Response to Arguments
Applicant’s arguments with respect to claims 11, 29, and 30 regarding the treated and passivated sidewalls have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Applicant's arguments regarding the combination of Tanaka and Wu have been fully considered but they are not persuasive. Applicant asserts that Wu teaches away from Tanaka due to the different device orientations and would not be obvious to combine. However, the examiner used Wu to teach dimensions of the microLED which are independent of the orientation of the devices.
Claims 31 and 34 are objected to because of the following informalities: the preamble states they are dependent on claim 1, which has been cancelled. The examiner understands the claims depend on either claim 11 or 30. For purposes of examination, they will be understood to depend on claim 11. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim 30 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. The claim recites “the mesa is tapered” and “the sidewalls include a ridge”. There is no written support for these limitations in the specification.
Claims 31-33 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. Claim 11 recites “a dielectric on the top surface”. Claim 31, which is understood to depend on claim 11, then recites “a first dielectric layer” and “a second dielectric layer”. The specification only teaches an ALD dielectric layer and a sputtered dielectric layer over the ALD layer, as indicated in page 16 lines 26-29 and page 17 lines 1-12. Claim 31 suggests that that the first and second dielectric layers are formed over the dielectric of claim 11, such that there are three dielectric materials over the mesa. It is not clear what corresponds to the second dielectric layer in the specification.
Claims 32-33 are rejected based on their dependency on claim 31.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 11-16, 19-20, 23-25, and 27-28 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 11 includes language at different stages of the manufacturing process, rendering the claim indefinite. The limitations “the sidewall of the mesa is treated and passivated so as to suppress a size dependent reduction in external quantum efficiency of the microLED as the area is reduced to 10 micrometers squared or less” appear to refer to an intermediate stage of manufacturing. The limitation suggests that the mesa is being processed and reduced in size. It is not clear if the claim pertains to a device with an area of 10 micrometers or less and with passivated sidewalls or if it pertains to a device before the reduction in size. For purposes of examination, claim 11 will be understood as a device with an area of 10 micrometers or less and with passivated sidewalls.
Claims 12-16, 19-20, 23-25, and 27-28 are rejected based on their dependence on claim 11.
Claim 30 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 30 includes language at different stages of the manufacturing process, rendering the claim indefinite. The limitations “the sidewall of the mesa is treated and passivated so as to suppress a size dependent reduction in external quantum efficiency of the microLED as the area is reduced to 10 micrometers squared or less” appear to refer to an intermediate stage of manufacturing. The limitation suggests that the mesa is being processed and reduced in size. It is not clear if the claim pertains to a device with an area of 10 micrometers or less and with passivated sidewalls or if it pertains to a device before the reduction in size. For purposes of examination, claim 30 will be understood as a device with an area of 10 micrometers or less and with passivated sidewalls.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 11-14, 19-21, 27 and 28 are rejected under 35 U.S.C. 103 as being unpatentable over Tanaka US 20030232455 A1 (hereinafter referred to as Tanaka), in view of Wu et al., US 20190115333 A1 (hereinafter referred to as Wu), in view of Bour et al. US 20160197232 A1 (hereinafter referred to as Bour).
Claim 11 is a product-by-process claim. A product-by-process claim is a product claim. Applicant has merely chosen to define the claimed product by the process by which it was made. It has been well established that process limitations do not impart patentability to an old/obvious product. Process limitations are significant only to the extent that they distinguish the claimed product over the prior art product. Even though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process. In re Thorpe, 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir.1985). In this case, the claimed “micro light emitting diode (microLED), comprising: a mesa comprising an epitaxial structure and having at least one of: a top surface with an area of 10 micrometers squared or less, or at least one of a diameter, a largest width, or a largest dimension of 10 micrometers or less; a dielectric on the top surface; and a hole in the dielectric that is centered or self aligned on the top surface; wherein the hole has a diameter of 2 microns or less and a hole has a first center within 0.5% of a second center of the top surface, the mesa sidewall is passivated and free of defects.” need not be formed by the process of and the sidewall of the mesa is treated and passivated so as to suppress a size dependent reduction in external quantum efficiency of the microLED as the area is reduced to 10 micrometers or less.”. Once the Examiner provides a rationale tending to show that the claimed product appears to be the same or similar to that of the prior art, although produced by a different process, the burden shifts to applicant to come forward with evidence establishing an unobvious difference between the claimed product and the prior art product. In re Marosi, 710 F.2d 798, 802, 218 USPQ 289, 292 (Fed. Cir.1983).
Tanaka teaches
A light emitting diode (“semiconductor light-emitting element 10” para. 0048 FIG. 1A and 2), comprising:
a mesa (“GaN-based semiconductor laminate 40” forms a mesa structure over the “light guide 30” and “monocrystal silicon substrate 20” as seen in FIG. 2, para.0048, 0050, and 0053) comprising an epitaxial structure (“GaN-based semiconductor laminate 40” is comprised of “N-type semiconductor layer 41”, “activation layer 42”, and “P-type semiconductor layer 43” that are epitaxially grown, para. 0050 FIG. 2) and
a dielectric (“insulating layer 61” para. 0051 FIG. 2) on the top surface; and
a hole in the dielectric that is centered or self aligned on the top surface (“The insulating layer covers the uppermost layer of the GaN-based semiconductor laminate 40 other than a predetermined center region”, the predetermined region being the “mouth 61a”, para. 0051, as seen in FIG. 2),
wherein the hole has a first center within 0.5% of a second center of the top surface (Tanaka teaches that “insulating layer 61” has a “mouth 61a” in a “predetermined center region” above the “GaN-based semiconductor laminate 40” (para. 0051, as seen in FIG. 2). From this, it is understood that the center of the mouth is substantially in the center of the top surface of the “GaN-based semiconductor laminate 40”.).
However, Tanaka fails to teach the micro light emitting diode having at least one of: a top surface with an area of 10 micrometers squared or less, or at least one of a diameter, a largest width, or a largest dimension of 10 micrometers or less, wherein the hole has a diameter of 2 microns or less, the mesa sidewall is passivated and free of defects.
Nevertheless, Wu teaches
The micro light emitting diode (“micro light-emitting devices 120” para. 0031 FIG. 1B), having at least one of: a top surface with an area of 10 micrometers squared or less, or at least one of a diameter, a largest width, or a largest dimension of 10 micrometers or less (“the maximum width of the vertical type micro LEDs may be 1 μm-100 μm” para. 0033 FIG. 1B).
Tanaka and Wu teach light emitting devices. Wu teaches micro LEDs comprising an “epitaxial structure 122” (para. 0031) with a maximum width as low as 1-2μm for use in a micro LED display device. The examiner understands that by making light-emitting diodes smaller they can be more densely packed in a given surface area to offer greater image resolution. One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that micro light emitting diodes allow for higher resolution displays than larger LEDs in a same surface area.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the light emitting device taught in Tanaka with the maximum width taught in Wu. By making the LED a micro light emitting diode, a display of higher resolution is obtained.
However, Tanaka modified by Wu fails to expressly teach wherein the hole has a diameter of 2 microns or less, the mesa sidewall is passivated and free of defects.
Nevertheless, Tanaka teaches that “insulating layer 61 has a mouth 61a, which is diametrically smaller than the mouth 31a of the hole 31” (Tanaka para. 0051), which implies a circular shape. Wu teaches that the maximum width of the “micro light-emitting devices 120” is 1m (Wu para. 0033). By making the microLED with a maximum diameter between 1-2µm as taught in Wu, forming “mouth 61a” as taught in Tanaka implies the “mouth 61a” has a diameter less than the diameter than the microLED. Part of “insulating layer 61” should still cover the top surface so that the emission area is in the central region (Tanaka para. 0054). One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that forming a hole in an insulating layer on top of a microLED as taught in Tanaka will have a smaller diameter than the microLED.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further modify the microLED taught between Tanaka and Wu. To make the microLED smaller and maintain the emission area at the center, the diameter of the hole has to scale down accordingly. For a microLED with a greatest diameter of 2 microns or less, the diameter of the hole will be smaller than the microLED diameter.
However, Tanaka, modified and Wu, fails to teach the mesa sidewall is passivated and free of defects.
Nevertheless, Bour teaches a “sidewall passivation layer 170” formed over a “mesa structure 120” made of GaN that forms a “LED 150” (para. 0070 and 0116-0117 FIG. 17A- 17F). In LEDs, efficiency degradation may occur due to non-radiative recombination at the LED sidewalls when the sidewalls have unsatisfied bonds, chemical contamination, and structural damage (para. 0051). Passivation of the sidewall surface of the LED mesas reduces the amount of non-radiative recombination near the exterior or side surfaces of the active layer, such that efficiency of the LED device increased (para. 0052). One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that passivation of the sidewalls of the “semiconductor laminate 40” in Tanaka with the “sidewalls passivation layer 170” can prevent non-radiative recombination around the sidewalls and improve device efficiency.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the micro light emitting device taught between Tanaka and Wu with the passivated mesa sidewall from Bour. Passivated sidewalls improve the emission efficiency of the device.
Regarding claim 12, Tanaka, modified by Wu and Bour, teaches the micro light emitting diode of claim 11 but fails to expressly teach the area being: 1 micron squared or less, or 0.5 microns squared or less (the maximum width of the “micro light-emitting devices 120” in Wu can be 1μm. As such, it is understood that 1µm is the greatest extent on the top and bottom surfaces of the “micro light-emitting devices 120”).
Regarding claim 13, Tanaka, modified by Wu and Bour, teaches the micro light emitting diode of claim 11. Tanaka fails to teach comprising at least one of the diameter, the largest width, or the largest dimension being: 5 microns or less, 1 micron or less, or 0.5 microns or less.
Nevertheless, Wu teaches
at least one of the diameter, the largest width, or the largest dimension being: 5 microns or less, 1 micron or less, or 0.5 microns or less (“the maximum width of the vertical type micro LEDs may be 1 μm-100 μm” para. 0033 FIG. 1B).
Tanaka and Wu teach light emitting devices. Wu teaches micro LEDs comprising an “epitaxial structure 122” (para. 0031) with a maximum width as low as 1μm or use in a micro LED display device. The examiner understands that by making light-emitting diodes smaller they can be more densely packed in a given surface area to offer greater image resolution. One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that micro light emitting diodes allow for higher resolution displays than larger LEDs in a same surface area.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further modify the light emitting device taught between Tanaka, Wu, and Bour with the maximum width taught in Wu. By making the LED a micro light emitting diode, a display of higher resolution is obtained.
Regarding claim 14, Tanaka, modified by Wu and Bour, teaches the micro LED of claim 11. Tanaka further teaches
wherein the micro LED comprises III-nitride (“semiconductor laminate 40” is GaN-based, “N-type semiconductor layer 41” comprising GaN or AlGaN, “activation layer 42” comprising InGaN, and “P-type semiconductor layer 43” comprising GaN or AlGaN, para. 0050).
Regarding claim 19, Tanaka, modified by Wu and Bour, teaches the micro light emitting diode of claim 11. Tanaka, modified by Wu and Bour, fails to expressly teach wherein the light emitting diode is plasma damage free.
Nevertheless, Tanaka teaches that the “GaN-based semiconductor laminate 40” can be made by selective epitaxial growth as an alternative to epitaxially growing across a large surface and then removing portions by etching (para. 0059). “Selective-area growth (SAG), which is also called selective growth (SG), selective epitaxy (SE), selective-area epitaxial growth (SAEG), and selective epitaxial growth (SEG), involves epitaxial growth of materials on nonmasked (window) regions” as defined in Ryou and Lee (see page 60, “3.4.1. Selective area growth and epitaxial lateral overgrowth of GaN” in Nitride Semiconductor Light-Emitting Diodes, by Jae-Hyun Ryou, Wonseok Lee. Plasma is a known etchant, as evidenced in para. 0116 in Okagawa et al. US 20080135868 A1, and the selective epitaxial growth in Tanaka would not require the use of an etchant as plasma. Furthermore, even though “mouth 61a” may be made by etching, there is no indication of plasma being used as an etchant. Furthermore, the use of “passivation layer 170” from Bour is understood to passivate any defect sites on the sidewalls. One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that there is no plasma damage since there is no plasma etching in the process of forming the “semiconductor laminate 40” in Tanaka.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the light emitting diode is plasma damage free.
Regarding claim 20, Tanaka, modified by Wu and Bour, teaches the micro light emitting diode of claim 11 but fails to teach an array of the micro light emitting diodes of claim 11.
Nevertheless, Wu teaches
an array of the micro light emitting diodes (“a plurality of micro light-emitting devices 120” in a patterned arrangement as seen in FIG. 1A, para. 0031).
Tanaka and Wu teach light emitting devices. Wu teaches “micro light-emitting devices 120” comprising “epitaxial structures 122”. The plurality of “micro light-emitting devices 120” form a “display apparatus 100a” (para. 0031 FIG. 1A). One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that a group of “micro light-emitting devices 120” can be arranged in an array for use in a display apparatus.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further modify the light emitting device taught between Tanaka, Wu, and Borr with the array of micro light emitting diodes taught in Wu. Arranging the micro light emitting diodes into an array allows for the formation of a display device to display images.
Regarding claim 21, Tanaka, modified by Wu and Bour, teaches the array of claim 20. Tanaka fails to teach a display comprising the array of claim 20, wherein the array comprises pixels each comprising at least one of the micro light emitting diodes.
Nevertheless, Wu teaches
a display (“display apparatus 100a” para. 0031 FIG. 1A) comprising the array of claim 20 (“a plurality of micro light-emitting devices 120” in a patterned arrangement as seen in FIG. 1A, para. 0031), wherein the array comprises pixels each comprising at least one of the micro light emitting diodes (At least three of the micro light-emitting devices 120 are disposed in each of the pixel regions 112”, para. 0031 FIG. 1A).
Tanaka and Wu teach light emitting devices. Wu teaches “micro light-emitting devices 120” comprising “epitaxial structures 122”. The plurality of “micro light-emitting devices 120” form a “display apparatus 100a” where “each of the micro light-emitting devices 120 is, for example, a sub-pixel capable of emitting lights of different colors” (para. 0031 FIG. 1A). One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that a group of “micro light-emitting devices 120” can be arranged in an array for use in a multicolor display apparatus.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further modify the light emitting device taught between Tanaka, Wu, and Bour with the display taught in Wu. Arranging the micro light emitting diodes into an array allows for the formation of a display device to display colored images.
Regarding claim 27, Tanaka, modified by Wu and Bour, teaches the microLED of claim11. Tanaka further teaches
wherein the epitaxial structure comprises or consists essentially of a semiconductor including comprising a III-nitride material or a III-V material (“semiconductor laminate 40” is GaN-based, “N-type semiconductor layer 41” comprising GaN or AlGaN, “activation layer 42” comprising InGaN, and “P-type semiconductor layer 43” comprising GaN or AlGaN, para. 0050).
Regarding claim 28, Tanaka, modified by Wu Bour, teaches the microLED of claim11. Tanaka further teaches
wherein the mesa includes sidewalls (“GaN-based semiconductor laminate 40”, para. 0051, has sidewalls, as seen in FIG. 2) and at least one of a dielectric or passivation on the sidewalls (“insulating layer 61”, para. 0051, is also formed along the sidewalls of the “GaN-based semiconductor laminate 40”, as seen in FIG. 2. As modified, “passivation layer 170” from Bour is formed on the sidewalls.).
Claims 15 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Tanaka, modified by Wu and Bour, as applied to claims 11 and 14 above, and further in view of Seong et al., US 20180026162 A1 (hereinafter referred to as Seong).
Regarding claim 15, Tanaka, modified by Wu and Bour, teaches the microLED of claim 14 but fails to teach further comprising metallization in the hole forming an ohmic contact with the epitaxial structure.
Nevertheless, Seong teaches
further comprising metallization (“p ohmic contact pattern 142” comprised of metal, para. 0047 FIG. 1B) in the hole (the space on “p-type GaP window layer 130” between “protection layer 180”, para. 0068 FIG. 1B) forming an ohmic contact with the epitaxial structure (“The p ohmic contact pattern 142 and the p-type GaP window layer 130 may be provided to form an ohmic junction”, para. 0047).
Tanaka, modified by Wu and Bour, and Seong teach light emitting diodes. Seong teaches that “the p ohmic contact pattern and the transparent conductive metal oxide pattern 144 may provide a current spreading effect and may serve as an electrode with low resistance and high transmittance” (para. 0047). One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that the “p ohmic contact pattern 142” can be used in conjunction with a “transparent conductive metal oxide pattern 144” as a low resistance electrode that helps spread the current across the epitaxial structure.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the microLED device as taught between Tanaka and Wu with the metallization as taught in Seong. The metallization forms an ohmic contact, which useful for forming an electrode structure with low resistance and helping with current spreading.
Regarding claim 16, Tanaka, modified by Wu and Bour, teaches the micro light emitting diode of claim 11. Tanaka further teaches
wherein:
the epitaxial structure comprises an n-type layer (of “N-type semiconductor layer 41” para. 0050 FIG. 2), a p-type layer (“P-type semiconductor layer 43” para. 0050 FIG. 2), and an active region (“activation layer 42” para. 0050 FIG. 2) between the n-type layer and the p-type layer, and the active region emits electromagnetic radiation in response an electric field across the n-type layer and the p-type layer, the electric field formed by a potential difference between the first contact and a second contact to the micro light emitting diode (“voltage application across the electrode layers 51 and 52 causes the activator 42 of the GaN-based semiconductor laminate 40 to emit blue-light”, para. 0054. The examiner understands that an electric field exists where there is a potential difference between two points, therefore an electric field exists between “electrode layers 51 and 52”. The electric field is what provokes electron movement.)
However, Tanaka, Wu, and Bour fails to teach a first contact in the hole forms an ohmic contact with the n-type layer or the p-type layer.
Nevertheless, Seong teaches
a first contact (“p ohmic contact pattern 142” comprised of metal, para. 0047 FIG. 1B) in the hole (the space on “p-type GaP window layer 130” between “protection layer 180”, para. 0068 FIG. 1B) forms an ohmic contact with the n-type layer or the p-type layer (“The p ohmic contact pattern 142 and the p-type GaP window layer 130 may be provided to form an ohmic junction”, para. 0047).
Tanaka, modified by Wu and Bour, and Seong teach light emitting diodes. Seong teaches that “the p ohmic contact pattern and the transparent conductive metal oxide pattern 144 may provide a current spreading effect and may serve as an electrode with low resistance and high transmittance” (para. 0047). One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that the “p ohmic contact pattern 142” can be used in conjunction with a “transparent conductive metal oxide pattern 144” as a low resistance electro that helps spread the current across the epitaxial structure.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the microLED device as taught between Tanaka, Wu, and Bour with the metallization as taught in Seong. The metallization forms an ohmic contact, which is useful for forming an electrode structure with low resistance and helping with current spreading.
Claim 23 and 25 are rejected under 35 U.S.C. 103 as being unpatentable over Tanaka, Wu, and Wu as applied to claim 11 above, and further in view of Muramoto US 20200098832 A1 (hereinafter referred to as Muramoto).
Regarding claim 23, Tanaka, modified by Wu and Bour, teaches the microLED of claim 11. Tanaka further teaches
the micro light emitting diode (“semiconductor light-emitting element 10” para. 0048 FIG. 1A and 2) emits electromagnetic radiation in response to a bias applied (“voltage application across the electrode layers 51 and 52 causes the activator 42 of the GaN-based semiconductor laminate 40 to emit blue-light” para. 0054) between a first contact (“first electrode layer 51” para 0051 FIG. 1A and 2) to the epitaxial structure (“GaN-based semiconductor laminate 40” para. 0054) in the hole (“mouth 61a” para. 0054 FIG. 2) and a second contact (“second electrode layer 52” para. 0051 FIG. 1A) to the epitaxial structure, and
the first contact is electrically connected to an n-type layer in the epitaxial structure and the second contact is electrically connected to a p-type layer in the epitaxial layer, or the first contact is electrically connected to the p-type layer (“P-type semiconductor layer 43 of the GaN-based semiconductor laminate 40 is connected to the first electrode layer 51” para. 0054 FIG. 1A) and the second contact is electrically connected to a n-type layer (“N-type semiconductor layer 41 is connected to the second electrode layer 52 via the monocrystal silicon substrate 20” para. 0054 FIG. 1A).
However, Tanaka, Wu, and Bour, fail to teach wherein: the micro light emitting diode emits electromagnetic radiation for a current density of at least 100 amps per centimeter square in response to a bias of at least 2.5 volts.
Nevertheless, Muramoto teaches a “UV-LED chip” (para. 0037 FIG. 2) described as having “microchip sizes” (para. 0083) that emits electromagnetic at a wavelength of 385 nm (para. 0037). The “UV-LED chip” is operated with a forward voltage of 3.4-3.5V and a current of 25.5 A/cm2 for different chip sizes (para. 0088 FIG. 13). The luminous intensity of the chip increases for increased current density and current densities as high as 357.1 A/cm2 are measured, as seen in FIG. 9. It is further evidenced in Valentine that “The amount of light emitted by the mLED increases as the amount of current supplied to the mLED increases” and “In some implementations, mLEDs are driven using a voltage controlled current source which generates a driving current that increases with the increase in the voltage level of a voltage signal” (Valentine para. 0003). One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that the microLED taught between Tanaka and Wu can have increased luminous intensity when operated at an elevated current density, the current density depending on the amount of forward voltage.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the microLED taught between Tanaka, Wu, and Bour with the current density and bias voltage taught between Muramoto and Valentine. The microLED will emit a greater amount of light when operated at a higher current density and the current density increases as the voltage bias increases.
Regarding claim 25, Tanaka, modified by Wu, Bour, and Muramoto, teaches the microLED of claim 23. Tanaka further teaches
wherein at least one of the first contact and the second contact comprise a metal layer (“first electrode layer 51 is formed by vacuum spattering or vapor deposition of an Au- or Ag-based conductive metal” para. 0051).
Claim 24 is rejected under 35 U.S.C. 103 as being unpatentable over Tanaka, Wu, Bour, and Muramoto as applied to claim 23 above, and further in view of Yonkee et al., US 20190207043 A1 (hereinafter referred to as Yonkee).
Tanaka, modified by Wu, Bour and Muramoto, teaches the microLED of claim 23 but fails to teach wherein the first contact or the second contact are connected to the p-type layer via an n-type region in a tunnel junction.
Nevertheless, Yonkee teaches
wherein the first contact (“n-contact metallization 1218” on “n-type material 1214c” para. 0156 and 0158 FIG. 12(a)) or the second contact (“n-contact metallization 1220” on “n-type III-nitride layer 1202” para. 0156 and 0151 FIG. 12(a)) are connected to the p-type layer (“p-type III-nitride layer 1208” para 0153 FIG. 12(a)) via an n-type region in a tunnel junction (“first n.sup.+-GaN/III-nitride layer 602, 1214a closest to the p-type III-nitride layer 1208, 618 can form the tunnel junction 1216” para. 0156 FIG. 12(a)).
Tanaka, modified by Wu, Bour, and Muramoto, and Yonkee, teach microLED devices. Yonkee teaches the formation of a “tunnel junction 1216” over a “p-type III-nitride layer 1208”. Yonkee teaches that “A low resistance tunnel junction on top of p-GaN would allow for current spreading in n-type GaN (n-GaN) on both sides of the device, as well as the use of low resistance n-type contacts on both sides of the device” (para. 0018). One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that the tunnel junction allows for the current to more evenly spread on both sides of the microLED device.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the microLED device taught between Tanaka, Wu, Bour, and Muramoto with thetunnel junction as taught in Yonkee. The tunnel junction is useful for current spreading on the p-type side of the microLED device.
Claim 29 is rejected under 35 U.S.C. 103 as being unpatentable over Tanaka US 20030232455 A1 (hereinafter referred to as Tanaka), in view of Wu et al., US 20190115333 A1 (hereinafter referred to as Wu), in view of Bour et al. US 20160197232 A1 (hereinafter referred to as Bour), and further in view of Lin et al., US 20120228655 A1 (hereinafter referred to as Lin).
Claim 29 is a product-by-process claim. A product-by-process claim is a product claim. Applicant has merely chosen to define the claimed product by the process by which it was made. It has been well established that process limitations do not impart patentability to an old/obvious product. Process limitations are significant only to the extent that they distinguish the claimed product over the prior art product. Even though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process. In re Thorpe, 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir.1985). In this case, the claimed “micro light emitting diode, comprising: a mesa comprising an epitaxial structure and having at least one of: a top surface with an area of 10 micrometers squared or less, or at least one of a diameter, a largest width, or a largest dimension of 10 micrometers or less; a dielectric on the top surface; and a hole in the dielectric that is centered or self aligned on the top surface; the epitaxial structure including an n-type layer, a p-type layer, and an active region between the n-type layer and the p-type layer, sidewalls of the mesa are free of dangling bonds and defects, an ALD layer on the sidewalls of the mesa” need not be formed by the process of “(b) depositing a first hardmask layer comprising a first material on the epitaxial structure;(c) depositing a second hardmask layer comprising a second material on the first hardmask layer, wherein the first hardmask layer and the second hardmask layer are at least partially resistant to a wet chemical solution used in step(e);(d) patterning the first hardmask layer, the second hardmask layer, and the epitaxial structure using lithography so as to form the mesa comprising the epitaxial structure, wherein the patterning includes selectively etching the first hardmask layer over the second hardmask layer so as to form an undercut structure comprising the second hardmask layer extending laterally beyond the edges of the underlying patterned first hardmask layer;(e) performing one or more sidewall treatments so as to remove impurities, defects and passivate dangling bonds from sidewalls of the mesa, wherein the sidewall treatments include a dip of the sidewalls in the wet chemical solution;(g) depositing the dielectric layer on the ALD layer using a directional deposition method so that a discontinuity in the dielectric layer is formed, the discontinuity exposing the ALD layer surrounding the first hardmask layer;(h) removing the ALD layer surrounding the first hardmask layer and exposed by the discontinuity, using an etching technique; and etching the first hardmask layer, thereby removing the first hardmask layer and all of the layers above the first hardmask layer, leaving the hole in the dielectric layer on top of the mesa having a location and a first area defined by the position and second surface area of patterned hardmask layer prior to removal of patterned first hardmask layer, so that the hole exposes the top surface of the epitaxial structure in the mesa. The steps (e)-(g) treat and passivate the sidewalls so as to suppress a size-dependent reduction in exernal quantum efficiency of the microLED as the area is reduced to 10 micrometers squared or less.”. Once the Examiner provides a rationale tending to show that the claimed product appears to be the same or similar to that of the prior art, although produced by a different process, the burden shifts to applicant to come forward with evidence establishing an unobvious difference between the claimed product and the prior art product. In re Marosi, 710 F.2d 798, 802, 218 USPQ 289, 292 (Fed. Cir.1983).
Tanaka teaches
A micro light emitting diode (“semiconductor light-emitting element 10” para. 0048 FIG. 1A and 2), comprising:
a mesa (“GaN-based semiconductor laminate 40” forms a mesa structure over the “light guide 30” and “monocrystal silicon substrate 20” as seen in FIG. 2, para.0048, 0050, and 0053) comprising an epitaxial structure (“GaN-based semiconductor laminate 40” is comprised of “N-type semiconductor layer 41”, “activation layer 42”, and “P-type semiconductor layer 43” that are epitaxially grown, para. 0050 FIG. 2) a dielectric (“insulating layer 61” para. 0051 FIG. 2) on the top surface; and
a hole in the dielectric that is centered or self aligned on the top surface (“The insulating layer covers the uppermost layer of the GaN-based semiconductor laminate 40 other than a predetermined center region”, referred to as “mouth 61a” para. 0051, as seen in FIG. 2),
the epitaxial structure including an n-type layer (“N-type semiconductor layer 41” para. 0050 , a p-type layer (“P-type semiconductor layer 43” para. 0050), and an active region (“activation layer 42” para. 0050) between the n-type layer and the p-type layer.
However, Tanaka fails to teach a micro light emitting diode having at least one of: a top surface with an area of 10 micrometers squared or less, or at least one of a diameter, a largest width, or a largest dimension of 10 micrometers or less, passivated dangling bonds from sidewalls of the mesa, an ALD layer on the sidewalls of the mesa.
Nevertheless, Wu teaches
micro light emitting diode (“micro light-emitting devices 120” para. 0031 FIG. 1B), having at least one of: a top surface with an area of 10 micrometers squared or less, or at least one of a diameter, a largest width, or a largest dimension of 10 micrometers or less (“the maximum width of the vertical type micro LEDs may be 1 μm-100 μm” para. 0033 FIG. 1B).
Tanaka and Wu teach light emitting devices. Wu teaches micro LEDs comprising an “epitaxial structure 122” (para. 0031) with a maximum width as low as 1μm or use in a micro LED display device. The examiner understands that by making light-emitting diodes smaller they can be more densely packed in a given surface area to offer greater image resolution. One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that micro light emitting diodes allow for higher resolution displays than larger LEDs in a same surface area.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the light emitting device taught in Tanaka with the maximum width taught in Wu. By making the LED a micro light emitting diode, a display of higher resolution is obtained.
However, Tanaka, modified by Wu, fails to teach sidewalls of the mesa are free of dangling bonds and defects, an ALD layer formed over sidewalls of the mesa.
Nevertheless, Bour teaches a “sidewall passivation layer 170” formed over a “mesa structure 120” made of GaN that forms a “LED 150” (para. 0070 and 0116-0117 FIG. 17A- 17F). In LEDs, efficiency degradation may occur due to non-radiative recombination at the LED sidewalls when the sidewalls have unsatisfied bonds, chemical contamination, and structural damage (para. 0051). Passivation of the sidewall surface of the LED mesas reduces the amount of non-radiative recombination near the exterior or side surfaces of the active layer, such that efficiency of the LED device increased (para. 0052). One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that passivation of the sidewalls of the “semiconductor laminate 40” in Tanaka with the “sidewalls passivation layer 170” can prevent non-radiative recombination around the sidewalls and improve device efficiency.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the micro light emitting device taught between Tanaka and Wu with the passivated mesa sidewall from Bour. Passivated sidewalls improve the emission efficiency of the device.
Claim 30 is rejected under 35 U.S.C. 103 as being unpatentable over Tanaka US 20030232455 A1 (hereinafter referred to as Tanaka), in view of Wu et al., US 20190115333 A1 (hereinafter referred to as Wu), in view of Bour et al. .
Claim 30 is a product-by-process claim. A product-by-process claim is a product claim. Applicant has merely chosen to define the claimed product by the process by which it was made. It has been well established that process limitations do not impart patentability to an old/obvious product. Process limitations are significant only to the extent that they distinguish the claimed product over the prior art product. Even though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process. In re Thorpe, 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir.1985). In this case, the claimed “a mesa comprising an epitaxial structure, the mesa comprising a top surface comprising an area of 10 micrometers squared or less; a dielectric on the top surface; and a hole in the dielectric centered on the top surface, wherein sidewalls of the mesa are free of dangling bonds and defects, the mesa is tapered, and the sidewalls include a ridge” need not be formed by the process of “a location and a first area of the hole are defined by and aligned to a position and area of a patterned hardmask layer, prior to removal of the patterned hardmask layer to leave the hole exposing a surface of the epitaxial structure in the mesa.”. Once the Examiner provides a rationale tending to show that the claimed product appears to be the same or similar to that of the prior art, although produced by a different process, the burden shifts to applicant to come forward with evidence establishing an unobvious difference between the claimed product and the prior art product. In re Marosi, 710 F.2d 798, 802, 218 USPQ 289, 292 (Fed. Cir.1983).
Tanaka teaches
A microLED (“semiconductor light-emitting element 10” para. 0048 FIG. 1A and 2), comprising:
a mesa (“GaN-based semiconductor laminate 40” forms a mesa structure over the “light guide 30” and “monocrystal silicon substrate 20” as seen in FIG. 2, para.0048, 0050, and 0053) comprising an epitaxial structure (“GaN-based semiconductor laminate 40” is comprised of “N-type semiconductor layer 41”, “activation layer 42”, and “P-type semiconductor layer 43” that are epitaxially grown, para. 0050 FIG. 2), the mesa comprising a top surface (top surface of “P-type semiconductor layer 43”);
a dielectric (“insulating layer 61” para. 0051 FIG. 2) on the top surface; and
a hole in the dielectric centered on the top surface (“The insulating layer covers the uppermost layer of the GaN-based semiconductor laminate 40 other than a predetermined center region”, the predetermined region being the “mouth 61a”, para. 0051, as seen in FIG. 2),
the mesa is tapered (“semiconductor laminate 40” is shown as having slanted sidewalls),
the sidewalls include a ridge (the corner between the sidewalls and the top surface of “semiconductor laminate 40” can be considered a ridge).
However, Tanaka fails to teach the mesa comprising a top surface comprising an area of 10 micrometers squared or less, wherein sidewalls of the mesa are free of dangling bonds and defects.
Nevertheless, Wu teaches
the top surface comprising an area of 10 micrometers squared or less (“the maximum width of the vertical type micro LEDs may be 1 μm-100 μm” para. 0033 FIG. 1B).
Tanaka and Wu teach light emitting devices. Wu teaches micro LEDs comprising an “epitaxial structure 122” (para. 0031) with a maximum width as low as 1μm or use in a micro LED display device. The examiner understands that by making light-emitting diodes smaller they can be more densely packed in a given surface area to offer greater image resolution. One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that micro light emitting diodes allow for higher resolution displays than larger LEDs in a same surface area.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the light emitting device taught in Tanaka with the maximum width taught in Wu. By making the LED a micro light emitting diode, a display of higher resolution is obtained.
However, Tanaka, modified by Wu fails to teach wherein sidewalls of the mesa are free of dangling bonds and defects.
Nevertheless, Bour teaches a “sidewall passivation layer 170” formed over a “mesa structure 120” made of GaN that forms a “LED 150” (para. 0070 and 0116-0117 FIG. 17A- 17F). In LEDs, efficiency degradation may occur due to non-radiative recombination at the LED sidewalls when the sidewalls have unsatisfied bonds, chemical contamination, and structural damage (para. 0051). Passivation of the sidewall surface of the LED mesas reduces the amount of non-radiative recombination near the exterior or side surfaces of the active layer, such that efficiency of the LED device increased (para. 0052). One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that passivation of the sidewalls of the “semiconductor laminate 40” in Tanaka with the “sidewalls passivation layer 170” can prevent non-radiative recombination around the sidewalls and improve device efficiency.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the micro light emitting device taught between Tanaka and Wu with the passivated mesa sidewall from Bour. Passivated sidewalls improve the emission efficiency of the device.
Allowable Subject Matter
Claim 34 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
The prior art Tanaka teaches an electrode in contact with the top surface of the mesa and is described as being reflective so that more light is emitted towards the light guide (para. 0070). To change the electrode to a transparent material such as indium tin oxide or to add a contact that is indium tin oxide would reduce the emission efficiency through the light guide. Therefore, claim 34 is considered to contain allowable subject matter in view of Tanaka.
Prior art not cited but relevant to applicant’s disclosure
Kim et al. US 20190165207 A1: a microLED stack with an opening in a conductive layer over the microLED stack.
Yang et al. US 20170309678 A1: a microLED having an insulating layer on top with an opening.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIC MULERO FLORES whose telephone number is (571)270-0070. The examiner can normally be reached Mon-Fri 8am-5pm (typically).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio Maldonado can be reached on (571)272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/ERIC MANUEL MULERO FLORES/Examiner, Art Unit 2898
/JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898