Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
Claim(s) 1-2 and 10-11 are rejected under 35 U.S.C. 103 as being unpatentable over Yun1 (PGPub No. 20180026666) in further view of Li (US Patent No. 8384507).
Regarding claim 1, Yun1 teaches a manufacturing method of a substrate integrated with passive devices, comprising: providing a transparent dielectric layer, wherein the transparent dielectric layer comprises a first outer surface and a second outer surface which are opposite to each other along a thickness direction of the transparent dielectric layer (Fig. 1 points to a glass substrate 102 (transparent dielectric layer).); and the transparent dielectric layer has first connection vias which penetrate through the transparent dielectric layer along the thickness direction of the transparent dielectric layer (Fig. 5 and [0050-51] point to a method of forming a substrate 500 which includes defining a plurality of holes (first connection vias) in a glass substrate at step 502, with said glass substrate corresponding to glass substrate 102 (transparent dielectric layer).); integrating the passive devices on the transparent dielectric layer, wherein forming the passive devices comprises at least forming an inductor (Figs. 4-5 and [0053] point to forming a passive device which may include one or more 3D inductors, such as the 3D inductor 302, on the glass substrate 102 (transparent dielectric layer).); the inductor comprises first sub-structures on the first outer surface of the transparent dielectric layer and second sub-structures on the second outer surface of the transparent dielectric layer, and first connection electrodes in the first connection vias, respectively, to sequentially connect the first sub-structures and the second sub-structures together (Id. points to forming a passive device (inductor) via a plating process 506, resulting in a trace 310 (first sub-structures) on a first side of the glass substrate 102 (first outer surface), a trace 308 (second sub-structures) on a second side of said substrate (second outer surface), and TGVs 304 (first connection electrodes).); wherein the forming the inductor comprises: forming a first metal film layer on the first outer surface and/or the second outer surface of the transparent dielectric layer, and forming the first connection electrodes in the first connection vias through an electroplating process (Id. points to forming a passive device (inductor) via a plating process 506, such as copper plating (electroplating), resulting in trace 310 (first sub-structures), trace 308 (second sub-structures), and TGVs 304 (first connection electrodes).); the first connection electrodes filling the first connection vias (Fig. 5 points to steps 502 and 506, which comprise defining a plurality of holes (first connection vias) in a glass substrate, and using a second subset of said plurality of holes to form a passive device including the TGVs 304 (first connection electrodes).); and forming a pattern comprising the first sub-structures on the first outer surface of the transparent dielectric layer through a patterning process, and forming a pattern comprising the second sub-structures on the second outer surface of the transparent dielectric layer through a patterning process ([0053] points to forming a passive device, such as 3D inductor 302 and by extension trace 310 (first sub-structures) and trace 308 (second sub-structures), using a patterning process.).
Yun1 fails to teach wherein the transparent dielectric layer is a glass substrate, the first sub-structures are directly on the first outer surface of the glass substrate, and the second sub-structures are directly on the second outer surface of the glass substrate.
Li teaches wherein the transparent dielectric layer is a glass substrate, the first sub-structures are directly on the first outer surface of the glass substrate, and the second sub-structures are directly on the second outer surface of the glass substrate (Fig. 1 and Col. 4, lines 37-40 point to a substrate 102 (glass substrate), backside traces 118 (first sub-structures), and frontside traces 116 (second sub-structures).). Thus, it would have been obvious to a person of ordinary skill in the art (POSITA) prior to the filing date of the claimed invention to combine the teachings of Yun1 and Li, such that the transparent dielectric layer comprises a glass substrate and both the first and second sub-structures are directly connected to the respective outer surfaces of said layer/substrate in order to create a high-resistance substrate that can withstand the continuous conductive path formed by the backside and frontside traces, said traces being directly connected to the substrate in order to minimize the signal path(s) between traces and improve communication.
Regarding claim 2, Yun1 teaches wherein the forming the inductor comprises: forming the first metal film layer on the second outer surface of the transparent dielectric layer ([0043] points to forming a trace 310 as part of forming a 3D inductor 302, with said trace 310 also being called a planar metallic region (first metal film layer).), forming a first metal material in the first connection vias through a patterning process, and forming the first connection electrodes in the first connection vias through an electroplating process (Fig. 5 and [0053] point to using a patterning process and a plating process to form a passive device. Fig. 4 and [0047] further point to an example of said process, where the hole 412 (first connection vias) located in glass substrate 102 (transparent dielectric layer) is filled with a copper material (first metal material) to form a TGV 434 (first connection electrodes) of the 3D inductor 432.).
Regarding claim 10, Yun1 teaches wherein the transparent dielectric layer comprises a glass substrate (Fig. 1 and [0020] point to a glass substrate 102 (transparent dielectric layer).).
Regarding claim 11, Yun1 teaches a substrate integrated with passive devices, comprising a transparent dielectric layer and the passive devices integrated on the transparent dielectric layer (Claim 1 points to an apparatus comprising a passive on glass (POG) device integrated within a glass substrate (transparent dielectric layer).); wherein the transparent dielectric layer comprises a first outer surface and a second outer surface which are opposite to each other along a thickness direction of the transparent dielectric layer (Fig. 1 points to a glass substrate 102.); and the transparent dielectric layer has first connection vias which penetrate through the transparent dielectric layer along the thickness direction of the transparent dielectric layer (Fig. 5 and [0051] point to step 502 of a method for forming a substrate 500, which includes defining a plurality of holes (first connection vias) in a glass substrate (transparent dielectric layer).); and the passive devices comprise at least an inductor (Figs. 4-5 and [0053] point to forming a passive device which may include one or more 3D inductors, such as the 3D inductor 302, on the glass substrate 102 (transparent dielectric layer).); the inductor comprises first sub-structures on the first outer surface of the transparent dielectric layer and second sub-structures on the second outer surface of the transparent dielectric layer, and first connection electrodes in the first connection vias, respectively, to sequentially connect the first sub-structures and the second sub-structures together (([0053] points to forming a passive device, such as 3D inductor 302 which includes trace 310 (first sub-structures), trace 308 (second sub-structures), and TGVs 304 & 306 (first connection electrodes) which are formed by filling in holes (first connection vias) through a plating process, such as how TGV 434 is formed in hole 412.).
Yun1 fails to teach wherein the transparent dielectric layer is a glass substrate, the first sub-structures are directly on the first outer surface of the glass substrate, and the second sub-structures are directly on the second outer surface of the glass substrate.
Li teaches wherein the transparent dielectric layer is a glass substrate, the first sub-structures are directly on the first outer surface of the glass substrate, and the second sub-structures are directly on the second outer surface of the glass substrate (Fig. 1 and Col. 4, lines 37-40 point to a substrate 102 (glass substrate), backside traces 118 (first sub-structures), and frontside traces 116 (second sub-structures).). Thus, it would have been obvious to a person of ordinary skill in the art (POSITA) prior to the filing date of the claimed invention to combine the teachings of Yun1 and Li, such that the transparent dielectric layer comprises a glass substrate and both the first and second sub-structures are directly connected to the respective outer surfaces of said layer/substrate in order to create a high-resistance substrate that can withstand the continuous conductive path formed by the backside and frontside traces, said traces being directly connected to the substrate in order to minimize the signal path(s) between traces and improve communication.
Regarding claim 13, Yun1 teaches wherein the transparent dielectric layer comprises a glass substrate (Fig. 1 and [0020] point to a glass substrate 102 (transparent dielectric layer).).
Claim(s) 3-7 are rejected under 35 U.S.C. 103 as being unpatentable over Yun1 in further view of Chen (PGPub No. 20210118827).
Regarding claim 3, Chen teaches wherein prior to forming the first metal film layer on the second outer surface of the transparent dielectric layer, the manufacturing method further comprises: forming an auxiliary metal film layer on the second outer surface of the transparent dielectric layer to increase an adhesive force between the first metal film layer and the second outer surface of the transparent dielectric layer ([0025] and [0032] point to an inter-dielectric layer 120 (transparent dielectric layer) comprising an inductor pattern 160 (first metal film layer) which may include copper and an underlying inductor pattern 140 (auxiliary metal film layer) which may include titanium, nickel, or alloys thereof.). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Yun1 and Chen, such that an additional layer of nickel and/or titanium is formed between the transparent dielectric layer and first metal film layer in order to reduce mechanical stress and improve thermal cycling reliability by providing a suitable mounting point for the first metal film layer.
Regarding claim 4, Chen teaches wherein the providing the transparent dielectric layer comprises: providing a substrate, and coating a first adhesive layer on the substrate; and attaching the first outer surface of the transparent dielectric layer to the first adhesive layer (Fig. 1A points to an inter-dielectric layer 120 (transparent dielectric layer) formed on a semiconductor substrate 110a. [0021] and [0025] further point to the inter-dielectric layer 120 comprising multiple stacked dielectric layers comprising epoxy resin, acrylic resin, phenol resin (first adhesive layer), other suitable dielectric materials (transparent dielectric layer), or combinations thereof.). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Yun1 and Chen, such that a stack is formed comprising a substrate, a first adhesive layer made of dielectric material such as epoxy resin, and a transparent dielectric layer attached to said adhesive layer, in order to create a stable structure that would allow for further processing of the transparent dielectric layer while minimizing any incidental damage.
Regarding claim 5, Chen teaches wherein a material of the first adhesive layer comprises a temperature-controlled adhesive (Fig. 1A, [0021], and [0025] point to an inter-dielectric layer 120 comprising multiple stacked dielectric layers comprising epoxy resin, acrylic resin, phenol resin (first adhesive layer), combinations thereof, or other suitable dielectric materials. It is considered an obvious that any adhesive has an inherent property of being temperature-controlled.). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Yun1 and Chen, such that the adhesive layer used to bond the substrate to the transparent dielectric layer can be heated and/or cooled as needed in order to ensure proper mounting which will enable further processing of the transparent dielectric layer and minimize any incidental damage.
Regarding claim 6, Yun1 teaches forming the first connection electrodes in the first connection vias through an electroplating process (Figs. 4-5 and [0053] point to forming a passive device via a plating process 506, such as copper plating (electroplating), which includes filling a plurality of holes (first connection vias) to form TGVs 304 (first connection electrodes).)
Yun1 fails to teach wherein the forming the inductor comprises: providing a substrate, and coating a first adhesive layer on the substrate; forming a first metal film layer on the first adhesive layer; forming a second adhesive layer on a side of the first metal film layer distal to the first adhesive layer, patterning the second adhesive layer to remove portions of the second adhesive layer corresponding to positions of the first connection vias in the transparent dielectric layer to be attached to the second adhesive layer; and attaching the first outer surface of the transparent dielectric layer to the second adhesive layer.
Chen teaches wherein the forming the inductor comprises: providing a substrate, and coating a first adhesive layer on the substrate (Fig. 1A, [0021], and [0025] point to a semiconductor substrate 110a and a stack of multiple dielectric layers 120 which may comprise suitable dielectric material(s) such as epoxy resin (first adhesive layer).); forming a first metal film layer on the first adhesive layer (Fig. 1A and [0023] point to trench portion 144 (first metal film layer) of inductor pattern 140, which is formed within the stack of multiple dielectric layers 120.); forming a second adhesive layer on a side of the first metal film layer distal to the first adhesive layer (Fig. 1A, [0021], and [0025] point to the inter-dielectric layer 120 comprising a stack of multiple dielectric layers which may comprise suitable dielectric material(s) such as epoxy resin (second adhesive layer).), patterning the second adhesive layer to remove portions of the second adhesive layer corresponding to positions of the first connection vias in the transparent dielectric layer to be attached to the second adhesive layer (Fig. 1A and [0023] point to an inductor pattern 140 comprising a trench portion 144 (first metal film layer) directly connected to a via portion 146 (first connection vias). It is considered obvious the one of ordinary skill in the art would selectively pattern the portion/layer of the inter-dielectric layer/stack 120 located on the trench portion 144 (second adhesive layer) in order to directly connect said trench portion 144 to the via portion 146 as shown while still utilizing the adhesive properties of the original layer.), and attaching the first outer surface of the transparent dielectric layer to the second adhesive layer ([0025] points to the inter-dielectric layer 120 including polyimide, epoxy resin (second adhesive layer), acrylic resin, phenol resin, benzocyclobutene (BCB), polybenzoxazole (PBO), combinations thereof, or other suitable dielectric materials (transparent dielectric layer).). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Yun1 and Chen, such that multiple adhesive layers are selectively applied both under and above the first metal film layer of the inductor in order to properly isolate the first metal film layer from interference and/or damage and provide greater physical stability to the transparent dielectric layer as a whole before applying further processes to completely form the inductor.
Regarding claim 7, Chen teaches wherein prior to forming the first metal film layer on the first adhesive layer, the manufacturing method comprises: forming an auxiliary metal film layer on the first adhesive layer to increase an adhesive force between the first metal film layer and the first adhesive layer ([0025] points to inductor pattern 140 including copper (first metal film layer), titanium, nickel (auxiliary metal film layer), aluminum, tungsten, and/or alloys thereof.). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Yun1 and Chen, such that the inductor is formed using copper in combination with nickel and/or a titanium alloy in order to utilize the conductive properties of copper while making up for its poor adhesive properties.
Claim(s) 8-9, 12, and 14-20 are rejected under 35 U.S.C. 103 as being unpatentable over Yun1 et al. in further view of Yun2 (PGPub No. 20200091094).
Regarding claim 8, Yun2 teaches wherein the passive devices further comprise a capacitor (Fig. 2 and [0032] point to a triplexer largely composed of passive components including inductors and capacitors arranged on a glass substrate.), and the manufacturing method further comprises: forming a first plate of the capacitor while forming the second sub-structures of the inductor (Figs. 4-5 and [0041-42] point to a MIM capacitor 313 comprising a first metal layer M1/501 (first plate) located on a surface of the glass substrate 315 and parallel to a portion(s) of inductor 304 (second sub-structures).); forming a first interlayer dielectric layer on a side, which is distal to the transparent dielectric layer, of a layer where the second sub-structures of the inductor and the first plate of the capacitor are located (Fig. 5 and [0042] point to an insulating layer 503 (first interlayer dielectric) comprising a silicon nitride compound and located on the first metal layer M1/501 (first plate).); and forming a second plate of the capacitor on a side of the first interlayer dielectric layer distal to the transparent dielectric layer (Id. points to a second metal layer M2/502 (second plate) located on the insulating layer 503 (first interlayer dielectric).). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Yun1 et al. and Yun2, such that a capacitor is additionally formed on the substrate alongside a portion of the inductor in order to form precise filters that can be easily co-optimized for frequency tuning.
Regarding claim 9, Yun2 teaches wherein the inductor comprises a first lead terminal connected to a first connection pad and a second lead terminal connected to a second end of the first plate of the capacitor (Figs. 4-5 point to metal layer M4 (first lead terminal) connecting 3D inductor 304 and metal layer M3 (first connection pad) and solder balls 311 (second lead terminal) connecting said inductor to the first metal layer M1/501 (first plate) of capacitor 313.); the second plate of the capacitor is connected to a second connection pad (Fig. 5 points to second metal layer M2/502 (second plate) connected to metal layer UM (second connection pad).); the manufacturing method further comprises: forming a second interlayer dielectric layer on a side, which is distal to the first interlayer dielectric layer, of a layer where the second plate of the capacitor and the second connection pad are located (Fig. 5 and [0042] point to die 309 (second interlayer dielectric layer).); forming a second connection via and a third connection via which penetrate through the second interlayer dielectric layer (Id. points to via V3 (second connection via) and via VP (third connection via) formed in the die 309 (second interlayer dielectric).); and forming the first connection pad and the second connection pad (Fig. 5 points to metal layers M3 (first connection pad) and UM (second connection pad).); wherein the first connection pad is connected to the first lead terminal through the second connection via (Id. points to metal layer M3 (first connection pad) connected to metal layer M4 through via V3 (second connection via).); and the second connection pad is connected to the second plate of the capacitor through the third connection via (Id. points to metal layer M2/502 (second plate of the capacitor) connected to metal layer UM (second connection pad) through via VP (third connection via).). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Yun1 et al. and Yun2, such that a second interlayer dielectric layer is selectively formed in order to provide electrical isolation to the inductor and capacitor while still allowing the formation of lead terminals on the inductor to allow some level of electrical connectivity.
Regarding claim 12, Yun2 teaches wherein the passive devices further comprise a capacitor (Fig. 2 and [0032] point to a triplexer largely composed of passive components including inductors and capacitors arranged on a glass substrate.); the capacitor comprises a first plate which is in the same layer as the second sub-structures of the inductor (Figs. 4-5 and [0041-42] point to a MIM capacitor 313 comprising a first metal layer M1/501 (first plate) located on a surface of the glass substrate 315 and parallel to a portion(s) of inductor 304 (second sub-structures).); the substrate further comprises a first interlayer dielectric layer on a side, which is distal to the transparent dielectric layer, of the first plate of the capacitor (Fig. 5 and [0042] point to an insulating layer 503 (first interlayer dielectric) comprising a silicon nitride compound and located on the first metal layer M1/501 (first plate).); and the capacitor comprises a second plate on a side, which is distal to the first plate of the capacitor, of the first interlayer dielectric layer (Id. points to a second metal layer M2/502 (second plate) located on the insulating layer 503 (first interlayer dielectric).). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Yun1 et al. and Yun2, such that a capacitor is additionally formed on the substrate alongside a portion of the inductor in order to form precise filters that can be easily co-optimized for frequency tuning.
Regarding claim 14, Yun2 teaches wherein the passive devices further comprise a capacitor (Fig. 2 and [0032] point to a triplexer largely composed of passive components including inductors and capacitors arranged on a glass substrate.), and the manufacturing method further comprises: forming a first plate of the capacitor while forming the second sub-structures of the inductor (Figs. 4-5 and [0041-42] point to a MIM capacitor 313 comprising a first metal layer M1/501 (first plate) located on a surface of the glass substrate 315 and parallel to a portion(s) of inductor 304 (second sub-structures).); forming a first interlayer dielectric layer on a side, which is distal to the transparent dielectric layer, of a layer where the second sub-structures of the inductor and the first plate of the capacitor are located (Fig. 5 and [0042] point to an insulating layer 503 (first interlayer dielectric) comprising a silicon nitride compound and located on the first metal layer M1/501 (first plate).); and forming a second plate of the capacitor on a side of the first interlayer dielectric layer distal to the transparent dielectric layer (Id. points to a second metal layer M2/502 (second plate) located on the insulating layer 503 (first interlayer dielectric).). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Yun1 et al. and Yun2, such that a capacitor is additionally formed on the substrate alongside a portion of the inductor in order to form precise filters that can be easily co-optimized for frequency tuning.
Regarding claim 15, Yun2 teaches wherein the passive devices further comprise a capacitor (Fig. 2 and [0032] point to a triplexer largely composed of passive components including inductors and capacitors arranged on a glass substrate.), and the manufacturing method further comprises: forming a first plate of the capacitor while forming the second sub-structures of the inductor (Figs. 4-5 and [0041-42] point to a MIM capacitor 313 comprising a first metal layer M1/501 (first plate) located on a surface of the glass substrate 315 and parallel to a portion(s) of inductor 304 (second sub-structures).); forming a first interlayer dielectric layer on a side, which is distal to the transparent dielectric layer, of a layer where the second sub-structures of the inductor and the first plate of the capacitor are located (Fig. 5 and [0042] point to an insulating layer 503 (first interlayer dielectric) comprising a silicon nitride compound and located on the first metal layer M1/501 (first plate).); and forming a second plate of the capacitor on a side of the first interlayer dielectric layer distal to the transparent dielectric layer (Id. points to a second metal layer M2/502 (second plate) located on the insulating layer 503 (first interlayer dielectric).). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Yun1 et al. and Yun2, such that a capacitor is additionally formed on the substrate alongside a portion of the inductor in order to form precise filters that can be easily co-optimized for frequency tuning.
Regarding claim 16, Yun2 teaches wherein the passive devices further comprise a capacitor (Fig. 2 and [0032] point to a triplexer largely composed of passive components including inductors and capacitors arranged on a glass substrate.), and the manufacturing method further comprises: forming a first plate of the capacitor while forming the second sub-structures of the inductor (Figs. 4-5 and [0041-42] point to a MIM capacitor 313 comprising a first metal layer M1/501 (first plate) located on a surface of the glass substrate 315 and parallel to a portion(s) of inductor 304 (second sub-structures).); forming a first interlayer dielectric layer on a side, which is distal to the transparent dielectric layer, of a layer where the second sub-structures of the inductor and the first plate of the capacitor are located (Fig. 5 and [0042] point to an insulating layer 503 (first interlayer dielectric) comprising a silicon nitride compound and located on the first metal layer M1/501 (first plate).); and forming a second plate of the capacitor on a side of the first interlayer dielectric layer distal to the transparent dielectric layer (Id. points to a second metal layer M2/502 (second plate) located on the insulating layer 503 (first interlayer dielectric).). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Yun1 et al. and Yun2, such that a capacitor is additionally formed on the substrate alongside a portion of the inductor in order to form precise filters that can be easily co-optimized for frequency tuning.
Regarding claim 17, Yun2 teaches wherein the passive devices further comprise a capacitor (Fig. 2 and [0032] point to a triplexer largely composed of passive components including inductors and capacitors arranged on a glass substrate.), and the manufacturing method further comprises: forming a first plate of the capacitor while forming the second sub-structures of the inductor (Figs. 4-5 and [0041-42] point to a MIM capacitor 313 comprising a first metal layer M1/501 (first plate) located on a surface of the glass substrate 315 and parallel to a portion(s) of inductor 304 (second sub-structures).); forming a first interlayer dielectric layer on a side, which is distal to the transparent dielectric layer, of a layer where the second sub-structures of the inductor and the first plate of the capacitor are located (Fig. 5 and [0042] point to an insulating layer 503 (first interlayer dielectric) comprising a silicon nitride compound and located on the first metal layer M1/501 (first plate).); and forming a second plate of the capacitor on a side of the first interlayer dielectric layer distal to the transparent dielectric layer (Id. points to a second metal layer M2/502 (second plate) located on the insulating layer 503 (first interlayer dielectric).). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Yun1 et al. and Yun2, such that a capacitor is additionally formed on the substrate alongside a portion of the inductor in order to form precise filters that can be easily co-optimized for frequency tuning.
Regarding claim 18, Yun2 teaches wherein the passive devices further comprise a capacitor (Fig. 2 and [0032] point to a triplexer largely composed of passive components including inductors and capacitors arranged on a glass substrate.), and the manufacturing method further comprises: forming a first plate of the capacitor while forming the second sub-structures of the inductor (Figs. 4-5 and [0041-42] point to a MIM capacitor 313 comprising a first metal layer M1/501 (first plate) located on a surface of the glass substrate 315 and parallel to a portion(s) of inductor 304 (second sub-structures).); forming a first interlayer dielectric layer on a side, which is distal to the transparent dielectric layer, of a layer where the second sub-structures of the inductor and the first plate of the capacitor are located (Fig. 5 and [0042] point to an insulating layer 503 (first interlayer dielectric) comprising a silicon nitride compound and located on the first metal layer M1/501 (first plate).); and forming a second plate of the capacitor on a side of the first interlayer dielectric layer distal to the transparent dielectric layer (Id. points to a second metal layer M2/502 (second plate) located on the insulating layer 503 (first interlayer dielectric).). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Yun1 et al. and Yun2, such that a capacitor is additionally formed on the substrate alongside a portion of the inductor in order to form precise filters that can be easily co-optimized for frequency tuning.
Regarding claim 19, Yun2 teaches wherein the passive devices further comprise a capacitor (Fig. 2 and [0032] point to a triplexer largely composed of passive components including inductors and capacitors arranged on a glass substrate.), and the manufacturing method further comprises: forming a first plate of the capacitor while forming the second sub-structures of the inductor (Figs. 4-5 and [0041-42] point to a MIM capacitor 313 comprising a first metal layer M1/501 (first plate) located on a surface of the glass substrate 315 and parallel to a portion(s) of inductor 304 (second sub-structures).); forming a first interlayer dielectric layer on a side, which is distal to the transparent dielectric layer, of a layer where the second sub-structures of the inductor and the first plate of the capacitor are located (Fig. 5 and [0042] point to an insulating layer 503 (first interlayer dielectric layer) comprising a silicon nitride compound and located on the first metal layer M1/501 (first plate).); and forming a second plate of the capacitor on a side of the first interlayer dielectric layer distal to the transparent dielectric layer (Id. points to a second metal layer M2/502 (second plate) located on the insulating layer 503 (first interlayer dielectric layer).). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Yun1 et al. and Yun2, such that a capacitor is additionally formed on the substrate alongside a portion of the inductor in order to form precise filters that can be easily co-optimized for frequency tuning.
Regarding claim 20, Yun2 teaches a second interlayer dielectric layer covering the second sub-structures and the capacitor (Figs. 4-5 and [0040-41] point to a MIM capacitor 313 and a portion of a 3D inductor 304 (second sub-structures) located within a die 309 (second interlayer dielectric layer), which may be made of glass, high resistivity silicon, or other insulating materials); a second connection via and a third connection via which penetrate through the second interlayer dielectric layer (Fig. 5 and [0042] point to via V3 (second connection via) and via VP (third connection via) formed in the die 309 (second interlayer dielectric).); and a first connection pad and a second connection pad on the second interlayer dielectric layer and at positions of the second connection via and the third connection via, respectively (Id. points to metal layers M3 (first connection pad) and UM (second connection pad).); wherein the inductor further comprises a first lead terminal connected to the first connection pad and a second lead terminal connected to the second connection pad (Figs. 4-5 point to metal layer M4 (first lead terminal) connecting 3D inductor 304 and metal layer M3 (first connection pad) and solder balls 311 (second lead terminal) connecting said inductor to the metal layer UM (second connection pad).). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Yun1 et al. and Yun2, such that a second interlayer dielectric layer is selectively formed in order to provide electrical isolation to the inductor and capacitor while still allowing the formation of lead terminals on the inductor to allow some level of electrical connectivity.
Response to Arguments
Applicant’s arguments, see Remarks, filed 03/05/2026, with respect to the rejection(s) of claim(s) 1 and 11 under 35 U.S.C. §103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Li (US Patent No. 8384507).
Conclusion
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/PATRICK CULLEN/ Assistant Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899
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