DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on March 16, 2026 has been entered.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3, 5, 7-9, 11-13, 15-18 and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2013/0137244 A1 to Kramer et al. (hereinafter “Kramer” – previously cited reference).
Regarding claim 1, Kramer discloses a method of producing a wafer layer (5) (method of making thin film crystalline semiconductor substrate; paragraph [0012]), comprising the following method steps:
A providing a carrier element (1) (reusable doped crystalline semiconductor template; Figs. 1A-1C; paragraphs [0048]-[0049], [0110]);
B porosifying the carrier element (1) on at least one surface for creation of a separation layer (4) (front side of template 120 has porosity region and layer 114, 116 of porous silicon release layer formed therein such as by wet anodic etch in an HF-based chemistry; Fig. 2A; paragraphs [0051], [0110]-[0111]; claim 1);
C epitaxially applying a wafer layer (5) to the separation layer (4) of the carrier element (1) (epitaxially depositing a thin film semiconductor substrate conformally to release layer of template; abstract; paragraphs [0107], [0111]; claim 1); and
D detaching the wafer layer (5) from the carrier element (1) (substrate is released from template; abstract; paragraphs [0060], [0107]; claim 1), wherein method steps B to D are repeated at least once with the carrier element (1) (template is reusable for creation of a plurality of substrates by same process; abstract; paragraphs [0110]-[0111]; claim 1); and
method step A comprises the further method steps of A1 providing a carrier substrate (2) (template comprises a wafer body 100; Fig. 1C; paragraph [0048]); and A2 epitaxially applying a seed layer (3) to at least one surface and at least one lateral face of the carrier substrate (2) for production of the carrier element (1) (epitaxial seed layer 140 is applied at least to front and side of template 138 as shown in Fig. 4; paragraphs [0054], [0057]), with the seed layer being applied with a greater layer width, in a direction outward from the at least one lateral face of the carrier substrate (2), than a layer thickness applied to the at least one surface (epitaxial seed layer 140 has larger horizontal width dimension in a direction parallel to that outward from a lateral face of wafer body 100 than vertical thickness dimension applied to front of template 138; Fig. 4; paragraphs [0054], [0057]).
Regarding claim 2, Kramer discloses the method as claimed in claim 1, wherein the seed layer (3) is applied so as to ensheath the one surface and all of the lateral faces of the carrier substrate (2) (porous silicon layer has seed layer disposed upon top surface thereof, where layers wrap around the template; Fig. 6A; paragraphs [0054], [0066]).
Regarding claim 3, Kramer discloses the method as claimed in claim 1, wherein the carrier substrate (2) and the seed layer (3) have been formed or are formed from silicon, germanium or gallium arsenide (template and seed layer may be formed from quasi-monocrystalline silicon or gallium arsenide; paragraph [0013]; claims 12-13).
Regarding claim 5, Kramer discloses the method as claimed in claim 1, wherein the seed layer (3) is applied on the at least one surface of the carrier substrate (2) with a layer thickness (8) in a range from 10 µm to 250 µm (template may have a thickness of 100 microns which means porous Si layer having seed layer may proportionally have a thickness of at least 10 microns as shown in Fig. 18; paragraph [0111]).
Regarding claim 7, Kramer discloses the method as claimed in claim 1, further comprising: applying, forming, or disposing a contact layer (6) on the surface of the carrier substrate (2) remote from the seed layer (3) before, during or after the application of the seed layer (3) (contact material formation may be performed on the surface of the template in the form of higher porosity layer 126 separate from low porosity layer 124 having seed layer; Figs. 2A-2B; paragraphs [0051]-[0052], [0108]).
Regarding claim 8, Kramer discloses the method as claimed in claim 7, wherein the contact layer (6) has been formed or is formed from polycrystalline semiconductor (material deposition for all layers may be quasi-monocrystalline silicon; paragraphs [0084], [0095], [0121]).
Regarding claim 9, Kramer discloses the method as claimed in claim 7, wherein the contact layer (6) has a thickness in a range from 0.1 to 20 µm (higher porosity layer 126 has a thickness of 2.53 microns as shown in Fig. 2A; paragraph [0052]).
Regarding claim 11, Kramer discloses the method as claimed in claim 1, wherein the seed layer (3) is applied to the carrier substrate (2) with an inhomogeneous layer thickness (8), and the inhomogeneous layer thickness (8) increases or decreases at least toward one of two opposite ones of the lateral faces of the carrier substrate (2) (seed layer in QMS layer 140 shows asymmetric thickness profile towards one later face of template 138 as shown in Fig. 4; paragraphs [0054], [0057]).
Regarding claim 12, Kramer discloses a carrier element (1) for production of a wafer layer (5) (reusable doped crystalline semiconductor template for making thin film crystalline semiconductor substrate; Figs. 1A-1C; paragraphs [0012], [0048]-[0049], [0110]), the carrier element comprising:
a carrier substrate (2) (template comprises a wafer body 100; Fig. 1C; paragraph [0048]);
an epitaxial seed layer (3) applied to at least one surface and at least one lateral face of the carrier substrate (2) (epitaxial seed layer 140 is applied at least to front and side of template 138 as shown in Fig. 4; paragraphs [0054], [0057]), the seed layer being applied with a greater layer width, in a direction outward from the at least one lateral face of the carrier substrate (2), than a layer thickness applied to the at least one surface (epitaxial seed layer 140 has larger horizontal width dimension in a direction parallel to that outward from a lateral face of wafer body 100 than vertical thickness dimension applied to front of template 138; Fig. 4; paragraphs [0054], [0057]); and
a separation layer (4) formed by porosifying of the at least one surface of the epitaxial seed layer (3) (front side of template 120 having seed layer has porosity region and layer 114, 116 porous silicon release layer formed therein such as by wet anodic etch in an HF-based chemistry; Fig. 2A; paragraphs [0051], [0110]-[0111]; claim 1).
Regarding claim 13, Kramer discloses the carrier element (1) as claimed in claim 12, wherein the seed layer (3) on the at least one surface of the carrier substrate (2) has a layer thickness (8) in a range from 10 µm to 250 µm (template may have a thickness of 100 microns which means porous Si layer having seed layer may proportionally have a thickness of at least 10 microns as shown in Fig. 18; paragraph [0111]).
Regarding claim 15, Kramer discloses the carrier element (1) as claimed in claim 12, further comprising a contact layer (6) disposed on the surface of the carrier substrate (2) remote from the seed layer (3) (contact material formation may be performed on the surface of the template in the form of higher porosity layer 126; Fig. 2A; paragraphs [0051]-[0052], [0108]).
Regarding claim 16, Kramer discloses an intermediate product (10) comprising the carrier element (1) as claimed in claim 12 and an epitaxial wafer layer (5) disposed on the separation layer (4) (product created when thin film crystalline semiconductor substrate is formed on porous release layer of template as shown in Figs. 2A-2B, 4 and 18; paragraphs [0052], [0057]).
Regarding claim 17, Kramer discloses the method as claimed in claim 1, wherein the seed layer (3) is applied on the at least one lateral face of the carrier substrate (2) with a layer width (9) in a range from 10 µm to 600 µm (template may have a thickness of 100 microns which means porous Si layer having seed layer may proportionally have a thickness of at least 10 microns as shown in Fig. 18; paragraph [0111]).
Regarding claim 18, as best understood, Kramer discloses the method as claimed in claim 7, wherein material the contact layer (6) is formed or disposed so as to protrude beyond the carrier substrate (2) (higher porosity layer 126 extends beyond body of template 122 as shown in Fig. 2B; paragraph [0052]).
Regarding claim 20, Kramer discloses the carrier element (1) as claimed in claim 12, wherein the seed layer (3) on the at least one lateral face of the carrier substrate (2) has a layer width (9) in the range from 10 µm to 600 µm (template may have a thickness of 100 microns which means porous Si layer having seed layer may proportionally have a thickness of at least 10 microns as shown in Fig. 18; paragraph [0111]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 4 and 6 are rejected under 35 U.S.C. 103 as being unpatentable over Kramer in further view of US 2018/0277629 A1 to Lee et al. (hereinafter “Lee” – previously cited reference).
Regarding claim 4, Kramer discloses the method as claimed in claim 1, wherein the carrier substrate (2) is n-doped or p-doped (template may be doped; paragraphs [0068], [0079], [0084]).
Kramer fails to disclose a dopant concentration is in a region of less than 5 x 10^19 cm-3.
However, Lee discloses a dopant concentration is in a region of less than 5 x 10^19 cm-3 (substrate doped at concentration of 1x10^18/cm^3; paragraph [0057]).
Kramer and Lee are both considered to be analogous to the claimed invention because they are in the same field of semiconductor devices. Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Kramer to incorporate the teaching of Lee in order to potentially provide improved carrier mobility, reduced lattice strain and defects, and enhanced control of electrical properties.
Regarding claim 6, Kramer discloses the method as claimed in claim 1, wherein the seed layer (3) is doped during the application with a dopant concentration (release layer having seed layer may be doped; paragraphs [0079], [0084], [0091]-[0092], [0099], [0116]).
Kramer fails to disclose a dopant concentration in a range from 1 x 10^16 cm-3 to 5 x 10^19 cm-3.
However, Lee discloses a dopant concentration in a range from 1 x 1016cm-3 to 5 x 1019 cm-3 (seed layer 104 doped with concentration of about 10^19/cm^3; paragraph [0047]).
Kramer and Lee are both considered to be analogous to the claimed invention because they are in the same field of semiconductor devices. Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Kramer to incorporate the teaching of Lee in order to potentially provide improved carrier mobility, reduced lattice strain and defects, and enhanced control of electrical properties.
Claims 10 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Kramer in further view of US 2013/0095597 A1 to Park et al. (hereinafter “Park” – previously cited reference).
Regarding claim 10, Kramer discloses the method as claimed in claim 7.
Kramer fails to disclose further comprising forming the contact layer (6) by diffusion of a diffusion layer on the surface of the carrier substrate (2) remote from the seed layer (3) into the carrier substrate (2).
However, Park discloses further comprising forming the contact layer (6) by diffusion of a diffusion layer on the surface of the carrier substrate (2) remote from the seed layer (3) into the carrier substrate (2) (contact layers 100c formed into surface of substrate 100 by diffusion of dopants in a dopant material layer coated over substrate 100; Fig. 2; paragraphs [0024], [0039]).
Kramer and Park are both considered to be analogous to the claimed invention because they are in the same field of semiconductor devices. Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Kramer to incorporate the teaching of Park in order to potentially provide simplified process integration, consistency across multiple cycles, and improved impurity management.
Regarding claim 19, Kramer in view of Lee discloses the method of claim 10.
Kramer fails to disclose wherein the diffusion layer is formed by a holding element for holding the carrier substrate (2) during method step A2, or is applied prior to method step A2 on the surface of the carrier substrate (2) remote from the seed layer (3).
However, Park discloses wherein the diffusion layer is formed by a holding element for holding the carrier substrate (2) during method step A2, or is applied prior to method step A2 on the surface of the carrier substrate (2) remote from the seed layer (3) (dopants of dopant material layer are coated over substrate 100 before any other materials layers are formed thereover as shown in Fig. 2; paragraphs [0024], [0039]).
Kramer and Park are both considered to be analogous to the claimed invention because they are in the same field of semiconductor devices. Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Kramer to incorporate the teaching of Park in order to potentially provide simplified process integration, consistency across multiple cycles, and improved impurity management.
Response to Arguments
Applicant's arguments filed March 3, 2026 have been fully considered. Applicant presents substantive amendments to claims 1 and 12 with corresponding arguments. Applicant asserts that their specification paragraph [0122] provides a specific definition to the terms “seed layer width” and “seed layer thickness” and therefore amended claims 1 and 12 are not disclosed by Kramer. However, Examiner notes that the terms “seed layer width” and “seed layer thickness” are readily understood in plain English lexicon and, therefore, the broadest reasonable interpretation of these phrases extends beyond any specific narrower definition provided by Applicant. Examiner is constrained by broadest reasonable interpretation and therefore must maintain that Kramer discloses amended claims 1 and 12 by epitaxial seed layer 140 having a larger horizontal width dimension in a direction parallel to a direction that is outward from a lateral face of the wafer body 100 than the vertical thickness dimension as applied to the front side of template 138. Further, Applicant asserts that seed layer 140 is not disposed on the same sides of template 138 as that which is claimed in claims 1 and 12. However, the terms ‘front’ and ‘side’ as used in the claim analysis by Examiner are arbitrary labels and therefore render Applicant’s point moot. If Applicant would like these labels not to be considered arbitrary, then the terms ‘lateral face’ and ‘at least one surface’ should be claimed in more detail and in an orientational relationship to other fixed structures so that Examiner is further constrained in the construction of claims 1 and 12. Moreover, even if Applicant’s assertion in this regard is accepted, there still exists an interpretation of Kramer where the rotated template 138 still discloses a part of seed layer 140 having a larger horizontal width dimension in a direction parallel to a direction that is outward from a lateral face of the wafer body 100 than the vertical thickness dimension of another part of seed layer 140 as applied to the front side of template 138. Amended claims 1 and 12 are simply too broad to be read in the manner suggested by Applicant in the Response. Finally, Applicant claims that QMS epitaxial seed layer 140 is not a seed layer, but paragraph [0054] of Kramer states that “the top layer of the porous semiconductor is reflowed to re-form a quasi-monocrystalline growth surface and ultrathin seed layer of semiconductor (QMS).” Therefore, Examiner maintains that epitaxial seed layer 140 is a seed layer.
Conclusion
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/IAN DEGRASSE/Examiner, Art Unit 2818
/JEFF W NATALINI/Supervisory Patent Examiner, Art Unit 2818