DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The amendments filed 12/18/2025 are noted.
Claims 1 and 3-20 remain pending.
Claims 1 and 3-20 have been fully considered in examination.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1, 3, 5, 13-17 and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over US 20200235178 A1 (of record), hereafter “Shin”, in view of US 20200395570 A1 (of record), hereafter “Nakamura”.
Regarding claim 1, Shin teaches an array substrate (Figs. 5 & 6), comprising:
a base substrate 100 [0110];
a pixel defining layer 300 [0110], disposed on a side of the base substrate 100 (see Fig. 6), wherein the pixel defining layer 300 is provided with opening regions (OP1-OP3 [0121]), peripheral regions PPA [0078] (Figs. 5 and 6) surrounding the opening regions (OP1-OP3; Figs. 5 & 6) and other regions (see region corresponding to the spacer 400 [0078] in Fig. 5) except (“except” interpreted by the examiner to mean “different from”) the opening regions (OP1-OP3) and the peripheral regions PPA;
a first electrode layer 600 [0099], disposed on a side (upper side; Fig. 6), facing away from the base substrate 100 (see Fig. 6), of the pixel defining layer 300, wherein a roughness of a surface (upper surface of Fig. 6), facing away from the base substrate 100 (Fig. 6), of the first electrode layer 600 in the peripheral regions PPA (see PPA areas in Fig. 6) is greater than a roughness of a surface (upper surface), facing away from the base substrate 100, of the first electrode layer 600 in the other regions (see 400 in Fig. 5 and then in Fig. 6);
wherein the peripheral regions PPA comprise slope regions (see annotated Fig. 6 of Shin below, hereafter, “Fig. 6.1”) connected with the opening regions (OP1-OP3; Fig. 6.1) and transition regions (Fig. 6.1) connected with the slope regions (Fig. 6.1);
a roughness of a surface, facing away from the base substrate 100, of the first electrode layer 600 in the transition regions (Fig. 6.1; comprising uneven structures 310 and 320 [0108]) is greater than the roughness of the surface, facing away from the base substrate 100, of the first electrode layer 600 in the other regions (see 400 in Fig. 5 and then in Fig. 6 where top layer is a planar surface);
wherein for one opening region (see OP3 in Fig. 6.1), the slope region (Fig. 6.1) is arranged between the opening region OP3 and the transition region (Fig. 6.1 and Fig. 5), and the transition region (see Fig. 5) is arranged between (“between” with respect to the DR1 direction; see Fig. 5) the slope region (Fig. 5; corresponding to the edge of PXA3 nearest 400) and the other region 400.
Shin does not teach wherein a roughness of a surface, facing away from the base substrate 100, of the first electrode layer 600 in the slope regions (Fig. 6.1) is greater than the roughness of the surface, facing away from the base substrate 100, of the first electrode layer 600 in the other regions (see Fig. 6 where the slope regions are planar), and
color filter parts, disposed on a side (upper surface), facing away from the base substrate 100, of the first electrode layer 600, wherein the color filter parts arranged in one-to-one correspondence to the opening regions (OP1-OP3), orthographic projections of the color filter parts on the base substrate 100 cover orthographic projections of the opening regions (OP1-OP3) on the base substrate 100, and the color filter parts are configured to filter incident light from outside to the color filter parts,
wherein the array substrate further comprises a black matrix; the black matrix comprises a plurality of openings corresponding one-to-one to the opening regions OP1-3; and
an orthographic projection of a boundary of the opening (black matrix opening) on the base substrate 100 is located in an orthographic projection of transition region (Fig. 6.1) on the base substrate 100.
Shin does not teach wherein a roughness of a surface, facing away from the base substrate 100, of the first electrode layer 600 in the slope regions (Fig. 6.1) is greater than the roughness of the surface, facing away from the base substrate 100, of the first electrode layer 600 in the other regions (taught by Shin; see Fig. 6 of Shin where the slope regions are planar/not roughened, rather than having the uneven structures 310 and 320 present in the transition region).
Nakamura teaches an array substrate (Figs. 1 and 16) wherein a roughness of a surface, facing away from a base substrate 101 [0101], of an EL layer 107 [0140] (see Fig. 16; disposed below a first electrode layer 108; see Fig. 3), in slope regions (see wavy/rough portion of 107 in Fig. 16) is greater than a roughness of the surface, facing away from the base substrate 101, of the EL layer 600 in other regions (see regions outside of staircase region where 107 is smooth).
While Nakamura does not explicitly teach that the first electrode layer 108 (see Fig. 3) inherits the shape of the EL layer 107 in Fig. 16, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to make the first electrode layer to be rough in the slope region in the normal course of experimentation while trying to optimize the amount of optical scattering that occurs, as taught by Nakamura [0134] (MPEP 2144.05 (II)).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the teachings of Nakamura in the device of Shin, such that the roughness in the slope region (see Fig. 6.1 below of Shin) is greater than the roughness in the other regions (see 400 of Shin, which has a planar/not rough surface).
One would be motivated to include the teachings of Nakamura in order to increase optical scattering effect [0134], as taught by Nakamura.
Nakamura further teaches color filter parts 112 [0102], disposed on a side (upper surface), facing away from the base substrate 101, of the first electrode layer 108, wherein the color filter parts arranged in one-to-one correspondence to the opening regions (corresponding to openings in the banks 106 [0102]), orthographic projections of the color filter parts 112 on the base substrate 101 cover orthographic projections of the opening regions (openings in banks of 106) on the base substrate 101, and the color filter parts 112 are configured to filter incident light from outside to the color filter parts 112 (Fig. 3),
wherein the array substrate (Fig. 3) further comprising a black matrix 111 [0102]; the black matrix 111 comprises a plurality of openings (see CF 112) corresponding one-to-one to opening regions (the opening regions defined between banks of insulating layer 106); and
an orthographic projection of a boundary of the opening (black matrix opening; corresponding to boundary between 111 and 112; Fig. 3) on a base substrate 101 [0101] is located in an orthographic projection of a transition region (top of banked region of 106) on the base substrate 101.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the color filter parts of Nakamura in the device of Shin in order to produce a color image [0073] as motivated by Nakamura.
Further, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the black matrix and black matrix opening of Nakamura in the device of Shin in order to separate adjacent light emitting elements into distinct units and prevent light bleed. Additionally, one would be motivated in the ordinary course of experimentation and optimization to make the black matrix opening so as to be located over the transition region of Shin while finding a sufficient opening size to separate adjacent light emitting elements while maintaining the improved viewing angle by scattering, as taught by Nakamura [0109] (see MPEP 2144.05(II)).
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Regarding claim 3, Shin in view of Nakamura teaches the array substrate of claim 1, and Shin further teaches wherein a roughness of a surface (upper surface), facing away from the base substrate 100, of the pixel defining layer 300 in peripheral regions PPA (see also 310 [0070] in Fig. 3) is greater than a roughness of a surface (upper surface), facing away from the base substrate 100, of the pixel defining layer 300 in the other regions (corresponding to 400; where 300 under 400 is shown not to comprise the roughened area 310); and
the roughness of the first electrode layer 600 in the peripheral regions PPA is approximately equal to the roughness of the surface of the pixel defining layer 300 in the peripheral regions PPA (see Fig. 6).
Regarding claim 5, Shin in view of Nakamura teaches the array substrate of claim 3, and Shin further teaches wherein for one of the opening regions OP1 (Fig. 6; corresponding to first pixel area PXA1 [0108]), in a peripheral region PPA surrounding an opening region OP1 (see PXA1 in Fig. 5), the pixel defining layer 300 is provided with recessed parts (311 [0074] (see also Fig. 3) and 321 [0110]; Fig. 5) surrounding the opening region OP1 (see PXA1 in Fig. 5), wherein the recessed parts (311) are arranged in sequence in a direction (along DR3 towards PXA3; see annotated Fig. 5 below, hereafter “Fig. 5.1”) in which the opening region OP1 points towards the peripheral region PPA, and a distance between the recessed parts 311 away from the opening region (Fig. 5.1) and the base substrate is equal to a distance between the recessed parts (Fig. 5.1) close to the opening region OP1 and the base substrate 100 (where all recessed parts are equidistant to 100).
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Regarding claim 13, Shin in view of Nakamura teaches the array substrate of claim 1, and Nakamura further teaches
wherein the black matrix 111 surrounds at least one of the color filter parts 112 (Fig. 3); and
for one of the opening regions (corresponding to opening in banks of 106), an orthographic projection of a peripheral region (see transistors of circuit layer 102 [0101]) on the base substrate 101 has an overlapping region with an orthographic projection of the black matrix 111 (see annotated Fig. 3 of Nakamura below) on the base substrate 101, and
the orthographic projection of the peripheral region (circuits of 102) on the base substrate 101 has an overlapping region with an orthographic projection of a color filter part 112 on the base substrate 101 (annotated Fig. 3 below).
It would have been obvious to one of ordinary skill in the art to further include the teachings of Nakamura for the same reasons discussed above regarding claim 1.
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Regarding claim 14, Shin in view of Nakamura teaches the array substrate of claim 1, and Shin further teaches wherein a distance between a boundary of each of peripheral regions (where the boundary is the midway point of the peripheral region between two openings OP/pixel areas) away from the opening regions (corresponding to PXA1-2) and a boundary of the opening region PXA1 ranges from 6 μm to 10 μm (where D12 is about 19.2 μm [0082] such that the midpoint is 9.6 μm).
Regarding claim 15, Shin in view of Nakamura teaches the array substrate of claim 1, and Shin teaches the array substrate further comprising:
a second electrode layer (201-203 [0113]; Fig. 6), arranged between the base substrate 100 and the pixel defining layer 300 (Fig. 6), wherein an orthographic projection of the second electrode layer (201-203) on the base substrate 100 covers the orthographic projections of the opening regions (OP1-3) on the base substrate 100 (Fig. 6); and
a light emitting layer (531-533 [0090]), arranged between the first electrode layer 600 and the second electrode layer (201-203), wherein an orthographic projection of the light emitting layer (531-533) on the base substrate 100 covers the orthographic projections of the opening regions (OP1-3) on the base substrate 100 ([0090]; Fig. 6).
Regarding claim 16, Shin in view of Nakamura teaches a manufacturing method (Figs. 7-11) of the array substrate according to claim 1, comprising:
providing a base substrate 100; forming a pixel defining layer 300 on the base substrate 100;
performing composition [0118] (Fig. 8) on the pixel defining layer 300, so that a plurality of opening regions (OP1-3), peripheral regions PPA surrounding opening regions (OP1-3) and other regions (corresponding to 400) except (“except” interpreted by the examiner to mean “different from”) the opening regions (OP1-3) and the peripheral regions PPA are formed in the pixel defining layer 300; forming a first electrode layer 600 (see Fig. 6) on the pixel defining layer 300, wherein a roughness of a surface (see 310; Fig. 6), facing away from the base substrate 100 (upper surface), of the first electrode layer 600 in the peripheral regions PPA (Fig. 6) is greater than a roughness of a surface, facing away from the base substrate 100 (upper surface), of the first electrode layer 600 in the other regions 400; and Nakamura, as discussed above regarding claim 1, motivates forming color filter parts 112 on the first electrode layer 600 of Shin.
One would have been motivated to use the teachings of Nakamura in the method taught by Shin for the same reasons discussed above regarding claim 1.
Regarding claim 17, Shin in view of Nakamura teaches the manufacturing method of the array substrate of claim 16, and Shin further teaches wherein the performing composition (Fig. 8) on the pixel defining layer 300, comprises: forming photoresist 301 [0119] on the pixel defining layer 300 (the excess material of 301 not corresponding to 300); and
performing exposure development [0119] on the pixel defining layer 300 by using a preset mask 700 [0119], to form the opening regions (OP1-3; see Fig. 9) and patterns (310 [0121]; Fig. 9) of the pixel defining layer 300 in the peripheral regions PPA, wherein the preset mask 700 (Fig. 8) comprises patterns (710, 720 and 730 [0121]) of the opening regions 710 and patterns of recessed parts 730.
Regarding claim 19, Shin teaches a display panel (OLED display; see title), comprising the array substrate according to claim 1 (Figs. 5 & 6).
Regarding claim 20, Shin teaches a display apparatus (MP3 player [0126]), comprising the display panel (OLED display) of claim 19 [0126].
Claims 4 and 6-12 are rejected under 35 U.S.C. 103 as being unpatentable over Shin in view of Nakamura as applied to claim 3 above, and further in view of US 20150069361 A1 (of record), hereafter “Sato”.
Regarding claim 4, Shin in view of Nakamura teaches the array substrate according to claim 3, and Shin further teaches wherein for one of the opening regions OP1 (Fig. 6; corresponding to first pixel area PXA1 [0108]), in a peripheral region PPA surrounding an opening region OP1 (see PXA1 in Fig. 5), the pixel defining layer 300 is provided with recessed parts (311 [0074] (see also Fig. 3) and 321 [0110]; Fig. 5) surrounding the opening region OP1 (see PXA1 in Fig. 5), wherein the recessed parts (311) are arranged in sequence in a direction (along DR3 towards PXA3; see Fig. 5.1 above) in which the opening region OP1 points towards the peripheral region PPA.
Shin does not teach wherein a distance between the recessed parts 311 away from the opening region (Fig. 5.1) and the base substrate is larger than a distance between the recessed parts (Fig. 5.1) close to the opening region OP1 and the base substrate 100 (where all recessed parts are equidistant to 100), but rather, teaches the distance are equal.
Sato teaches an array substrate (Figs. 14 and 15) wherein a distance between recessed parts 136 [0084] (Fig. 14) away from (see recessed part 136 as labeled in Fig. 14) an opening region (the opening region corresponding to the region comprising pixel electrode 118 [0083]) and a base substrate 110 [0084] is larger than a distance between the recessed parts (Fig. 5.1) close to (see recessed part 136 nearest 118 in Fig. 14) the opening region and the base substrate 110.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the teachings of Sato in the array substrate of Shin as a mere matter of design choice with respect to the shape of the pixel defining layer (see MPEP 2144.04 (IV)(B)) given Sato teaches the distance can be larger (as discussed above ; Fig. 14) or, similarly to the structure taught by Shin, the distance may be equal (Fig. 15).
Regarding claim 6, Shin in view of Nakamura and Sato teaches the array substrate according to claim 4, and Shin further teaches wherein a shape (square shape) defined by orthographic projections of the recessed parts (321 and 311) on the base substrate 100 is same as a shape (shape) of an orthographic projection of the opening region OP (Fig. 6; corresponding to PXA1 of Fig. 5) Fig. 5 on the base substrate 100 (see Fig. 5).
Regarding claim 7, Shin in view of Nakamura and Sato teaches the array substrate according to claim 6, and Shin further teaches wherein a central point of the shape (square) defined by the orthographic projections of the recessed parts (321 and 311) on the base substrate 100 roughly overlaps with a central point of the orthographic projection of the opening region PXA1 on the base substrate 100 (see Fig. 5).
Regarding claim 8, Shin in view of Nakamura and Sato teaches the array substrate according to claim 4, and Shin further teaches wherein a width of the recessed parts (311 and 321; see Fig. 3), in the direction in which the opening region OP1-3 points towards the peripheral region PPA, ranges from 0.5 μm to 2.5 μm (where the pitch, WD [0075], is 2.9 μm [0075], the width is half that, i.e., 1.45 μm); and
a distance between adjacent recessed parts (with respect to the nearest inside portions of the recesses) ranges from 0.5 μm to 2.5 μm (about 1.45 μm; Fig. 3).
Regarding claim 9, Shin in view of Nakamura and Sato teaches the array substrate according to claim 4, and Shin further teaches wherein a distance between an upper surface of each of the recessed parts 311 (corresponding to 312 [0075] and a lower surface of each of the recessed parts 311 ranges from 0.2 μm to 1.0 μm (see [0075]).
Regarding claim 10, Shin in view of Nakamura and Sato teaches the array substrate according to claim 4, and Shin further teaches wherein each of the recessed parts (311 and 321) comprises a plurality of sub recessed parts (311 and 321 individually; Fig. 5), and adjacent sub recessed parts (extending along a single linear direction) are arranged at interval by a preset distance (see Fig. 3; where the present distance corresponds to about half of WD [0075]); and
a shape (square; see Fig. 5) defined by orthographic projections of the sub recessed parts (311 and 321) on the base substrate 100 is same as a shape (square) of an orthographic projection of the opening region PXA1 on the base substrate 100 (see Fig. 5).
Regarding claim 11, Shin in view of Nakamura and Sato teaches the array substrate according to claim 10, and Shin further teaches wherein the shape (square) defined by the orthographic projections of the sub recessed parts (311 and 321) on the base substrate 100 is a circle, a rectangle or an oval (square; Fig. 5).
Regarding claim 12, Shin in view of Nakamura and Sato teaches the array substrate according to claim 10, and Shin further teaches wherein the preset distance ranges from 0.5 μm to 2.5 μm (where the preset distance is about half of WD, 1.45 μm [0075]; Fig. 3).
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Shin in view of Nakamura as applied to claim 16 above, and further in view of US 20160300889 A1 (of record), hereafter “Kim”.
Regarding claim 18, Shin in view of Nakamura teaches the manufacturing method of the array substrate of claim 16, and Nakamura further teaches wherein after forming the first electrode layer 108 (Fig. 3) on a pixel defining layer (bank layer 106) and forming the color filter parts 112 on the first electrode layer 108, the manufacturing method further comprises:
forming a black matrix (the black matrix) 111 on the first electrode layer 108.
Nakamura does not explicitly teach specifically forming the black matrix 111 before forming the color filter parts 112.
Kim teaches a method of manufacturing an array substrate (see title and Fig. 1) wherein a black matrix is formed prior to forming a color filter parts layer (see Fig. 7 and further Figs. 8A-8G).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Kim into the method of Shin and Nakamura given Nakamura does not teach a specific order in manufacturing steps, and Kim teaches forming the black matrix first is well suited to effectively forming a similar structure in an array substrate (MPEP 2144.07), and further, to use the black matrix as a dam for confining the color filter parts [0116], as taught by Kim.
Response to Arguments
Applicant’s arguments, filed 12/18/2025, with respect to the previously relied upon Lee reference for a color filter and black matrix (see pgs. 7-8) have been considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of a new interpretation of the prior art of record (Nakamura), not previously challenged, as necessitated by amendment (see rejection above).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Bruce Smith III whose telephone number is (571)272-5570. The examiner can normally be reached Monday - Friday; 8 am - 5 pm.
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/BRUCE R. SMITH/Examiner, Art Unit 2892
/ERIC W JONES/Primary Examiner, Art Unit 2892