Detailed Action
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This office action is final and is in response to claims filed on 07/16/2025 via amendment. Claims 1-6 are pending for examination. Claims 1-2 and 4 are currently amended. Claims 3 and 5-6 are as previously presented.
Response to Arguments
Objections to the Specification
Applicant has amended the title, therefore the previous objection to the title has been withdrawn.
Applicant has amended the abstract, therefore the previous objection to the abstract is withdrawn.
Objections to the Claims
Applicant has amended the claims at issue. Therefore, the previous objections of the claims have been withdrawn.
Rejections under 35 U.S.C. 103
Applicant’s arguments with respect to claims 1-6 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Information Disclosure Statement
The Information Disclosure Statement (IDS) submitted on 12/31/2025 is in compliance with the provisions of 37 CFR 1.97, 1.98, and MPEP § 609. It has been placed in the application file, and the information referred to therein has been considered as to the merits.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3 are rejected under 35 U.S.C. 103 as being unpatentable over Manipatruni et al. (US 20200303344 A1) hereinafter Manipatruni in view of Lee et al. (US 20180196713 A1) hereinafter Lee further in view of Chou et al. (US 20200210759 A1) hereinafter Chou further in view of Yamazaki et al. (US 20110128777 A1) hereinafter Yamazaki.
With regards to claim 1, Manipatruni teaches An information processing device comprising: a storage device; (Manipatruni [0010]: FIG. 3D illustrates a cross-section of a package comprising a computational block, which includes a compute die between memory dies in a horizontal stack along the plane of the package)
and an arithmetic device, (Manipatruni [0010]: FIG. 3D illustrates a cross-section of a package comprising a computational block, which includes a compute die between memory dies in a horizontal stack along the plane of the package)
wherein the storage device comprises a first layer and a second layer, (Manipatruni [0010]: FIG. 3D illustrates a cross-section of a package comprising a computational block, which includes a compute die between memory dies in a horizontal stack along the plane of the package)
wherein the first layer is provided with a circuit, (Manipatruni [0010]: FIG. 3D illustrates a cross-section of a package comprising a computational block, which includes a compute die between memory dies in a horizontal stack along the plane of the package; Manipatruni Fig. 3D: shows the first layer being the compute die)
wherein the second layer is provided with a memory cell portion, (Manipatruni [0010]: FIG. 3D illustrates a cross-section of a package comprising a computational block, which includes a compute die between memory dies in a horizontal stack along the plane of the package; Manipatruni Fig. 3D: shows the second layer being FE-RAM die)
[wherein the circuit is configured to switch and perform reading or writing of first data or second data from or to] the memory cell portion, (Manipatruni [0010]: FIG. 3D illustrates a cross-section of a package comprising a computational block, which includes a compute die between memory dies in a horizontal stack along the plane of the package; Manipatruni Fig. 3D: shows the second layer being FE-RAM die)
wherein the memory cell portion is configured to retain the first data or the second data written, without power supply, (Manipatruni [0071]: RAM dies 343/345 may comprise FE-SRAM, FE-DRAM, SRAM, MRAM, Re-RAM or a combination of them; Manipatruni [0048]: n some embodiments, SRAM 104 is ferroelectric based SRAM. For example, a six transistor (6T) SRAM bit-cells having ferroelectric transistors are used to implement a non-volatile Fe-SRAM)
wherein at least part of the second layer is stacked above the first layer, (Manipatruni [0010]: FIG. 3D illustrates a cross-section of a package comprising a computational block, which includes a compute die between memory dies in a horizontal stack along the plane of the package; Manipatruni Fig. 3D: shows the second layer stacked on top of the first layer)
wherein the arithmetic device is provided in the first layer, (Manipatruni [0010]: FIG. 3D illustrates a cross-section of a package comprising a computational block, which includes a compute die between memory dies in a horizontal stack along the plane of the package; Manipatruni Fig. 3D: shows the first layer being the compute die)
wherein the arithmetic device comprises a central processing device and [an accelerator,] (Manipatruni [0060]: in some embodiments, compute die 304 is an application specific circuit (ASIC), a processor, or some combination of such functions).
Manipatruni fails to teach wherein the circuit is configured to switch and perform reading or writing of first data or second data and wherein the circuit comprises a data writing circuit and a data reading circuit.
However, Lee teaches wherein the circuit is configured to switch and perform reading or writing of first data or second data (Lee [0038]-[0040]: The first write repeater 412 may output the input data DIN<1:K> as first write data WD1...The second write repeater 414 may output the input data DIN<1:K> as second write data WD2; Lee [0045]-[0048]: The first read repeater 422 may output the internal data ID<1:K> as first read data RD1...The second read repeater 425 may output the corrected data CD<1:K> as second read data RD2)
wherein the circuit comprises a data writing circuit and a data reading circuit, (Lee [0038]-[0040]: The first write repeater 412 may output the input data DIN<1:K> as first write data WD1...The second write repeater 414 may output the input data DIN<1:K> as second write data WD2; Lee [0045]-[0048]: The first read repeater 422 may output the internal data ID<1:K> as first read data RD1...The second read repeater 425 may output the corrected data CD<1:K> as second read data RD2).
Therefore, it would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to combine the teachings of Manipatruni with the read and write circuits of Lee. One of ordinary skill in the art would be motivated to make this combination because it would allow for simultaneous reads and writes of the first and second data, speeding up calculations. Also, it would ensure the reliability of the data transmissions as taught by Lee (Lee [0003]).
Manipatruni in view of Lee fails to teach that the arithmetic circuit of Manipatruni in view of Lee comprises an accelerator. Manipatruni in view of Lee also fails to teach wherein the accelerator is configured to execute a product-sum operation for performing inference processing based on a neural network.
However, Chou teaches that the arithmetic circuit of Manipatruni in view of Lee comprises an accelerator (Chou [0028]: Based on these observations, embodiments of the invention provide an architecture of BNN accelerator that leverages input and kernel similarities to reduce the number of MAC operations at inference time)
wherein the accelerator is configured to execute a product-sum operation for performing inference processing based on a neural network (Chou [0028]: Based on these observations, embodiments of the invention provide an architecture of BNN accelerator that leverages input and kernel similarities to reduce the number of MAC operations at inference time).
Therefore, it would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to combine the teachings of Manipatruni in view of Lee with the accelerator as taught by Chou. One of ordinary skill in the art would be motivated to make this combination because a BNN removes bitwidth redundancy in a classical CNN by using a single bit (−1/+1) for network parameters and intermediate representations. Such aspect greatly reduces the off-chip data transfer and storage overhead as taught by Chou (Chou [0005]).
Manipatruni in view of Lee further in view of Chou fails to teach wherein the data writing circuit is directly connected to the memory cell portion through a first wiring, and the data reading circuit is directly connected to the memory cell portion through a second wiring.
However, Yamazaki teaches wherein the data writing circuit is directly connected to the memory cell portion through a first wiring, (Yamazaki [0290]: the reading circuit 212 may be directly connected to the bit line BL)
and the data reading circuit is directly connected to the memory cell portion through a second wiring, (Yamazaki [0290]: the writing circuit 211 may be directly connected to the first signal line S1).
Therefore, it would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to combine the teachings of Manipatruni in view of Lee further in view of Chou with the read and write circuits being directly connected to the memory as taught by Yamazaki. One of ordinary skill in the art would be motivated to make this combination because it would increase the efficiency of the system as the signals would not have to travel through multiple components to get the read and write circuits. Also, a semiconductor device according to one embodiment of the present invention has no limitation on the number of write cycles, which is a problem of a conventional non-volatile memory, and thus has a significantly increased reliability as taught by Yamazaki (Yamazaki [0029]).
With regards to claim 2, Manipatruni in view of Lee further in view of Chou further in view of Yamazaki teaches all of the limitations of claim 1 above. Manipatruni fails to teach wherein the data writing circuit comprises a first writing circuit which is configured to write the first data and a second writing circuit which is configured to write the second data, and wherein the data reading circuit comprises a first reading circuit which is configured to read the first data and a second reading circuit which is configured to read the second data.
However, Lee teaches wherein the data writing circuit comprises a first writing circuit which is configured to write the first data (Lee [0038]: The first write repeater 412 may output the input data DIN<1:K> as first write data WD1)
and a second writing circuit which is configured to write the second data, (Lee [0040]: The second write repeater 414 may output the input data DIN<1:K> as second write data WD2)
and wherein the data reading circuit comprises a first reading circuit which is configured to read the first data (Lee [0045]: The first read repeater 422 may output the internal data ID<1:K> as first read data RD1)
and a second reading circuit which is configured to read the second data (Lee [0048]: The second read repeater 425 may output the corrected data CD<1:K> as second read data RD2).
Therefore, it would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to combine the teachings of Manipatruni in view of Lee further in view of Chou further in view of Yamazaki with the read and write circuits of Lee. One of ordinary skill in the art would be motivated to make this combination because it would allow for simultaneous reads and writes of the first and second data, speeding up calculations. Also, it would ensure the reliability of the data transmissions as taught by Lee (Lee [0003]).
With regards to claim 3, Manipatruni in view of Lee further in view of Chou further in view of Yamazaki teaches all of the limitations of claim 1 above. Manipatruni fails to teach wherein the first data is binary data, and wherein the second data is data having three or more values.
However, Chou teaches wherein the first data is binary data, (Chou [0007]: In addition, embodiments of the invention provide two BNN configurations...(ii) Input is quantized to fixed-point values and weights are binarized)
and wherein the second data is data having three or more values (Chou [0007]: In addition, embodiments of the invention provide two BNN configurations...(ii) Input is quantized to fixed-point values and weights are binarized).
Therefore, it would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to combine the teachings of Manipatruni in view of Lee further in view of Chou further in view of Yamazaki with the input types as taught by Chou. One of ordinary skill in the art would be motivated to make this combination because a BNN removes bitwidth redundancy in a classical CNN by using a single bit (−1/+1) for network parameters and intermediate representations. Such aspect greatly reduces the off-chip data transfer and storage overhead as taught by Chou (Chou [0005]).
Claims 4-5 are rejected under 35 U.S.C. 103 as being unpatentable over Manipatruni in view of further in view of Chou further in view of Yamazaki further in view of Ohmaru et al. (US 20120170355 A1) hereinafter Ohmaru.
With regards to claim 4, Manipatruni in view of Lee further in view of Chou further in view of Yamazaki teaches all of the limitations of claim 1 above. Manipatruni further teaches wherein the first layer [comprises a silicon-on-insulator (SOI) substrate,] (Manipatruni [0010]: FIG. 3D illustrates a cross-section of a package comprising a computational block, which includes a compute die between memory dies in a horizontal stack along the plane of the package; Manipatruni Fig. 3D: shows the first layer being the compute die)
wherein the circuit [comprises a first transistor on the SOI substrate,] (Manipatruni [0010]: FIG. 3D illustrates a cross-section of a package comprising a computational block, which includes a compute die between memory dies in a horizontal stack along the plane of the package; Manipatruni Fig. 3D: shows the first layer being the compute die)
wherein the memory cell portion comprises a second transistor, (Manipatruni [0048]: In some embodiments, SRAM 104 is ferroelectric based SRAM. For example, a six transistor (6T) SRAM bit-cells having ferroelectric transistors are used to implement a non-volatile Fe-SRAM)
and wherein the second transistor [comprises a metal oxide in a channel formation region] (Manipatruni [0048]: In some embodiments, SRAM 104 is ferroelectric based SRAM. For example, a six transistor (6T) SRAM bit-cells having ferroelectric transistors are used to implement a non-volatile Fe-SRAM).
Manipatruni fails to teach [wherein the first layer] comprises an SOI substrate, [wherein the circuit] comprises a first transistor on the SOI substrate, [and wherein the second transistor] comprises a metal oxide in a channel formation region.
However, Ohmaru teaches [wherein the first layer] comprises a silicon-on-insulator (SOI) substrate, (Ohmaru [0335]: The logic circuit 3004 includes a transistor 3001… Note that the transistor 3001 may be a transistor in which a channel formation region is formed in a semiconductor film such as a silicon film formed on an insulating surface or a silicon film in an SOI substrate)
[wherein the circuit] comprises a first transistor on the SOI substrate, (Ohmaru [0335]: The logic circuit 3004 includes a transistor 3001… Note that the transistor 3001 may be a transistor in which a channel formation region is formed in a semiconductor film such as a silicon film formed on an insulating surface or a silicon film in an SOI substrate)
[and wherein the second transistor] comprises a metal oxide in a channel formation region (Ohmaru [0087]-[0089]: The storage circuit 102 includes a capacitor 108, a transistor 109... The transistor 109 is a transistor in which a channel is formed in an oxide semiconductor layer).
Therefore, it would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to combine the teachings of Manipatruni in view of Lee further in view of Chou further in view of Yamazaki with the SOI substrate and transistors as taught by Ohmaru. One of ordinary skill in the art would be motivated to make this combination because it would decrease the power consumption for the system as an SOI substrate has a lower parasitic capacitance than other silicon substrates. Additionally, A known structure can be employed for the structure of the transistor 3001; thus, the description thereof is omitted here as taught by Ohmaru (Ohmaru [0335).
With regards to claim 5, Manipatruni in view of Lee further in view of Chou further in view of Yamazaki teaches all of the limitations of claim 1 above. Manipatruni further teaches wherein the first layer [comprises a single crystal silicon substrate,] (Manipatruni [0010]: FIG. 3D illustrates a cross-section of a package comprising a computational block, which includes a compute die between memory dies in a horizontal stack along the plane of the package; Manipatruni Fig. 3D: shows the first layer being the compute die)
wherein the circuit [comprises a first transistor on the single crystal silicon substrate,] (Manipatruni [0010]: FIG. 3D illustrates a cross-section of a package comprising a computational block, which includes a compute die between memory dies in a horizontal stack along the plane of the package; Manipatruni Fig. 3D: shows the first layer being the compute die)
wherein the memory cell portion comprises a second transistor, (Manipatruni [0048]: In some embodiments, SRAM 104 is ferroelectric based SRAM. For example, a six transistor (6T) SRAM bit-cells having ferroelectric transistors are used to implement a non-volatile Fe-SRAM)
and wherein the second transistor [comprises a metal oxide in a channel formation region] (Manipatruni [0048]: In some embodiments, SRAM 104 is ferroelectric based SRAM. For example, a six transistor (6T) SRAM bit-cells having ferroelectric transistors are used to implement a non-volatile Fe-SRAM).
Manipatruni fails to teach [wherein the first layer] comprises a single crystal silicon substrate, [wherein the circuit] comprises a first transistor on the single crystal silicon substrate, [and wherein the second transistor] comprises a metal oxide in a channel formation region.
However, Ohmaru teaches [wherein the first layer] comprises a single crystal silicon substrate, (Ohmaru [0150]: In this embodiment, an example in which the semiconductor film 702 is formed using single crystal silicon is given as a manufacturing method of the transistor)
[wherein the circuit] comprises a first transistor on the single crystal silicon substrate, (Ohmaru [0150]: In this embodiment, an example in which the semiconductor film 702 is formed using single crystal silicon is given as a manufacturing method of the transistor)
[and wherein the second transistor] comprises a metal oxide in a channel formation region (Ohmaru [0087]-[0089]: The storage circuit 102 includes a capacitor 108, a transistor 109... The transistor 109 is a transistor in which a channel is formed in an oxide semiconductor layer).
Therefore, it would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to combine the teachings of Manipatruni in view of Lee further in view of Chou further in view of Yamazaki with the single crystal silicon substrate and transistors as taught by Ohmaru. One of ordinary skill in the art would be motivated to make this combination because it would increase the accuracy of the system as a single crystal silicon substrate is free from impurities and grain boundaries which can impede electronic signals. Also, it is necessary that the material have at least heat resistance high enough to withstand heat treatment to be performed later as taught by Ohmaru (Ohmaru [0149]).
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Manipatruni in view of further in view of Chou further in view of Yamazaki further in view of Pakin et al. (Power usage of production supercomputers and production workloads) hereinafter Pakin.
With regards to claim 6, Manipatruni in view of Lee further in view of Chou further in view of Yamazaki teaches all of the limitations of claim 1 above. Manipatruni further teaches [A supercomputer comprising:] the information processing device according to claim 1; (Manipatruni [0010]: FIG. 3D illustrates a cross-section of a package comprising a computational block, which includes a compute die between memory dies in a horizontal stack along the plane of the package)
wherein the information processing device [is electrically connected to the plurality of switchboards] (Manipatruni [0010]: FIG. 3D illustrates a cross-section of a package comprising a computational block, which includes a compute die between memory dies in a horizontal stack along the plane of the package).
Manipatruni fails to teach A supercomputer comprising: [the information processing device according to claim 1;] and a plurality of switchboards, [wherein the information processing device] is electrically connected to the plurality of switchboards.
However, Pakin teaches A supercomputer comprising: [the information processing device according to claim 1;] (Pakin Page 274 Summary: large supercomputer)
and a plurality of switchboards, (Pakin Pages 275-276 Section 3.1: The substations transmit power through a rotary uninterruptible power supply to a number of switchboards each of which feeds multiple power distribution units (PDUs) on the machine-room floor. These convert the power into three-phase, 208 V or 480 V power for distribution to the compute racks)
[wherein the information processing device] is electrically connected to the plurality of switchboards (Pakin Pages 275-276 Section 3.1: The substations transmit power through a rotary uninterruptible power supply to a number of switchboards each of which feeds multiple power distribution units (PDUs) on the machine-room floor. These convert the power into three-phase, 208 V or 480 V power for distribution to the compute racks).
Therefore, it would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to combine the teachings of Manipatruni in view of Lee further in view of Chou further in view of Yamazaki with the supercomputer as taught by Pakin. One of ordinary skill in the art would be motivated to make this combination because it would increase the performance of the system as many information processing devices could be run at the same time.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Jakob O Gudas whose telephone number is (571)272-0695. The examiner can normally be reached Monday-Thursday: 7:30AM-5:00PM Friday: 7:30AM-4:00PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, James Trujillo can be reached at (571) 272-3677. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/J.O.G./Examiner, Art Unit 2151
/James Trujillo/Supervisory Patent Examiner, Art Unit 2151
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