Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 10 and 17 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
“Backplane components” lacks antecedent basis and it is unclear what exactly has a “higher profile” than “backplane components.” The introduction of “backplane components” introduces confusion because it is unclear if these “backplane components” are integral to “component layers,” or some other things not limited in the claim. The specification is of little help. “Backplane components” and “component layers” seem to refer to the same stack of functional layers common to TFTs. For purposes of examination, referencing Figs. 2A and 2B, the claim will be interpreted as a stack of functional layers 202-216, where a pad 212 is formed on the top layer 216 of functional layers, “top” being with respect to distance from the substrate 200.
Furthermore, a “backplane” is defined in [0016] as including conductive, dielectric or semiconductor layers, so “applying component layers comprising of multiple conductive layers and multiple dielectric or semiconductor layers on a backplane…” becomes further unclear. It is assumed “substrate” was intended in the limitation.
Regarding Claim 17, it is not clear what “a fully integrated system” is.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 10-14 and 16-18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by U.S. Pat. No. 6127199 to Inoue et al. (Inoue).
Regarding Claim 10, Inoue teaches starting at Fig. 31 at least, method to eliminate interference using a stacked structure, the method comprising:
applying component layers 1500/1100/1300/1400 comprising of multiple conductive layers and multiple dielectric or semiconductor layers on a backplane 3000; and
applying a pad 1790 on one or more of the component layers, wherein the one or more of the component layers on which the pad is applied has a profile higher, relative to the backplane, than a highest profile of any of backplane components of the component layers, relative to the backplane, and wherein the one or more of the component layers on which the pad is applied are part of one or more of active electrodes, devices or dummy layers (see Fig. 31, 1300a has a higher profile than the remaining layers below).
Regarding Claim 11, Inoue teaches the method of claim 10, wherein a conductive layer of one of the multiple conductive layers is patterned to form electrodes 1400a/b and gate electrode 1300a of a transistor.
Regarding Claim 12, Inoue teaches the method of claim 10, wherein one of a plurality of transistor electrodes is coupled with the pad (see Fig. 31).
Regarding Claim 13, Inoue teaches the method of claim 12, wherein one or more of the multiple dielectric or semiconductor layers form a channel of a transistor, a source region, and a drain region 22:28-36.
Regarding Claim 14, Inoue teaches the method of claim 13, wherein electrode layers create a connection to the source and the drain region (see Fig. 31).
Regarding Claim 16, Inoue teaches the method of claim 10, the method further comprising forming wherein the backplane components on top of a buffer layer deposited on top of a substrate.
Regarding Claim 17, Inoue teaches the method of claim 16, the method further comprising using the buffer layer as a delamination layer as well as separating a fully integrated system from the substrate (see Figs. 32-33).
Regarding Claim 18, Inoue teaches the method of claim 17, the method further comprising forming an additional layer 1000 on top of the buffer layer to create a substrate for the backplane after a delamination.
Claims 10 and 15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by U.S. Pat. No. 6503778 to Yamauchi et al. (Yamauchi).
Regarding Claims 10 and 15, Yamauchi teaches starting at Fig. 4D at least, method to eliminate interference using a stacked structure, the method comprising:
applying component layers 21/23/26/28/251-254 comprising of multiple conductive layers and multiple dielectric or semiconductor layers on a backplane 11; and
applying a pad 291/b/c on one or more of the component layers, wherein the one or more of the component layers on which the pad is applied has a profile higher, relative to the backplane, than a highest profile of any of backplane components of the component layers, relative to the backplane, and wherein the one or more of the component layers on which the pad is applied are part of one or more of active electrodes, devices or dummy layers (see Fig. 4D, 28 has a higher profile than the remaining layers below),
wherein the pad is connected to a microdevice 40 in Fig. 9B.
Applicants are highly encouraged to review all of the cited prior art in the attached form 892.
Conclusion
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/EVREN SEVEN/ Primary Examiner, Art Unit 2812