Detailed Action
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the transferring method of Claim 10, the multi-stack pad of Claim 19, the bonding material of Claim 20, the light reflector of Claim 21, the “another pad” of Claim 27, the devices listed in Claim 28 and the microdevice and pixel circuits of Claim 30 must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
Claims 21, 23 and 27 are rejected under 35 U.S.C. 112(a) as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor at the time the application was filed, had possession of the claimed invention.
Regarding Claim 21, “forming a light reflector to redirect light emitted by the microdevice” is not in the original application as filed; only that light can be reflected. The source is not mentioned.
Regarding Claim 23, the only embodiment showing the pad laterally offset as required by Claim 23 is Fig. 1, where the pad is not formed on backplane components as required by Claim 10 from which Claim 23 depends. The assembly of Claim 23 amounts to a new structure not previously disclosed on the record.
Regarding Claim 27, “the one or more component layers on which the pad is applied is not adjacent to another pad” is not found in the application as filed.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 10-14, 16-18, 20, 22, 24-26 and 28-30 are rejected under 35 U.S.C. 102(A)(1) as being anticipated by U.S. Pat. Pub. No. 20060273319 to Dairiki et al. (Dairiki).
Regarding Claim 10, Dairiki teaches a method of eliminating interference during transfer of a microdevice to a backplane using a stacked structure, comprising:
applying one or more component layers (layers forming TFTs 105/106/107, 104, 112) forming the backplane, comprising of multiple conductive layers and multiple dielectric or semiconductor layers, on a buffer layer 101 or a substrate 100, wherein the one or more component layers includes backplane components;
applying a pad 113 on the one or more component layers to form the stacked structure, wherein the one or more of the component layers on which the pad is applied has a profile higher, relative to the buffer layer or the substrate, than a highest profile of any of the backplane components of the one or more component layers, relative to the buffer layer or the substrate, wherein the one or more of the component layers on which the pad is applied are part of one or more of active electrodes, devices or dummy layers, and wherein the backplane components are laterally offset from the pad (see Fig. 1C);
transferring the microdevice to the pad such that there is no interference caused by the backplane components during the transferring of the microdevice to the pad, the pad, together with the one or more component layers on which the pad is applied, having a highest profile of the backplane, relative to the buffer layer or the substrate (see Fig. 5B).
Regarding Claim 11, Dairiki teaches the method of claim 10, wherein a conductive layer of one of the multiple conductive layers is patterned to form electrodes and gate electrode of a transistor (see Fig. 1C).
Regarding Claim 12, Dairiki teaches the method of claim 10, wherein one of a plurality of transistor electrodes is coupled with the pad (see Fig. 1C).
Regarding Claim 13, Dairiki teaches the method of claim 12, wherein one or more of the multiple dielectric or semiconductor layers form a channel of a transistor, a source region, and a drain region (see Fig. 1C).
Regarding Claim 14, Dairiki teaches the method of claim 13, wherein electrode layers create a connection to the source and the drain region (see Fig. 1C).
Regarding Claim 16, Dairiki teaches the method of claim 10, the method further comprising forming the backplane components on top of the buffer layer deposited on top of the substrate (see Fig. 1C).
Regarding Claim 17, Dairiki teaches the method of claim 16, the method further comprising using the buffer layer as a delamination layer to separate the component layers and the pad from the substrate (see Fig. 5A).
Regarding Claim 18, Dairiki teaches the method of claim 17, the method further comprising forming an additional layer 102 on top of the buffer layer to create a substrate for the backplane after a delamination.
Regarding Claim 20, Dairiki teaches the method of claim 10, wherein the pad comprises a bonding material 124 to hold the microdevice permanently.
Regarding Claim 22, Dairiki teaches the method of claim 10, wherein the backplane components include a transistor 105.
Regarding Claim 24, Dairiki teaches the method of claim 22, wherein the transistor is connected to the pad using a conductive layer that extends laterally from the transistor to beneath the pad (see Fig. 1C).
Regarding Claim 25, Dairiki teaches the method of claim 24, wherein the pad extends through a topmost layer of the one or more component layers to contact the conductive layer (see Fig. 1C).
Regarding Claim 26, Dairiki teaches the method of claim 10, wherein during the transferring of the microdevice to the pad, there are no layers on top of the backplane components (see Fig. 5A).
Regarding Claim 28, Dairiki teaches the method of claim 10, wherein the microdevice is a micro light emitting diode (LED), an organic LED, a sensor (antenna, [0130]), a solid state device, an integrated circuit, or a micro-electro- mechanical systems (MEMS) device.
Regarding Claim 29, Dairiki teaches the method of claim 10, wherein the transferring includes transferring the microdevice onto a top surface of the pad, the top surface of the pad being above every surface of the backplane components, relative to the buffer layer or the substrate (see Fig. 5A).
Regarding Claim 30, Dairiki teaches the method of claim 10, wherein the pad provides an electrical connection between the microdevice and pixel circuits underneath the pad (see Fig. 5A).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Dairiki in view of U.S. Pat. Pub. No. 20040178411 to Misaki et al. (Misaki).
Regarding Claim 19, Dairiki teaches the method of claim 10, but does not explicitly teach that the pad comprises a stack of multiple layers.
However, in analogous art, Misaki shows a multi layer pad 16. It would have been obvious to the person of ordinary skill in the art before the time of filing to include the teaching of Misaki to provide a reflecting layer, as taught by Misaki [0058].
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to EVREN SEVEN whose telephone number is (571)270-5666. The examiner can normally be reached Mon-Fri 8:00- 5:00 Pacific.
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/EVREN SEVEN/Primary Examiner, Art Unit 2812
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