Prosecution Insights
Last updated: July 17, 2026
Application No. 17/782,133

MOUNTED IMAGING DEVICE WITH HEAT DISSIPATION

Non-Final OA §102§103
Filed
Jun 02, 2022
Priority
Jan 22, 2020 — JP 2020-007967 +1 more
Examiner
DUREN, TIMOTHY EDWARD
Art Unit
2817
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Hitachi Astemo Ltd.
OA Round
5 (Non-Final)
79%
Grant Probability
Favorable
5-6
OA Rounds
0m
Est. Remaining
91%
With Interview

Examiner Intelligence

Grants 79% — above average
79%
Career Allowance Rate
37 granted / 47 resolved
+10.7% vs TC avg
Moderate +13% lift
Without
With
+12.6%
Interview Lift
resolved cases with interview
Typical timeline
3y 4m
Avg Prosecution
20 currently pending
Career history
84
Total Applications
across all art units

Statute-Specific Performance

§103
82.6%
+42.6% vs TC avg
§102
7.6%
-32.4% vs TC avg
§112
9.4%
-30.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 47 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status 1. The present application, filed on or after May 23, 2022 is being examined under the first inventor to file provisions of the AIA . General Remarks 2. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection. 3. When responding to this office action, applicants are advised to provide the examiner with paragraph numbers in the application and/or references cited to assist the examiner in locating appropriate paragraphs. 4. Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification. Continued Examination Under 37 CFR 1.114 5. A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 3/05/2026 has been entered. Response to Arguments 6. Applicant’s arguments, see Rejections Under 35 U.S.C. § 103, filed 10/14/2025, with respect to the rejection of claim 1 under 35 U.S.C. § 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Kejiro, Kono et al. (Pub No. US20160307953A1) (hereinafter, Kejiro). Regarding the rejection of claim 1, the substantial amended limitations are recited to contain “a portion of the insulating layer is removed to expose the conductor layer…[and] the exposed region with a ground wiring pattern.” Referring to Figure 16 below, the amended limitations were found to be anticipated by Kejiro such that the insulating layer (332) has a portion removed to expose the conductor layer (Conductor/conductor patterns; 333b/331d/c/e). Further, the exposed region has been redefined as R1 instead of R2 which are recited to be connected to a ground wiring pattern (Ground wires; ¶¶[0177, 0195]) in its broadest reasonable interpretation in accordance with the Applicant’s Specification. (See MPEP § 2111). Claim Rejections - 35 USC § 102 7. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. 8. Claims 1 and 9-10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kejiro, Kono et al. (Pub No. US20160307953A1) (hereinafter, Kejiro). Kejiro, Fig 10: (Pertaining to Claim 1) Imaging sensor with imaging element and imaging element substrate PNG media_image1.png 334 453 media_image1.png Greyscale Kejiro, Fig 16: (Pertaining to Claim 1) Imaging sensor cross-section with insulating & conductor layers PNG media_image2.png 390 446 media_image2.png Greyscale Re Claim 1, (Currently Amended) Kejiro teaches an imaging device comprising: an imaging element substrate (Camera board; 33; Fig. 10; ¶[0169]) on which an insulating layer (Solder-resist layer; 332/330; Fig. 16) and a conductor layer (Conductor/conductor patterns; 333b/331d/c/e; Fig. 16) are stacked and an imaging element (Camera module; 3; Fig. 10) is mounted; a housing (2, Figs. 2A, 2B, & 3) which accommodates the imaging element substrate. wherein a surface of the imaging element substrate has a mounting region (Opening; 21; ¶[0149] ln 2-3; Fig. 11) on which an electronic component including the imaging element (Camera module; 3; Fig. 10) is mounted, a covered region (Sensor arrangement region; R1; Fig. 16) in which the conductor layer is covered with the insulating layer (Solder-resist layer; 332; Fig. 16), and an exposed region (Region comprising conductor 333b; R1; Fig. 16) in which a portion of the insulating layer is removed (¶[0177]) to expose the conductor layer from the insulating layer, the exposed region has a ground wiring pattern (Connects to conductor patterns 331 underneath which comprise of ground wires; ¶¶[0177, 0195]), and the exposed region is connected (Per Figs 16 and 19, region R1 comprises of image sensor 33a which connects to the housing 2) to the housing. (See Fig 19 below) Kejiro, Fig 19: Cross-sectional view of image sensor element connecting to housing PNG media_image3.png 351 444 media_image3.png Greyscale Re Claim 9, (New) The imaging device according to claim 1, wherein the conductor layer (Conductor/conductor patterns; 333b/331d/c/e; Fig. 16) is comprised of a metal foil (Conductor 333b may comprise of solder and conductor patterns 331 may be any material with higher thermal conductivity than the insulators 330; ¶¶[0177,0169]) and the metal foil is exposed (Conductor 333b is exposed from insulating layer 332; Fig 16) from the insulating layer at the exposed region. Re Claim 10, (New) The imaging device according to claim 9, wherein the metal foil (Conductor 333b may comprise of solder and conductor patterns 331 may be any material with higher thermal conductivity than the insulators 330; ¶¶[0177,0169]) is a copper foil (Conductor patterns 331 may be copper; ¶[0169]). Claim Rejections - 35 USC § 103 9. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 10. Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Kejiro, Kono et al. (Pub No. US20160307953A1) (hereinafter, Kejiro) as applied to claim 1, and further in view of Shiraishi, Satoshi et al. (Pub No. US20090051774A1) (hereinafter, Shiraishi). Shiraishi, Fig 2: (Pertaining to Claim 6) Illustration of electronic component bonded to an imaging element substrate PNG media_image4.png 534 678 media_image4.png Greyscale Re Claim 6, (Original) Kejiro teaches a surface of the conductor layer (Dissipator Plate; 36b; Fig 16) exposed to the surface of the imaging element substrate (Camera board; 33; Fig. 17; ¶[0169]) is covered with the bonding material (Dissipator Gel; 38; Fig. 17; ¶[0207]) in the exposed region (Dissipator region; R2; Fig 16). However, Kejiro does not teach wherein the electronic component is mounted on the imaging element substrate using a bonding material in the mounting region. In the same field of endeavor, Shiraishi teaches the imaging device according to claim 1, wherein the electronic component (Lens unit; 30; ¶[0047]) is mounted on the imaging element substrate (Wiring substrate; 10; Fig 2; ¶[0043]) using a bonding material (Conductive paste; 64; Fig 2; ¶[0043]) in the mounting region (Supporting portion; 18; Fig 2; ¶[0041]) It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the imaging device as disclosed by Kejiro to have the electronic component mounted on the imaging element substrate using a bonding material in the mounting region, as disclosed by Shiraishi. One of ordinary skill in the art would have been motivated to make this modification in order to use the conductive paste as a conductor from the connection pads C2 to the lens unit 30, such that an actuator such as a piezo motor may drive the lens unit by utility of the conductive paste (Shirashi, ¶[0045]). Furthermore, the conductive paste is ideal such that the adhesion and therefore anchoring may be improved from the wiring substrate to the lens unit, as suggested by Shiraishi (¶[0048]). 11. Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Kejiro, Kono et al. (Pub No. US20160307953A1) (hereinafter, Kejiro) as applied to claim 1, and further in view of Nakamura, Yuta et al. (Pub No. US 20170223243 A1) (hereinafter, Nakamura). Nakamura, Fig 10: (Pertaining to claim 7) Connection portions in imaging apparatus PNG media_image5.png 525 712 media_image5.png Greyscale Re Claim 7, (Currently Amended) Kejiro does not teach the imaging device according to claim 1, further comprising a pair of connection portions, wherein the pair of connection portions are arranged such that a first area of each connection portion that is along a left-right direction is greater than a second area that is along the optical axis direction. In the same field of endeavor, Nakamura teaches the imaging device according to claim 1, further comprising a pair of connection portions (Module covering portion; 3029; Fig 10; ¶[0098]), wherein the pair of connection portions are arranged such that a first area (Area orthogonal to the optical axis; Fig 10) of each connection portion that is along the left-right direction (Along the front of the first area; Fig 10) is greater than a second area (Area on side of module covering portion 3029; Fig 10) that is along the optical axis direction (Along the optical axis; Fig 10). Accordingly, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the imaging device as disclosed by Kejiro, to make a pair of connection portions of a flat plate shape orthogonal to the optical axis, as disclosed by Nakamura. One of ordinary skill in the art would have been motivated to make this modification in order to secure and cover the circuit board behind the imaging element with a sufficient area, and also to have a maximal area orthogonal to the optical axis such that a greater surface area of heat dissipating material may be applied below the connection portions to increase the rate of thermal transfer, as suggested by Nakamura (¶[0103]). Further, although a pair of connection portions is claimed, it would be obvious to use a pair of connection portions for a dual imaging element instead of a single connection portion for a single imaging element, and the duplication of parts has no patentable significance unless a new and unexpected result is produced. (See MPEP 2144 (VI) (B)) 12. Claims 11-13 are rejected under 35 U.S.C. 103 as being unpatentable over Kejiro, Kono et al. (Pub No. US20160307953A1) (hereinafter, Kejiro) as applied to claim 1, and further in view of Hiroyoshi, Sekiguchi et al. (Pub No. US20190391244A1) (hereinafter, Hiroyoshi). Hiroyoshi, Fig 9: (Pertaining to claim 11) Distance-measuring apparatus hardware configuration PNG media_image6.png 460 626 media_image6.png Greyscale Re Claim 11, (New) Kejiro does not teach the imaging device according to claim 1, further comprising: a signal processing substrate which is arranged to face a back surface of the imaging element substrate and on which a circuit element that processes an output signal of the imaging device is mounted, the back surface being opposite to a front surface of the imaging element substrate on which the imaging element is mounted, wherein the imaging element substrate includes a pair of imaging element substrates arranged with an interval in a left-right direction along the front surface, the circuit element is arranged between the pair of imaging element substrates as viewed from an optical axis direction of a lens unit that forms a subject image on the imaging element, each of the pair of imaging element substrates has a first end portion located in an outward direction from the circuit element toward the imaging element as viewed from the optical axis direction, and a second end portion located on an outer side of the first end in the outward direction, and the exposed region is provided in the second end portion of each of the pair of imaging element substrates, and is connected to an end portion located in the outward direction of the housing. In the same field of endeavor, Hiroyoshi teaches the imaging device according to claim 1, further comprising: signal processing substrate (Sensor stay 201 (lower surface); Fig 9) is arranged to face a back surface (Lower surface of 213; Fig 9) of the imaging element substrate (Sensor substrate; 213; Fig. 9; ¶[0109]) and on which a circuit element (Light-signal amplifier circuit; 236; Fig 9; ¶[0114]) that processes an output signal (Reflected signal; Fig 9; ¶[0115]) of the imaging device (Distance-measuring apparatus; 100; Fig 9; ¶[0075]) is mounted, the back surface being opposite to a front surface (Upper surface of 213; Fig 9) of the imaging element substrate on which the imaging element (Imaging device; 212; Fig 9; ¶[0109]) is mounted, wherein the imaging element substrate includes a pair of imaging element substrates (Sensor substrates; 213; 223; Fig. 9; ¶[0109]) arranged with an interval in a left-right direction (From sensor substrate 213 to 223) along the front surface, the circuit element is arranged between the pair of imaging element substrates as viewed from an optical axis direction (Y-direction; Fig 9) of a lens unit (Light-receptive lens; 234; Fig 9; ¶[0114]) that forms a subject image (Captured image is generated from imaging device 212; ¶[0109]) on the imaging element, each of the pair of imaging element substrates has a first end portion (Inner ends of 213/223; Fig 9) located in an outward direction (Outwards from center circuit element; Fig 9) from the circuit element toward the imaging element as viewed from the optical axis direction, and a second end portion (Outer ends of 213/223; Fig 9) located on an outer side of the first end in the outward direction, and the exposed region (Exposed portion of 223 from imaging device 222; Fig 9) is provided in the second end portion of each of the pair of imaging element substrates, and is connected to an end portion (Upper end portion of housing 202; Fig 9) located in the outward direction of the housing (Control board housing; 202; Fig 9; ¶[0105]). It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the imaging device disclosed by Kejiro to have a signal processing substrate facing the back surface of the imaging element substrate to create a space for two imaging element substrates and a housing with a pair of connection portions, as disclosed by Hiroyoshi. Furthermore, the imaging element substrates are mounted where the first end portions are set at an interval from each other, as disclosed by Hiroyoshi. One of ordinary skill in the art would have been motivated to make this modification in order to obtain two distance measurements and therefore higher distance resolution as disclosed by Hiroyoshi (¶[0003-0006]). Re Claim 12, (New) Kejiro teaches the imaging device according to claim 11, wherein the exposed region (Region comprising conductor 333b and image sensor 33a; R1; Figs 16-17) is connected to the housing (2, Fig 17) through an intermediate member (Thermal-transfer gel; 38; Fig 17; ¶[0207]) having thermal conductivity. Re Claim 13, (New) Kejiro teaches the imaging device according to claim 12, wherein the second end portion (Outer left portion of camera board 33; Figs 15/16) of the imaging element substrate (Camera board; 33; Figs 15/16) provided with the exposed region (Region comprising conductor 333b; R1; Fig. 16) is arranged on an outer side of an end portion (Left side of left end of circuit board 4; Fig 15) located in the outward direction (Outwards from circuit board 4; Fig 15) of the signal processing substrate (Circuit board; 4; Fig 15; ¶[0048]). 13. Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Kejiro, Kono et al. (Pub No. US20160307953A1) (hereinafter, Kejiro) in view of Hiroyoshi, Sekiguchi et al. (Pub No. US20190391244A1) (hereinafter, Hiroyoshi) as applied to claim 11, and further in view of Masashi, Adachi (Pub No. JP2016177257A) (hereinafter, Masashi). Masashi, Figs 1 & 3: (Pertaining to claim 14) Imaging unit with dual imaging devices PNG media_image7.png 330 283 media_image7.png Greyscale PNG media_image8.png 285 263 media_image8.png Greyscale Re Claim 14, (New) Kejiro in view of Hiroyoshi do not teach the imaging device according to claim 13, wherein the housing includes a pair of connection portions to which the exposed regions of the pair of imaging element substrates are connected, the pair of connection portions is orthogonal to the optical axis direction and is arranged with an interval in a direction along the front surface, the exposed region of each of the pair of imaging element substrates is orthogonal to the optical axis direction and is arranged to face each of the pair of connection portions with an interval in the optical axis direction, and the intermediate member is provided for the interval between the exposed region of each of the pair of imaging element substrates and each of the pair of connection portions. In the same field of endeavor, Masashi teaches the imaging device according to claim 13, wherein the housing (Camera stay unit; 10; Fig 1; ¶[0014]) includes a pair of connection portions (Lens; 101; Figs 1/2; ¶[0016]) to which the exposed regions (Outer regions of sensor substrates 103; Fig 1) of the pair of imaging element substrates (Individual sensor substrates; 103; Figs 1/3) are connected, the pair of connection portions is orthogonal to the optical axis direction (Optical axis; LX; Fig 1) and is arranged with an interval in a direction (Direction along A-A; Fig 1) along the front surface, the exposed region of each of the pair of imaging element substrates is orthogonal (Outer regions of 103 are orthogonal to LX; Fig 1) to the optical axis direction and is arranged to face each of the pair of connection portions with an interval (Interval between the upper surface of 102 and substrate 103 in optical axis direction LX; Fig 1) in the optical axis direction, and the intermediate member (Image sensors; 102; Fig 1; ¶[0015]) is provided for the interval (Per ¶[0017] the image sensor 102 is fixed on the back side of each lens 101, that is, in the Z-axis direction, and is configured such that the optical axis Lx of each lens 101 and the center of the image plane of the image sensor 102 coincide) between the exposed region of each of the pair of imaging element substrates and each of the pair of connection portions. It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the imaging device as disclosed by Kejiro in view of Hiroyoshi, to create two imaging element substrates connected to the exposed region at the second end portion, where heat may conduct away from the imaging elements as disclosed by Masashi. One of ordinary skill in the art would have been motivated to make this modification in order to create two efficient paths of heat dissipation by having two imaging elements connecting to the thermal interface material, rather than one path of heat dissipation for a single monocular camera such that thermal runaway may be avoided (Masashi, ¶[0024]). Furthermore, to accommodate the position of the exposed region, away from the signal processing substrate, to the outward location of the imaging element substrate, to improve heat dissipation, as suggested by Masashi (Abstract). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to TIMOTHY EDWARD DUREN whose telephone number is (703)756-1426. The examiner can normally be reached 07:30 - 17:00 PST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eliseo Ramos-Feliciano can be reached at (571) 272-7925. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /T.E.D./ Examiner Art Unit 2817 /ELISEO RAMOS FELICIANO/Supervisory Patent Examiner, Art Unit 2817
Read full office action

Prosecution Timeline

Show 5 earlier events
Jul 07, 2025
Request for Continued Examination
Jul 08, 2025
Response after Non-Final Action
Jul 18, 2025
Non-Final Rejection mailed — §102, §103
Oct 14, 2025
Response Filed
Nov 05, 2025
Final Rejection mailed — §102, §103
Mar 05, 2026
Request for Continued Examination
Mar 10, 2026
Response after Non-Final Action
May 21, 2026
Non-Final Rejection mailed — §102, §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

5-6
Expected OA Rounds
79%
Grant Probability
91%
With Interview (+12.6%)
3y 4m (~0m remaining)
Median Time to Grant
High
PTA Risk
Based on 47 resolved cases by this examiner. Grant probability derived from career allowance rate.

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