Detailed Action
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 04/08/2026 is being considered by the examiner.
Response to Amendment
Applicant’s amendment filed 04/28/2026 is entered and considered with this action.
Response to Arguments
Applicant’s Amendment and Arguments filed 04/28/2026 are considered to change the scope of the claims so as to render the prior rejections set forth in the Non-Final office action moot. As such, these rejections over 35 USC 103 are withdrawn.
After further search and consideration, the examiner makes a new grounds of rejection. Applicant’s Amendments to the claims have necessitated these new grounds.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1,2 and 4 are rejected under 35 U.S.C. 103 as being unpatentable over Li et al (JP3226494U) and Reingruber et al (US 20170170111 A1)
As a matter of claim interpretation – as the claim preamble uses “comprising” language, unrecited method steps to be performed prior to, between, or after claimed steps are not excluded from the scope of the claim.
Regarding Claim 1, Li is directed to a printed wiring board having conductive patterning (wiring) set therein.
As per figures 1-4 and [0017]-[0027, Li provides a loading substrate C having a surface C1. The substrate C may be made of a polymer material (insulating material) as per [0017] – the substrate constitutes an insulating layer. A metal seed layer C2 is formed atop the surface C1 such as by plating, where the material of the seed layer may be copper. A patterned mask M is formed directly on the seed layer such as by coating photoresist and then exposing and developing the photoresist. The mask pattern comprises gaps M1 that reveal the exposed seed layer. A series of conductive metal traces E are prepared to fill the gaps M1, where the conductive traces E are at different heights and widths (See Fig 3). The patterned mask M is removed to form wiring traces E on the patterned circuit 1. Afterwards, the seed film that is exposed from the removal of the mask M is also removed such as by etching or flushing.
As per figure 5, a liquid crystalline polymer is deposited so as to cover the outer periphery of the circuit pattern 1, forming the liquid crystalline polymer dielectric layer 2.
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Li thus teaches n insulating layer having a first and second wiring, wherein the second wiring (bounded by the rectangle) is both thicker (taller) and wider than the first (bounded by the oval) and is disposed apart from the first wiring, independent of the first wiring (claim 4), and wherein the gaps where the wirings that are formed do not overlap.
Li does not teach the specific sequential steps for forming the first wiring and the second wiring in successive depositions of photoresists and removals. Li does teach that the mask M may be formed out of photoresist in particular deposition, exposure, and development steps.
These limitations are taught by Reingruber.
Reingruber teaches a method of fabricating semiconductor packages such as those on a printed circuit board having variable redistribution layer thicknesses and the packages themselves. Specifically, the packages comprise a redistribution layer on a dielectric layer where the redistribution layer includes first conductive traces having a first thickness and second conductive traces having a second thickness. Reingruber attributes improvement in trace routing efficiencies to these variable thicknesses in [0054].
At [0038] (referencing Figures 5-6), a method of forming a redistribution layer having conductive traces of differing thicknesses or pitches is illustrated, wherein the redistribution layer 112 may be formed having multiple thicknesses using a two-operation plating approach to form a first sub-layer for thin/fine-pitch conductive traces and a second layer for thick/standard-pitch traces. A patterned plating resist may be deposited on metal seed layer 410 formed on the back surface 114 of the dielectric layer 110. This dielectric layer may be over a base substrate such as an integrated circuit illustrated as 104. A patterned plating resist 414 may be deposited so that a first region of seed layer 410 is exposed through a patterned plating resist 414 and a second region of the seed layer 410 is covered by the patterned plating resist 414.
A conductive pattern 602 may be formed on the first region of the seed layer 410 – as per Fig. 6B, this may be copper plated within the exposed regions between exposed resist 414 to form a conductive pattern. Another metal may be used, as the seed layer 410 is described elsewhere ([0026]) as being nickel, tungsten, copper, or a combination of various materials. This may be plated to have a first thickness 604.
The plating resist may then be stripped from the semiconductor structure to separate the portions of the conductive pattern 602 having a first thickness 604 by portions of metal seed layer 410 that are thinner than the first thickness 604 (Claim 2).
A protective resist 420 is then deposited on a portion of the conductive pattern 602 and another portion of the pattern 602 remains uncovered. An additional thickness 606 of the conductive pattern 602 is then formed on the second (uncovered) portion of the conductive pattern 602 (Fig 6E). The plating resist 420 is then stripped away to leave one or more first segments 608 and one or more second segments 610 of the conductive pattern 602. The segments 608 may have a thickness 604 equivalent to the thickness of the metal seed layer 401 and the thickness of plating added to the pattern 602 during the first plating operation. The second segment(s) 610 may have a second thickness 612 including the thickness 604 and additional thickness 606 added to the conductive pattern 602. As such, the first thickness 604 of segments 608 is less than that of the second thickness 612 of segments 610.
The metal seed layer 410 between the segments 608 and 610 may be removed ([0045).
Li and Reingruber are alike in field of endeavor and comprise substantially similar steps – both are concerned with the patterning of resists, insulating layer formation, plating of wires so as to form circuit patterns, and the manufacture of circuit boards. A person having ordinary skill in the art would glean from Reingruber that a thicker wiring could be formed second after a thinner primary wiring is formed – incorporating the more-specific steps of Reingruber into the method of producing the wiring patterns E so as to arrive at a more exacting process, noting the discussion of different pitches which includes differing widths and spacings in Reingruber at [0038].
A person of ordinary skill in the art would have found it obvious to arrive at the claimed process by modifying the process of forming the wiring structures of Li, using the two resist process of Reingruber with a reasonable expectation of forming a circuit board comprising wiring having different thicknesses thereon facilitating an improvement in routing efficiencies.
Claim(s) 5 is rejected under 35 U.S.C. 103 as being unpatentable over Li et al (JP3226494U) as applied to claim 1 above, and further in view of Nakano et al (US 20100181100 A1).
Regarding Claim 5, Li discloses the limitations of the claims as discussed above regarding claim 1. However, Li is silent on the thickness of the seed layer.
This limitation is taught by Nakano, who discloses a copper wiring board and a method for manufacturing same (abstract).
Nakano’s wiring board, as per example 1 in [0048]-[0055], patterning trenches into an insulating substrate followed by plating a nickel metal seed layer having a thickness of 200nm, followed by a copper plating film and further processing. The seed metal of Nakano may additionally or otherwise be chromium, palladium , tungsten, titanium, and alloys thereof such as nickel-boron and nickel-phosphorus – the disclosed genus overlaps that of metals disclosed for seed layers in Reingruber. Additionally, the general disclosure covers thickness of the seed layer may more generally be between 0.01 microns to 5 microns ( 10 to 5000 nm) and that the use of nickel and nickel-boron alloy in particular aid in retarding the diffusion of copper used in wiring and thus improving the reliability of the wiring. Regarding the thickness, the thickness provided in the reference is intended to avoid a lack of seed function (too thin) or difficulty in removing the layer between wires (too thick).
A person of ordinary skill in the art would have found it obvious to modify the process of Reingruber and Li discussed above by using a metal such as nickel or tungsten or alloy thereof in a seed layer having a thickness of 10 to 5000nm as a seed layer for the plating as taught by Nakano which facilitates easy processing by maintaining the removability of the seed layer between wires as taught by Nakano.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/A.P.T./Examiner, Art Unit 1737
/MARTIN J ANGEBRANNDT/Primary Examiner, Art Unit 1737 July 29, 2026
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