Detailed Action
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 11/19/2025 has been entered.
Response to Amendment
Applicant’s amendment filed 11/19/2025 has been accepted and is entered. Claim 1 has been amended. No new matter has been added.
Response to Arguments
Applicant’s Arguments filed 11/19/2025 have been accepted and are considered. All rejections over 35 USC 103 as set forth in the prior office action are withdrawn.
After further search and consideration, the Examiner makes a new grounds of rejection as set forth in the body of the action below.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-4 are rejected under 35 U.S.C. 103 as being unpatentable over Hirata (JP 2010067317A) and Reingruber et al (US 20170170111 A1).
Regarding Claims 1-4, Hirata discloses a substrate and wired patterns thereupon (circuit board) comprising two separate wirings, and methods of making such.
The board comprises an insulating layer disposed atop a substrate, a lead and a write wire, and an inter-wire insulating layer([0016]), wherein the lead wiring and write wiring have different line capacity. The thickness of a lower lead wiring and a lower write wiring are different ([0022], Fig. 3b and Fig 4 – wiring 3a is the lower lead wiring, which is thicker than write wiring 4a).
As per [0023]-[0025] and Figures 3 and 4, the wirings 3a and 4a are formed using conventional plating methods, wherein a resist 11 is formed with an opening atop wiring 3a so as to cover the wiring 4a, then a further plating of an existing wiring is performed so as to increase the thickness of the wiring 3a. After, a second resist is placed so as to cover the wiring 3a and an open section for forming the wiring 4a is deposited. The wiring 4a is plated in the open section and the resist removed (claim 4). The variable thicknesses of the wirings 3a and 4a are preferred so as to provide different wiring capacities.
Hirata does not specifically teach a seed film and its removal from exposed portions made during the first and second wrings. Hirata does teach that wires may be formed via conventional plating methods. Hirata does not specifically teach which wire may be formed first or second.
This limitation is met by Reingruber.
Reingruber teaches a method of fabricating semiconductor packages such as those on a printed circuit board having variable redistribution layer thicknesses and the packages themselves. Specifically, the packages comprise a redistribution layer on a dielectric layer where the redistribution layer includes first conductive traces having a first thickness and second conductive traces having a second thickness. Reingruber attributes improvement in trace routing efficiencies to these variable thicknesses in [0054].
At [0038] (referencing Figures 5-6), a method of forming a redistribution layer having conductive traces of differing thicknesses or pitches is illustrated, wherein the redistribution layer 112 may be formed having multiple thicknesses using a two-operation plating approach to form a first sub-layer for thin/fine-pitch conductive traces and a second layer for thick/standard-pitch traces. A patterned plating resist may be deposited on metal seed layer 410 formed on the back surface 114 of the dielectric layer 110. This dielectric layer may be over a base substrate such as an integrated circuit illustrated as 104. A patterned plating resist 414 may be deposited so that a first region of seed layer 410 is exposed through a patterned plating resist 414 and a second region of the seed layer 410 is covered by the patterned plating resist 414.
A conductive pattern 602 may be formed on the first region of the seed layer 410 – as per Fig. 6B, this may be copper plated within the exposed regions between exposed resist 414 to form a conductive pattern. Another metal may be used, as the seed layer 410 is described elsewhere ([0026]) as being nickel, tungsten, copper, or a combination of various materials. This may be plated to have a first thickness 604.
The plating resist may then be stripped from the semiconductor structure to separate the portions of the conductive pattern 602 having a first thickness 604 by portions of metal seed layer 410 that are thinner than the first thickness 604 (Claim 2).
A protective resist 420 is then deposited on a portion of the conductive pattern 602 and another portion of the pattern 602 remains uncovered. An additional thickness 606 of the conductive pattern 602 is then formed on the second (uncovered) portion of the conductive pattern 602 (Fig 6E). The plating resist 420 is then stripped away to leave one or more first segments 608 and one or more second segments 610 of the conductive pattern 602. The segments 608 may have a thickness 604 equivalent to the thickness of the metal seed layer 401 and the thickness of plating added to the pattern 602 during the first plating operation. The second segment(s) 610 may have a second thickness 612 including the thickness 604 and additional thickness 606 added to the conductive pattern 602. As such, the first thickness 604 of segments 608 is less than that of the second thickness 612 of segments 610 (Claim 3).
The metal seed layer 410 between the segments 608 and 610 may be removed ([0045).
Hirata and Reingruber are alike in field of endeavor and comprise substantially similar steps – both are concerned with the patterning of resists, insulating layer formation, plating of wires so as to form circuit patterns, and the manufacture of circuit boards. A person having ordinary skill in the art would glean from Reingruber that the use of a seed layer would be amenable to forming a wiring, and that a thicker wiring could be formed second after a thinner primary wiring is formed.
A person of ordinary skill in the art would have found it obvious to arrive at the claimed invention from the general disclosure of Hirata and Reingruber to arrive at a circuit board comprising wiring having different thicknesses thereon abetting an improvement in routing efficiencies.
Claim(s) 5 is rejected under 35 U.S.C. 103 as being unpatentable over Hirata (JP 2010067317A) and Reingruber (US 20170170111 A1) as applied to claim 1 above, and further in view of Nakano et al (US 20100181100 A1).
Regarding Claim 5, Reingruber discloses the limitations of the claim as discussed regarding claim 1 above.
However, Hirata and Reingruber fail to disclose a specific numerical thickness for any component, only reciting relative thicknesses.
This limitation is met by Nakano, who discloses a copper wiring board and a method for manufacturing same (abstract).
Nakano’s wiring board, as per example 1 in [0048]-[0055], patterning trenches into an insulating substrate followed by plating a nickel metal seed layer having a thickness of 200nm, followed by a copper plating film and further processing. The seed metal of Nakano may additionally or otherwise be chromium, palladium , tungsten, titanium, and alloys thereof such as nickel-boron and nickel-phosphorus – the disclosed genus overlaps that of metals disclosed for seed layers in Reingruber. Additionally, the general disclosure covers thickness of the seed layer may more generally be between 0.01 microns to 5 microns ( 10 to 5000 nm) and that the use of nickel and nickel-boron alloy in particular aid in retarding the diffusion of copper used in wiring and thus improving the reliability of the wiring. Regarding the thickness, the thickness provided in the reference is intended to avoid a lack of seed function (too thin) or difficulty in removing the layer between wires (too thick).
A person of ordinary skill in the art would have found it obvious to use a metal such as nickel or tungsten or alloy thereof in a seed layer of Reingruber and Hirata in a thickness of 10 to 5000nm so as to maintain the function of the layer as a seed layer while also enabling ease of processing by maintaining the removability of the seed layer between wires as taught by Nakano.
Conclusion
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/A.P.T./Examiner, Art Unit 1737
/JONATHAN JOHNSON/Supervisory Patent Examiner, Art Unit 1734