DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 4/22/2026 has been entered.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 10, 12-16, 18-19 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. Claim 10 recites “a second isolation layer arranged on the gate only along the first direction, wherein the second isolation layer extends along a third direction”. Applicant’s remarks point to Fig. 2A to support the amendment to claim 10 which show direction Z as the first direction and the second isolation layer is feature 216 which appear only on the sidewalls of the gate 214. However, the grammar of the claim requires that the second isolation layer is arranged on the gate only the portion of the gate that extends along the first direction (Z direction).
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This is not supported by the originally filed specification or drawings as the second isolation layer 216 is clearly shown to extend along the sidewalls of the gate that extend in the X direction. If applicant wishes to claim that the second isolation layer extends only along sidewalls of the gate that extend in the X direction thereby forming a stacked structure in the Z direction then this should be claimed. Claim 10 also recites “a length of the second isolation layer along a second direction is equal to a length of the gate along the second direction”. Applicant’s remarks point to Fig. 2A to support the amendment to claim 10 which shows that the length of the second isolation layer 216 in the X direction is equal the length of the gate AND gate dielectric 215 in the X direction, not the gate conductor alone as the claim requires. Applicant seems to be relying on limitations from multiple distinct embodiments of the disposition of the second isolation layer. Therefore the claims are rejected as failing to comply with the written description requirement.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 10, 12-16, 18-19 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 10 recites “a second isolation layer arranged on the gate only along the first direction, wherein the second isolation layer extends along a third direction”. Applicant’s remarks point to Fig. 2A to support the amendment to claim 10 which show direction Z as the first direction and the second isolation layer is feature 216 which appear only on the sidewalls of the gate 214. However, the grammar of the claim requires that the second isolation layer is arranged on the gate only the portion of the gate that extends along the first direction (Z direction).
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It is unclear if the claim should be interpreted plainly in which case the claim requires that the second isolation layer extends only along the surface of the gate that extends in the Z direction or if the claim should be interpreted in light of the specification which requires that the second isolation layers extend in the Z direction on opposite sidewalls of the gate.
Claim 10 recites “a length of the second isolation layer along a second direction is equal to a length of the gate along the second direction, and the first direction, the second direction and the third direction are perpendicular to each other.” It is unclear due to the grammar of the claim limitation whether the claim requires that 1) the length of the second isolation layer along the second direction is equal to the length of the gate along the second and first direction and wherein the second and third direction are perpendicular to each other, OR 2) the length of the second isolation layer along the second direction is equal to the length of the gate along the second direction and wherein the first, second and third direction are all perpendicular to each other.
Therefore, the claims are rejected as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 10, 12-14, 16 and 19 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 20110039381 A1 (Son).
Re claim 10, Son teaches a transistor array (Figs. 1 and 14), comprising a plurality of transistors arranged in an array, each of the plurality of transistors comprising:
a channel region (channel regions 21a, 21b, 21c, 21d);
a source located at a first end of the channel region (upper impurity regions 24b);
a drain located at a second end of the channel region (lower impurity regions 24a), wherein the first end and the second end are opposite ends of the channel region in a first direction (1st direction see annotated Figs. 1, 15) which is a thickness direction of a wafer forming the channel region (channel regions 21 Fig. 14);
a gate (gate lines 33a, 33b) located on only one side of the channel region and corresponding to the channel region (located only the exposed curved side of the cylindrical channel pillars);
a gate oxide layer (gate dielectric layers 30a, 30b, 30c, 30d) located between the channel region and the gate; and
a second isolation layer (gate masks 18a, 18b) arranged on the gate only along the first direction (1st direction see annotated Figs. 1, 14), wherein the second isolation layer extending extends along a third direction (3rd direction see annotated Figs. 1, 14), wherein a size of the second isolation layer in the third direction is greater than a size of the channel region in the third direction (region A shows 18a extending in the 3rd direction and having a greater lateral dimension that the pillars 21 see annotated Figs. 1, 14),
the third direction is parallel to a column arrangement direction of the transistor array (3rd direction see annotated Figs. 1, 14)
a length of the second isolation layer along a second direction is equal to a length of the gate along the second direction (region B shows the lateral dimension of 18a extending in the 2nd direction is equal to the lateral dimension of the entire gate electrode see annotated Figs. 1, 14), and
the first direction, the second direction and the third direction are perpendicular to each other (Figs. 1, 14).
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Re claim 19, Son further teaches wherein each of the plurality of transistors is an L- shaped transistor, sizes of the first end and the second end in the second direction are different, and the source, the channel region and the drain of the L-shaped transistor form an L-shaped structure (lowest drain portion 24a extends further in the 2nd direction giving the transistor body a L-shape see annotated region B Fig. 14).
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Re claim 12, Son teaches a semiconductor device, comprising:
at least one memory array (Figs. 1 and 14 [0061]) and a plurality of bit lines (bit lines in DRAM or PCRAM are the lines connected to the drain of the selection transistors, conductive patterns 52a, 52b Fig. 1) arranged in parallel along the second direction (2nd direction see annotated Figs. 1, 14), wherein each of the at least one memory array comprises the transistor array of claim 10, the third direction intersects with the second direction (2nd and 3rd directions see annotated Figs. 1 and 14), and a plane where the third direction and the second direction are located is perpendicular to the first direction (2nd and 3rd directions see annotated Figs. 1 and 14);
the gate (gate lines 33a, 33b) of each of the plurality of transistors arranged in parallel along the third direction (Fig. 1) is configured to receive a word line voltage and control each of the plurality of transistors to be turned on or off by the word line voltage (word lines in DRAM or PCRAM are the gates connected to the selection transistors); and
each of the plurality of bit lines is connected to the source or the drain of each of the plurality of transistors arranged in parallel along the second direction (Figs. 1 and 14), and is configured to perform a read or write operation on each of the at least one memory array when each of the plurality of transistors is turned on (this claim limitation merely states how DRAM and PCRAM operates).
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Re claim 13, Son teaches wherein each of the at least one memory array further comprises a storage capacitor (information storage elements 60 [0061]), the storage capacitor has one end connected to the drain or the source of the transistor and the other end configured to receive an external electrical signal, and is configured to store data written in each of the at least one memory array (DRAM storage capacitor for the standard 1T-1C memory cell region Fig. 14 [0061]).
Re claim 14, Son teaches wherein each of the at least one memory array further comprises an adjustable resistor (phase change variable resistor in PCRAM embodiment [0061]), the adjustable resistor is connected between the bit line and the source of the transistor, or is connected between the bit line and the drain of the transistor, and is configured to adjust a state of data stored in each of the at least one memory array by a bit line voltage provided by the bit line (standard operation of PCRAM IT-1B memory cells).
Re claim 16, Son teaches wherein when the semiconductor device comprises a plurality of memory arrays, the plurality of memory arrays are connected in parallel or in series (Figs. 1 and 14).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20110039381 A1 (Son) further in view of US 20200111800 A1 (Ramaswamy).
Re claim 15, Son teaches the semiconductor device of claim 12, but Son does not explicitly teach wherein each of the at least one memory array further comprises a ferroelectric capacitor, the ferroelectric capacitor comprises an upper electrode, a lower electrode and a ferroelectric material layer located between the upper electrode and the lower electrode; the upper electrode of the ferroelectric capacitor is connected to the drain of the transistor, the lower electrode of the ferroelectric capacitor is connected to the source of the transistor, and the ferroelectric capacitor is configured to store data written into each of the at least one memory array.
However, Son does teach that the transistor array can be used in different 1T-1B memory cell arrays such as DRAM and PCRAM.
Ramaswamy teaches a memory cel array wherein the selection transistors are formed as a 2D array of vertical transistors and the bit storage can either be a storage capacitor for DRAM or a ferroelectric capacitor (FRAM) (Fig. 13 [0067]).
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It would have been obvious to one of ordinary skill in the art at the time of filing to form the memory array of Son having ferroelectric capacitors for the bit storage.
The motivation to do so is that FRAM based on ferroelectric capacitors provides the predictable result of formed a non-volatile memory array which does not need constant refreshing due to charge leakage on the capacitor plates as with DRAM. Additionally, Son teaches that the bit storage can be swapped out for other two terminal non-volatile bit storage such as PCRAM.
Claim(s) 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20110039381 A1 (Son) further in view of US 20170294445 A1 (Son ‘445).
Re claim 18, Son teaches the transistor array of claim 10, and Son further teaches wherein each of the plurality of transistors is a columnar transistor, sizes of the first end and the second end in the second direction are substantially the same (Figs. 1 and 14). However, Son does not explicitly teach wherein the cross-section shapes of both the source and the drain of the columnar transistor are semicircles or triangles.
Son ‘445 teaches columnar channel patterns for vertical transistors wherein the cross-sectional profile of the active body can be a full circle or a semicircle (Figs. 5A, 6A [0070]).
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Applicant has not disclosed that the claimed shape is for a particular unobvious purpose, produces an unexpected result, or is otherwise critical, which are criteria that have been held to be necessary for specific shape limitations to be prima facie unobvious. The claimed shape is considered to be a "preferred" or "optimum" shape out of a plurality of well known shapes that a person of ordinary skill in the art at the time the invention was made would have found obvious to provide to the invention of the cited prior art reference, using routine experimentation and optimization of the invention. Applicant has not provided any evidence that the shape of the capacitor is critical to the operation of the device. Furthermore, the prior art teaches that the shape of the element is known. In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966) (The court held that the configuration of the claimed disposable plastic nursing container was a matter of choice which a person of ordinary skill in the art would have found obvious absent persuasive evidence that the particular configuration of the claimed container was significant.). MPEP 2144.04 (IV)(B).
Response to Arguments
Applicant’s arguments with respect to claim(s) 10 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRIGITTE A PATERSON whose telephone number is (571)272-1752. The examiner can normally be reached Monday-Friday 9:00AM-5:00PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Kraig can be reached at 571-272-8660. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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BRIGITTE A. PATERSON
Primary Examiner
Art Unit 2896
/BRIGITTE A PATERSON/Primary Examiner, Art Unit 2896
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