DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 10, 12-13, 15-16, 18 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 10,388,658 B1 (Ramaswamy).
Re claim 10, Ramaswamy teaches a transistor array (Fig. 1), comprising a plurality of transistors arranged in an array, each of the plurality of transistors comprising:
a channel region (channel region 20);
a source (source/drain region 18) located at a first end of the channel region;
a drain (source/drain region 22/semiconductor material 12) located at a second end of the channel region, wherein the first end and the second end are opposite ends of the channel region in a first direction (Fig. 1) which is a thickness direction of a wafer forming the channel region;
a gate (gate 24) located on only one side (right side) of the channel region and corresponding to the channel region;
a gate oxide layer (gate insulator 26) located between the channel region and the gate; and
a second isolation layer (dielectric material 77 in contact with gate 24) disposed only on a sidewall of the gate that extends in a second direction (Fig. 2), thereby forming a stacked structure in the first direction, wherein the second isolation layer extends along a third direction, a size of the second isolation layer in the third direction is greater than a size of the channel region in the third direction (Fig. 1 dielectric material 77 fills the void between transistors in each row), the third direction is parallel to a column arrangement direction of the transistor array (Fig. 1 should the column of each transistor are arranged parallel in the third direction), and a length of the second isolation layer along the second direction is equal to a total length of the gate and the gate oxide layer along the second direction (the length of the dielectric material 77 which is in contact with the gate 24 plus a portion of the length equal to the thickness of the gate oxide layer 26 is ‘a length’ of the material reading upon the claim), and wherein the first direction, the second direction and the third direction are perpendicular to each other,
wherein each of the plurality of transistors is an L-shaped transistor (Figs. 1-2), sizes of the first end and the second end in the second direction are different, and wherein the source, the channel region and the drain of the L-shaped transistor form an L-shaped structure (Figs. 1-2).
PNG
media_image1.png
506
752
media_image1.png
Greyscale
PNG
media_image2.png
534
685
media_image2.png
Greyscale
Re claim 18, Ramaswamy teaches wherein cross-section shapes of the source and the drain parallel to a preset plane are different, and the preset plane is perpendicular to the first direction (Figs. 1-2 shows that the drain region 22/12 is a different shape than source 18); and each of the cross-section shapes of the source and the drain comprises any one of a square, a semicircle, a triangle, or any polygon (rectangles are polygons).
Re claim 12, Ramaswamy teaches a semiconductor device, comprising:
at least one memory array (array 10) and a plurality of bit lines (digitlines 34) arranged in parallel along the second direction,
wherein each of the at least one memory array comprises the transistor array of claim 10, the third direction intersects with the second direction (Figs. 1-2), and a plane where the third direction and the second direction are located is perpendicular to the first direction (Figs. 1-2);
the gate of each of the plurality of transistors arranged in parallel along the third direction is configured to receive a word line voltage (gate 24 are part of wordline 30) and control each of the plurality of transistors to be turned on or off by the word line voltage (this merely states how a transistor works); and
each of the plurality of bit lines is connected to the source or the drain of each of the plurality of transistors arranged in parallel along the second direction, and is configured to perform a read or write operation on each of the at least one memory array when each of the plurality of transistors is turned on (Figs. 1-2 these limitations are a recitation of the nominal operation of transistor selectors in DRAM as is taught in Ramaswamy).
Re claim 13, Ramaswamy teaches wherein each of the at least one memory array further comprises a storage capacitor (capacitor 75), the storage capacitor has one end connected to the drain or the source of the transistor and the other end configured to receive an external electrical signal, and is configured to store data written in each of the at least one memory array (Figs. 1-2 these limitations are a recitation of the nominal operation of transistor selectors in DRAM as is taught in Ramaswamy).
Re claim 15, Ramaswamy teaches wherein each of the at least one memory array further comprises a ferroelectric capacitor (capacitor 75 can be formed with ferroelectric material making it a ferroelectric capacitor), the ferroelectric capacitor comprises an upper electrode (first capacitor electrode 40) , a lower electrode (second capacitor electrode 50) and a ferroelectric material layer (capacitor insulator 46) located between the upper electrode and the lower electrode; the upper electrode of the ferroelectric capacitor is connected to the drain of the transistor (indirectly electrically connected through the intervening layers Figs. 1-2), the lower electrode of the ferroelectric capacitor is connected to the source of the transistor (indirectly electrically connected through the intervening layers Figs. 1-2), and the ferroelectric capacitor is configured to store data written into each of the at least one memory array.
Re claim 16, Ramaswamy teaches wherein when the semiconductor device comprises a plurality of memory arrays, the plurality of memory arrays are connected in parallel or in series (nominal structure of memory arrays Figs. 1-2).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 10,388,658 B1 (Ramaswamy) further in view of US 20110039381 A1 (Son).
Re claim 14, Ramaswamy teaches wherein each of the at least one memory array further comprises a bit storage element, such as a static or ferroelectric capacitor, is connected between the bit line and the source of the transistor, or is connected between the bit line and the drain of the transistor, and is configured to adjust a state of data stored in each of the at least one memory array by a bit line voltage provided by the bit line (Col. 5 lines 33-62). However, Ramaswamy does not explicitly teach wherein the bit storage element is an adjustable resistor.
Son teaches a memory array of 1 transistor, 1 bit storage memory core regions wherein the bit storage can be either a capacitor or a variable resistor (phase change variable resistor in PCRAM embodiment [0061]).
It would be obvious at the time of filing the invention to change the invention of Ramaswamy wherein the bit storage element is a variable resistor rather than a capacitor.
The motivation to do so is that Ramaswamy teaches one transistor-one bit storage element memory array having various two terminal bit storage devices (Col. 5 lines 33-62), Son teaches the obviousness of using capacitors or variable resistors in one transistor-one bit storage element memory arrays. Using a variable resistance element for bit storage provides the predictable result of making the memory array non-volatile so that there is no need for regular bit refresh as is necessary with static capacitor bit storage.
Response to Arguments
Applicant’s arguments with respect to the pending claim(s) have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRIGITTE A PATERSON whose telephone number is (571)272-1752. The examiner can normally be reached Monday-Friday 9:00AM-5:00PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Kraig can be reached at 571-272-8660. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
BRIGITTE A. PATERSON
Primary Examiner
Art Unit 2896
/BRIGITTE A PATERSON/Primary Examiner, Art Unit 2896
Prosecution Insights