Prosecution Insights
Last updated: October 04, 2026
Application No. 17/785,091

POWER MODULE WITH IMPROVED ELECTRICAL AND THERMAL CHARACTERISTICS

Non-Final OA §103
Filed
Jun 14, 2022
Priority
Dec 28, 2019 — DK PA201901556 +1 more
Examiner
DINH, TUAN T
Art Unit
2848
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Danfoss Silicon Power GmbH
OA Round
6 (Non-Final)
79%
Grant Probability
Favorable
6-7
OA Rounds
0m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 79% — above average
79%
Career Allowance Rate
944 granted / 1198 resolved
+10.8% vs TC avg
Strong +22% interview lift
Without
With
+22.1%
Interview Lift
resolved cases with interview
Typical timeline
2y 11m
Avg Prosecution
29 currently pending
Career history
1229
Total Applications
across all art units

Statute-Specific Performance

§101
0.1%
-39.9% vs TC avg
§103
45.0%
+5.0% vs TC avg
§102
38.5%
-1.5% vs TC avg
§112
6.0%
-34.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1198 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 09/10/25 has been entered. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1-4, and 11-12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tsunoda (U.S. 2006/02441 16), in view of Takao et al. (U.S. 2016/0284683) cited in the record. As to claim 1, Tsunoda discloses a power module (1) as shown in figures 1-3 comprising a group of at least three rectangular electrical power components (IGBT chips 20, para-0031) arranged on a substrate (14, para-0031), at least one the power components that has a line passes through the geometric centres of the remaining rectangular electrical power components (20) of the group, and wherein at least one side (bottom of the three components 20) of another of the rectangular electrical power components is orthogonal or parallel to the line. Tsunoda does not specifically disclose at least one side of at least one of the rectangular electrical power components that is not orthogonal or parallel to the line. It would have been an obvious matter of design choice to have at least one side of at least one of the rectangular electrical power components that is not orthogonal or parallel to the line in order to provide achieve minimum space for the power components mounted on the substrate or board, since such a modification would have involved a mere change in the size or shape of a component. A change in size/shape is generally recognized as being within the level of ordinary skill in the art. In re Rose, 105 USPQ 237 (CCPA 1995). Further, Takao teaches a semiconductor module (100) as shown in figure 1 comprising at least one side of at least one of the rectangular electrical power components that is not orthogonal or parallel to the line. It would have been obvious to one having ordinary skill in the art before the effective filling date to have a teaching of Takao employed in the power module of Tsunoda in order to achieve minimum space for the power components mounted on the substrate or board. As to claim 2, Tsunoda as modified by Takao discloses the geometric centres of all of the rectangular electrical power components (20) that comprise the group are disposed along a straight line, see figure 1. As to claim 3, Tsunoda as modified by Takao discloses in figure 2 the group of rectangular electrical power components (20) are electrically connected in parallel (para-0007+). As to claim 4, Tsunoda as modified by Takao discloses the rectangular electrical power components (20) are semiconductor switches (IGBT chips). As to claim 11, Tsunoda discloses a power module (1) as shown in figures 1-3 comprising: a group of at least three rectangular electrical power components (20) arranged on a substrate (14); and a first load track (16) and a second load track (17) located on the substrate (14); wherein at least one of the rectangular electrical power components (20) passes through the line of the geometric centres of the remaining rectangular electrical power components of the group; and wherein the at least three rectangular electrical power components (20) are arranged on the first load track (16). Tsunoda does not specifically disclose at least one side of at least one of the rectangular electrical power components that is not orthogonal or parallel to the line. It would have been an obvious matter of design choice to have at least one side of at least one of the rectangular electrical power components that is not orthogonal or parallel to the line in order to provide achieve minimum space for the power components mounted on the substrate or board, since such a modification would have involved a mere change in the size or shape of a component. A change in size/shape is generally recognized as being within the level of ordinary skill in the art. In re Rose, 105 USPQ 237 (CCPA 1995). Further, Takao teaches a semiconductor module (100) as shown in figure 1 comprising at least one side of at least one of the rectangular electrical power components that is not orthogonal or parallel to the line. It would have been obvious to one having ordinary skill in the art before the effective filling date to have a teaching of Takao employed in the power module of Tsunoda in order to achieve minimum space for the power components mounted on the substrate or board. As to claim 12, Tsunoda as modified by Takao further comprising wire-bonds (46) connecting the at least three rectangular electrical power components (20) to the second load track. Claim(s) 5, and 7-9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tsunoda in view of Takao, and further in view of Morinaga et al. (U.S. 2018/0367054) cited in the record. As to claim 5, Tsunoda and Takao discloses all of the limitations of claimed invention except for the power module provides a half bridge circuit. Morinaga teaches a semiconductor device (1) as shown in figures 1-5 comprising the power module provided a half bridge circuit (10, 20 or 30, 40). It would have been obvious to one having ordinary skill in the art before the effective filling date to have a teaching of Morinaga employed in the power module of Tsunoda and Takao in order to control a low input impedance to reduce the conductive losses, and a fast-switching time to reduce the switching losses. Regarding claim 7, Tsunoda as modified by Takao and Morinaga teaches external DC power terminals (i.e. T1, T11) are arranged at one end of the module in the first direction, and one or more AC power terminals (T4, T14) are arranged at the opposite end of the module in the first direction. It would have been obvious to one having ordinary skill in the art before the effective filling date to have a teaching of Morinaga employed in the power module of Tsunoda and Takao in order to provide a cascade-connection structurer. Regarding claims 8-9, Tsunoda as modified by Takao and Morinaga teaches the angle between a side of at least one of the rectangular electronic power components (10, 20, 30, 40) and a line that passes through the geometric centres of the remaining rectangular electrical power components (10, 20 or 20, 40, or 30, 40) of the group is within the range 30-60 or is 45°. Allowable Subject Matter Claim 6 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Claim 10 is allowed. The following is an examiner's statement of reasons for allowance: Neither the references cited nor the cited references teach, suggest, or in combination of a power module having an inner load track, two intermediate load tracks and two outer load tracks each of which load tracks is elongated and extends substantially across the substrate in a first direction; wherein the two intermediate load tracks are arranged adjacent to the inner load track, and each outer load track is arranged on the opposite side of one of the two intermediate load tracks to that of the inner load track with respect to a second direction substantially orthogonal to the first direction; wherein the power module comprises two first sets of semiconductor switches, each first set of semiconductor switches being mounted on the inner load track and electrically connected to an intermediate load track such that the first sets of semiconductor switches form a first arm of the half bridge circuit; and wherein the power module comprises two second sets of semiconductor switches, each second set of semiconductor switches being mounted on an intermediate load track and electrically connected to an outer load track, such that the second sets of semiconductor switches form a second arm of the half bridge circuit. Response to Arguments Applicant should submit an argument under the heading “Remarks” pointing out disagreements with the examiner’s contentions. Applicant must also discuss the references applied against the claims, explaining how the claims avoid the references or distinguish from them. Any inquiry concerning this communication or earlier communications from the examiner should be directed to TUAN T DINH whose telephone number is (571)272-1929. The examiner can normally be reached MON-FRI: 8AM-4:30PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Timothy Dole can be reached at 571-272-2229. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /TUAN T DINH/Primary Examiner, Art Unit 2848
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Prosecution Timeline

Show 13 earlier events
Jul 28, 2025
Notice of Allowance
Sep 10, 2025
Request for Continued Examination
Sep 12, 2025
Response after Non-Final Action
Oct 10, 2025
Non-Final Rejection mailed — §103
Jan 08, 2026
Notice of Allowance
Apr 24, 2026
Response after Non-Final Action
Jul 26, 2026
Response after Non-Final Action
Oct 01, 2026
Non-Final Rejection mailed — §103 (current)

Precedent Cases

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EMBEDDED PACKAGE STRUCTURE, POWER SUPPLY APPARATUS, AND ELECTRONIC DEVICE
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Patent 12733100
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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

6-7
Expected OA Rounds
79%
Grant Probability
99%
With Interview (+22.1%)
2y 11m (~0m remaining)
Median Time to Grant
High
PTA Risk
Based on 1198 resolved cases by this examiner. Grant probability derived from career allowance rate.

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