DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on September 11th 2025 has been entered.
Response to Arguments
Applicant’s arguments, filed September 11th 2025, with respect to the rejection(s) of claim(s) 14-24 under 35 U.S.C. 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of 35 U.S.C. 103.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claim(s) 14-18, and 22-24 are rejected under 35 U.S.C. 103 as being unpatentable over Nakamura et al. (JP 2016075567 A) in view of Pellenc (US 20090039830 A1) further in view of White et al. (US 20140167780 A1).
Regarding Claim 14, Nakamura teaches a method (Fig. 3) for operating a battery (60) having at least two battery cells (14), comprising:
a symmetrization process in which states of charge of the at least two battery cells are symmetrized continuously or repeatedly (¶[29] “When the CPU 70 detects the minimum voltage battery, it executes an equalization process (S12)”);
establishing whether a same battery cell was determined as the battery cell having the lowest quiescent voltage during an entirety of the first predefined period (¶[30] Furthermore, the CPU 70 judges, based on the numbers of the secondary batteries 14 stored in the memory 76, whether or not the same secondary batteries 14 consecutively have the lowest voltage (S14));
and performing a checking process in which the symmetrization process is interrupted or terminated and a check is carried out to determine whether the battery cell for which the lowest quiescent voltage was determined during the entirety of the first predefined period exhibits an increased charge loss that indicates a possible defect (¶[30] “On the other hand, when the minimum voltage battery is the same secondary battery 14 continuously NK times, the CPU 70 executes a preparation process for determining whether or not the minimum voltage battery is abnormal (S16 to S20)”, ¶[44] “it is possible to determine that an abnormality such as a micro-short circuit has occurred”);
wherein the checking process includes performing a second measurement process (S16-S20) and determining whether a second predefined period has elapsed since interruption or termination of the symmetrization process (¶[34] “Then, when the CPU 70 finishes discharging the reference battery DY, it starts the process of measuring the elapsed time T from the end of discharging the reference battery DY (S20: elapsed time measurement process)”),
Nakamura does not explicitly teach a first measurement process that runs over a first predefined period during the symmetrization process and in which measurements are performed repeatedly,
wherein, in each of the measurements, a battery cell that has a lowest quiescent voltage out of the at least two battery cells in a measurement is determined;
Nakamura does not teach in a case that the second predefined period has elapsed the method begins again by activating the symmetrization process and in a case that the second predefined period has not elapsed yet the second measurement process continues without reactivating the symmetrization process.
Pellenc teaches (see Fig. 4) a first measurement process that runs over a first predefined period (charging cycle) during the symmetrization process and in which measurements are performed repeatedly (¶[68] “a first half cycle comprising the consecutive execution of the following operations: successive reading of the voltages of the different cells”)
wherein, in each of the measurements, a battery cell that has a lowest quiescent voltage out of the at least two battery cells in a measurement is determined (¶[54] “detecting the cell 1 which is tardiest to charge”);
It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Nakamura to incorporate the teachings of Pellenc to provide a first measurement process that runs over a first predefined period during the symmetrization process and in which measurements are performed repeatedly,
wherein, in each of the measurements, a battery cell that has a lowest quiescent voltage out of the at least two battery cells in a measurement is determined;
in order to repeatedly determine which cell is the slowest to charge during one single charging cycle.
Nakamura in view of Pellenc does not teach in a case that the second predefined period has elapsed the method begins again by activating the symmetrization process and in a case that the second predefined period has not elapsed yet the second measurement process continues without reactivating the symmetrization process.
White teaches (Fig. 8) in a case that the second predefined period (update period in block 812) has elapsed (YES at block 812) the method begins again by activating the symmetrization process and in a case that the second predefined period has not elapsed yet (NO at block 812) the second measurement process continues without reactivating the symmetrization process (flowchart remains at 812) (¶[79] “At block 812 it is determined if the update period has expired. If the update period has not expired, the method 800 remains at block 812. When the update period has expired, the method 800 continues to block 814”).
It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Nakamura in view of Pellenc to incorporate the teachings of White to provide in a case that the second predefined period has elapsed the method begins again by activating the symmetrization process and in a case that the second predefined period has not elapsed yet the second measurement process continues without reactivating the symmetrization process in order to provide cell voltages an opportunity to stabilize before reactivating the symmetrization process.
Regarding Claim 15, the combination of Nakamura, Pellenc and White teaches the method according to claim 14.
Nakamura further teaches a measurement of the first measurement process is performed when a control unit that controls the battery wakes up (¶[24] “The abnormality determination sequence is executed by the CPU 70”), and waking of the control unit changes said control unit from a quiescent mode thereof to an active mode (¶[24] “Upon receiving notification of status information indicating charging from the ECU, the CPU 70 executes an abnormality determination sequence.”)
Regarding Claim 16, the combination of Nakamura, Pellenc and White teaches the method according to claim 15.
Nakamura further teaches after the control unit has woken up, first a measurement of the first measurement process is performed and only thereafter are the states of charge of the battery cells symmetrized (¶[25] “When starting the abnormality determination sequence, the CPU 70 starts a process of measuring the voltage V of each secondary battery 14”).
Regarding Claim 17, the combination of Nakamura, Pellenc and White teaches the method according to claim 14.
Nakamura further teaches wherein each performance of a measurement of the first measurement process contains:
measuring a quiescent voltage of all of the at least two battery cells contained in the battery (¶[27] “The CPU 70 Estimates the open circuit voltage of each secondary battery 14 from the voltage V measured at the end of charging (S6: acquisition process)”);
and ascertaining the lowest quiescent voltage out of the quiescent voltages measured at all of the at least two battery cells (¶[28] “The minimum battery that is the secondary battery 14 is detected (S10)”)
Regarding Claim 18, the combination of Nakamura, Pellenc and White teaches the method according to claim 14.
Nakamura further teaches after each performance of a measurement of the first measurement process, an identifier that characterizes the battery with the lowest quiescent voltage is entered into a history (¶[29] “Therefore, the CPU 70 detects the Nth secondary battery 14 as the minimum voltage battery and stores the detected number (in this case, N) of the secondary battery 14 in the memory 76”), the history contains identifiers of battery cells for which the lowest quiescent voltage has been determined, and it is established, based on identifiers entered in the history within a predefined first period, whether among the at least two battery cells there is a battery cell that had the lowest quiescent voltage during an entirety of the predefined first period and which battery cell that is (¶[30] “Further, the CPU 70 determines whether or not the minimum voltage battery is continuously the same secondary battery 14 based on the number of the secondary battery 14 stored in the memory 76 (S14).”)
Regarding Claim 22, the combination of Nakamura, Pellenc and White teaches the method according to claim 14,
Nakamura further teaches reporting an increased charge loss when an increased charge loss is established when the checking process is performed (¶[51] “when the target battery DX is determined to be abnormal in the abnormality determination sequence, the abnormality is notified, so that the user of the electric vehicle may take necessary measures such as replacement of the battery module 10”).
Regarding Claim 23, the combination of Nakamura, Pellenc and White teaches a battery system, comprising:
a battery having at least two battery cells (Nakamura 14) and a control unit (Nakamura 70) coupled to the battery cells, wherein the control unit is designed to carry out the method according to claim 14 (as explained above).
Regarding Claim 24, the combination of Nakamura, Pellenc and White teaches the battery system according to claim 23.
Nakamura further teaches the history that contains the identifiers of the battery cells for which a lowest quiescent voltage has been determined (¶[17] “The memory 76 also stores data necessary for executing the abnormality judgment sequence, such as specified values such as the specified voltage VK, the specified discharge voltage difference ΔVK, the specified elapsed time TK, the specified number of times NK, and the specified counter value CK”) is stored in the control unit (76, ¶[16] “the CPU 70 has a memory 76 such as a ROM or a RAM”).
Claim(s) 19-21 are rejected under 35 U.S.C. 103 as being unpatentable over Nakamura et al. (JP 2016075567 A) in view of Pellenc (US 20090039830 A1) further in view of White et al. (US 20140167780 A1) and further in view of Ohkawa et al. (US 20120175953 A1).
Regarding Claim 19, the combination of Nakamura, Pellenc and White teaches the method according to claim 14.
Nakamura further teaches the checking process (S16-S20) comprises:
a second measurement process runs over at most the second predefined period and in which one or more measurements are performed,
wherein, in each of the measurements, the following are respectively determined:
the lowest quiescent voltage U1 among the quiescent voltages of the battery cells, the battery cell at which the lowest quiescent voltage U1 has been determined, the second-lowest quiescent voltage U2 among the quiescent voltages of the at least two battery cells, (¶[33] “the CPU 70 first selects the minimum voltage battery as the target battery DX, and selects the maximum voltage battery as the reference battery DY (S16: selection process)”; In the case where there are only two cells, the highest cell is also the second-lowest cell)
and establishing an increased charge loss at the battery cell for which the lowest quiescent voltage was determined during the entirety of the first measurement process when the lowest quiescent voltage U1 has been measured at this battery cell (¶[44] “it is possible to determine that an abnormality such as a micro-short circuit has occurred”);
and wherein the second predefined period follows the first predefined period ((S2: detection process) followed by S16 to S20 (determining if the detected cell is abnormal)).
The combination of Nakamura, Pellenc and White does not teach and an average quiescent voltage Um, which corresponds to the average value of the quiescent voltages of all of the at least two battery cells.
Ohkawa teaches determining and an average quiescent voltage Um, which corresponds to the average value of the quiescent voltages of all of the at least two battery cells (¶[56] “the state of charge of each of the lithium cells is obtained by detecting the terminal voltages of the lithium cells, and then the deviation of the state of charge of each of the lithium cells is obtained. For the deviation, for example, the deviation of the state of charge of each of the lithium cells from the average state of charge of the lithium battery system may be used”)
It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Nakamura, Pellenc and White to incorporate the teachings of Ohkawa to provide an average quiescent voltage Um, which corresponds to the average value of the quiescent voltages of all of the at least two battery cells in order to improve the accuracy of detecting defective battery cells, as suggested by Ohkawa (¶[51]).
The combination of Nakamura, Pellenc, White, and Ohkawa teaches that the following equations hold true:
| U1 – U2| < US1 and | U1 – Um| < US2
wherein US1 and US2 each represent positive voltage threshold values, and US1 is less than or equal to US2;
(since US1 can equal US2, for any given values of U1, U2 and Um, a value of US1 equal to US2, may be arbitrarily selected to render the inequality true, therefore, Nakamura as modified discloses the claim)
Regarding Claim 20, the combination of Nakamura, Pellenc, White and Ohkawa teaches the method according to claim 19.
Nakamura further teaches each performance of a measurement of the second measurement process contains:
measuring the quiescent voltage of all of the at least two battery cells contained in the battery ¶[25] (“the CPU 70 starts a process of measuring the voltage V of each secondary battery 14”);
ascertaining the lowest quiescent voltage U1 and the second-lowest quiescent voltage U2 among the quiescent voltages measured at all of the at least two battery cells (¶[33] “the CPU 70 first selects the minimum voltage battery as the target battery DX, and selects the maximum voltage battery as the reference battery DY (S16: selection process)”; In the case where there are only two cells, the highest cell is also the second-lowest cell)
and determining the battery cell that has the lowest quiescent voltage U1 (¶[28] “it detects the minimum voltage battery, which is the secondary battery 14 with the smallest open circuit voltage”).
Ohkawa further teaches determining the average quiescent voltage Um using the quiescent voltages measured at all of the at least two battery cells (¶[56] “the state of charge of each of the lithium cells is obtained by detecting the terminal voltages of the lithium cells, and then the deviation of the state of charge of each of the lithium cells is obtained. For the deviation, for example, the deviation of the state of charge of each of the lithium cells from the average state of charge of the lithium battery system may be used”)
Regarding Claim 21, the combination of Nakamura, Pellenc, White and Ohkawa teaches the method according to claim 19.
Ohkawa further teaches wherein the symmetrization process is reactivated after an increased charge loss has been established or at the latest after the predefined second period has elapsed (¶[316] “Then in a step 1413, on the basis of the cause of occurrence of the anomaly signal, a decision is made as to whether normal operation should be continued” “CONTINUE OPERATION” at 1413 in Fig. 34).
Conclusion
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/A.B./Examiner, Art Unit 2859
/JULIAN D HUFFMAN/Supervisory Patent Examiner, Art Unit 2859