DETAILED ACTION
This Office action is in response to the Amendment filed on 05 September 2025 Claims 1, 2, and 4-15 are pending in the application. Claim 3 has been cancelled.
This application is a US National Stage Application under 35 USC 371 of PCT/EP2021/062851, filed 14 May 2021, which claims priority to German application 10 2020 113 237.9, filed on 15 May 2020.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Copies of the certified copies of Applicant’s priority document have been received in this National Stage application from the International Bureau (PCT Rule 17.2(a)).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 4-6, 8-10, and 12-15 are rejected under 35 U.S.C. 103 as being unpatentable over Kasai et al., US 2020/0043903, cited by Applicant on the Information Disclosure Statement submitted on 22 June 2022, in view of the article entitled “TIE 35: Transmittance of Optical Glasses”, both of record.
With respect to claim 1, Kasai et al. disclose a component 100, shown in Fig. 3, comprising:
an electrically insulating and radiation-transparent substrate 1 (see paragraph [0073]) and at least one semiconductor chip 11 arranged on the substrate 1 (see Fig. 3 and paragraph [0041]),
wherein: the at least one semiconductor chip 11 is designed to generate electromagnetic radiation and has a front side11c and a rear side 11d facing away from the front side 11c (see Fig. 3 and paragraphs [0041]-[0042]),
the front side 11c of the at least one semiconductor chip 11 faces the substrate 1 and is designed as a radiation exit surface of the at least one semiconductor chip 11 (see paragraph [0043]), and
the rear side 11d of the at least one semiconductor chip 11 faces away from the substrate 1, the at least one semiconductor chip 11 being electrically contactable externally via the rear side 11d (see Fig. 3 and paragraph [0042]).
Kasai et al. lack anticipation only of the substrate 1 having a transmittance of between 15% and 95% inclusive for visible light. In the component 100 of Kasai et al., the substrate is an optically transparent material, such as glass (see paragraph [0073]). The article entitled “TIE-35: Transmittance of Optical Glasses” discloses that optical glasses provide excellent transmittance throughout the total visible range from 400 to 800 nm (see the Introduction) and have a transmittance of between 15% and 95% inclusive for visible light, see Figs. 2-5, 3-2, 3-3, and 3-4. In light this article, it would have been obvious to the skilled artisan that the glass substrate 1 in the component 100 of Kasai et al. would have a transmittance of between 15% and 95% inclusive for visible light. This limitation is not deemed to patentably distinguish Applicant’s claimed component from the prior art component of Kasai et al.
With respect to claim 2, Kasai et al. teach that the substrate 1 is a glass panel, as shown in Figs.1-3.
With respect to claim 4, as shown in Figs. 1-3 of Kasai et al., the substrate 1 has a structured surface (with optical functional portions 1a) facing the at least one semiconductor chip 11, the transmittance of the substrate (9) being set by the structuring of the surface, see paragraphs [0093]-[0097].
With respect to claim 5, .in the component 100 of Kasai et al., the at least one semiconductor chip 11 has a converter layer 12 (see paragraph [0053]-[0054}) containing phosphors (see paragraphs [0055]-[0057]), the phosphors being designed to convert short-wave radiation components into long-wave radiation components (see paragraph [0057]), and the front side 11c of the at least one semiconductor chip 11 being formed by a surface of the converter layer (3), as shown in Fig. 3.
With respect to claim 6, in the component 100 of Kasai et al., the at least one semiconductor chip 11 has a semiconductor body with a first semiconductor layer of a first charge carrier type, with a second semiconductor layer of a second charge carrier type, and an active zone arranged between the first semiconductor layer and the second semiconductor layer (see paragraph [0047]), the at least one semiconductor chip 11 having a first contact layer 11b on the rear side 11d for electrically contacting the first semiconductor layer and a second contact layer 11b for electrically contacting the second semiconductor layer (see paragraph [0047]).
With respect to claim 8, the component 100 of Kasai et al. has at least one electrically insulating molded body 16, arranged on the substrate 1 and completely enclosing the at least one semiconductor chip 11 in lateral directions (see paragraph [0039]), as shown in Fig. 3.
With respect to claim 9, in the component 100 of Kasai et al., the at least one semiconductor chip 11 is separated from the at least one molded body 16 in the lateral directions by an intermediate region 15 and 14a, the intermediate region 15 and 14a being filled with an electrically insulating and/or radiation reflecting material (see paragraphs [0064]-[0067], and [0082]-[0087]), as shown in Fig. 3.
With respect to claim 10, the component 100 of Kasai et al. has at least one first bonding pad 24 and at least one second bonding pad 24, wherein each of the at least one first bonding pad 24 and the at least one second bonding pad 24 covers some regions of the at least one molded body 16 and the at least one semiconductor chip 11 when the substrate 1 is viewed from above, see Fig. 3.
With respect to claim 12, the component 100 of Kasai et al. comprises a plurality of radiation-emitting semiconductor chips 11 which are arranged side-by-side on the substrate 1, as shown in Fig. 3.
With respect to claim 13, Kasai et al. disclose a method for producing the component 100, shown in Fig. 3, as claimed in claim 1, in which:
the at least one semiconductor chip 11 is adhesively bonded to the substrate 1 (see paragraphs [0082]-[0087]),
the at least one semiconductor chip 11 is at least laterally encased with an electrically insulating material to form a molded body 16 (see paragraphs [0039] and [0098]-[0101]), and
bonding pads 24 are formed on the molded body 16 and on the rear side 11d of the at least one semiconductor chip 11, wherein each of the bonding pads 24 covers some regions of the molded body 16 and the at least one semiconductor chip 11 when the substrate 1 is viewed from above (see Fig. 3 and paragraph [0130]).
With respect to claim 14, in the method of Kasai et al., the bonding pads 24 are produced by means of planar electrical interconnect (see paragraph [0130]), as shown in Fig. 3.
With respect to claim 15, in the method of Kasai et al., the molded body 16 is formed by means of a forming process, in particular by means of a film-assisted forming process (see Fig. 10A and paragraphs [0100]-[0101] and [0127]-[0129]).
Claims 7 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Kasai et al., US 2020/0043903, in view of the article entitled “TIE 35: Transmittance of Optical Glasses”, as applied to claim 6 and 10 above, and further in view of Nishiuchi et al., US 2011/0297986.
Kasai et al. and the article entitled “TIE 35: Transmittance of Optical Glasses are applied as above. Although Kasai et al. disclose the structure of the at least one semiconductor chip 11 in paragraph [0047], Kasai et al. lack anticipation of the at least one semiconductor chip 11 having a via extending along a vertical direction through the first semiconductor layer and the active zone into the second semiconductor layer, wherein the via is designed for electrically contacting the second semiconductor layer and is electrically conductively connected to the second contact layer. Nishiuchi et al. disclose a semiconductor chip, shown in Figs. 1A and 2A, which comprises a stacked semiconductor body 10 that includes a first semiconductor layer 12 of a first conductivity type, a second semiconductor layer 11 of a second conductivity type, and a light emitting layer 13 provided between the first semiconductor layer 12 and the second semiconductor layer 11. As shown in Fig. 2A of Nishiuchi et al., a via extends along a vertical direction through the first semiconductor layer 12 and the active zone 13 into the second semiconductor layer 11, wherein the via is designed for electrically contacting the second semiconductor layer 11 and is electrically conductively connected (through the first conductive member 30a, shown in Fig. 2A) to a second contact layer 210a, as shown in Fig. 1A. Since Kasai et al. disclose that the semiconductor chip 11 is a flip-chip mounted light-emitting diode (see paragraph [0051]). In light of the flip-chip mounted light-emitting diode of Nishiuchi et al., it would have been obvious to the skilled artisan that in the known component 100 of Kasai et al., a via extending along a vertical direction through the first semiconductor layer and the active zone into the second semiconductor layer, wherein the via is designed for electrically contacting the second semiconductor layer and is electrically conductively connected to the second contact layer 11b, since this is necessary to make electrical contact between the second semiconductor layer and the second contact layer 11b.
With respect to claim 11, in paragraph [0170], Nishiuchi et al. disclose that the first connection member 230a and the second conductive member 230b can be a solder material, see paragraphs [0050] and [0170]. Therefore, in light of this teaching of Nishiuchi et al., it would have been obvious to the skilled artisan that in the component 100 of Kasai et al., at least one solder ball could be arranged on each of the at least one first bonding pad 24 and the at least one second bonding pad 24, each solder ball being designed to create a mechanical and electrical connection of the component to a target mounting surface and at a same time to compensate for height differences on a rear side 11d of the component 100.
Response to Arguments
Applicant's arguments filed 05 September 2025 have been fully considered but they are not persuasive. Independent claim 1 has been amended to require the substrate to have a transmittance of between 15% and 95% inclusive for visible light. Applicant has argued that the article “TIE 35: Transmittance of Optical Glasses” specifically discloses optical glasses that have a transmittance higher than 99%, and does not disclose or suggest a transmittance between 15% and 95% inclusive. However, the article entitled “TIE-35: Transmittance of Optical Glasses” discloses that optical glasses provide excellent transmittance throughout the total visible range from 400 to 800 nm (see the Introduction) and have a transmittance of between 15% and 95% inclusive for visible light, see Figs. 2-3, 2-5, 3-2, 3-3, and 3-4. For example, in Table 2-3 on page5 of the article, it is disclosed that for a wavelength of 500 nm, a 25 nm thick N-SF57 glass panel has a transmittance of 93%. Similarly, Fig. 2-5 shows glasses having a transmittance of less than 95%. Fig. 3-2 of the article also shows glasses having a transmittance of between 15% and 95% inclusive for visible light. The article clearly shows that glass panels having a transmittance of between 15% and 95% inclusive for visible light are readily available in the art, as clearly shown in Figs. 2-3, 2-5, 3-2, 3-3, and 3-4 of the article. Since Kasai et al. teach a glass substrate 1, it would have been obvious to the skilled artisan that the glass substrate 1 in the component 100 of Kasai et al. would have a transmittance of between 15% and 95% inclusive for visible light. In light of this article, this limitation is not deemed to patentably distinguish Applicant’s claimed component from the prior art component of Kasai et al.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The additionally cited references disclose various components which include light emitting devices, having substrates with having a transmittance of between 15% and 95% inclusive for visible light.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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MARY A. WILCZEWSKI
Primary Examiner
Art Unit 2898
/MARY A WILCZEWSKI/Primary Examiner, Art Unit 2898