DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
This Office Action is in response to Applicant’s Amendment filed on January 16, 2026. Claims 1-3 have been amended. No new claims have been added. No claims have been canceled. Currently, claims 1-13 are pending.
Applicant’s amendment to claim 1 successfully overcomes the objection to claim 1 set forth in the previous Office Action.
Applicant’s amendment to claims 2-3 successfully overcomes the 112(b) rejection of claims 2-3 set forth in the previous Office Action.
Response to Arguments
Applicant's arguments filed on January 16, 2026 have been fully considered but they are not persuasive. The Applicant argues that prior art does not teach the newly added claim limitation, “.. gate electrodes are in contact with the side walls of the trenches without extending into the mesa-shaped portions of the n-type semiconductor layer” which is not persuasive since the Applicant fails to define the mesa-shaped portions as having straight ideal sidewalls without any undercuts, notches or other imperfections. Under a broad reasonable interpretation Yu’s Figure 19 teaches a structure that reads on the newly added claim limitation. Specifically, the mesas in this embodiment have irregularities on the sidewalls. Consequently, the gate electrode while in contact with the sidewalls of the trench is confined to the space defined by the irregularity and does not encroach upon or extend into the main body of the mesa portion. Furthermore, Yu’s Figure 12 discloses another embodiment that, when interpreting the mesa-shaped portions as having straight sidewalls, shows gate electrodes (e.g., 146/148) that do not extend into the mesas. The p-type diffusion 140 is not considered as part of gate electrode, allowing the gate structure 146/148 to meet the limitation of being confined to the trench sidewalls without encroaching into the mesa portion.
Claim Objections
Claim 2 is objected to because of the following informalities: “gate electrodes comprises NiO” should read “gate electrodes comprise NiO”. Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 5 and 10-13 are rejected under 35 U.S.C. 103 as being unpatentable over Yu et al. (US 7,262,461 B1; hereafter Yu) in view of Li et al., ("Single and multi-fin normally-off Ga2O3 vertical transistors with a breakdown voltage over 2.6 kV," 2019 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, USA, 2019, pp. 12.4.1-12.4.4, doi: 10.1109/IEDM19573.2019.8993526; hereafter Li, Date of Conference 07-11 December 2019) and Bencuya et al. (4,566,172; hereafter Bencuya).
Regarding claim 1, Yu teaches a trench-type MESFET (see e.g., MESFET device 250, Figure 19), comprising:
an n-type layer (see e.g., n-type substrate 100a, Col. 8, Line 54, Figure 19) and comprising a plurality of trenches opening on one surface, the plurality of trenches having side walls (see e.g., trenches with sidewalls formed in the n-type substrate 100a as shown in modified Figure 19 and are filled with oxide 108 and gate layer 170, Col. 8, Lines 65-67, Figure 19);
first insulators respectively buried in bottom portions of the plurality of trenches (see e.g., oxide 108b buried in bottom portions of the trench, Col. 9, Lines 25-27, Figure 19);
mesa-shaped portions between the adjacent trenches of the plurality of trenches; (see e.g., the mesa-shaped portions of n-type substrate 100a between the adjacent trenches, Figure 19)
gate electrodes respectively buried in the plurality of trenches so as to be placed on the first insulators (see e.g., gate layer of platinum silicide 170 formed on the oxide 108b, Col. 8, Lines 65-67, Figure 19) and so that the entirety of the side surfaces of the gate electrodes are in contact with the side walls of the trenches without extending into the mesa-shaped portions of the n-type semiconductor layer (see e.g., the entirety of the side surfaces of the gate layer 170 is in contact with the sidewalls of the trenches formed in the n-type substrate 100a as shown in Figure 19, Examiner’s interpretation: the mesa-shaped portions have irregularities on its sidewalls. Yu’s Figure 12 discloses another embodiment that, when interpreting the mesa-shaped portions as having straight sidewalls, shows gate electrodes (e.g., 146/148) that do not extend into the mesas. The p-type diffusion 140 is not considered as part of gate electrode, allowing the gate structure 146/148 to meet the limitation of being confined to the trench sidewalls without encroaching into the mesa portion);
second insulators respectively buried in the plurality of trenches (see e.g., oxide 108c disposed in the trenches, Col. 9, Lines 17-18, Figure 19) on the gate electrodes (see e.g., the oxide 108c is placed on the gate layer 170, Col. 9, Lines 17-18, Figure 19); to insulate the gate electrodes and the source; and (see e.g., oxide 108c disposed in the trenches and placed over the gate layer 170 insulates the gate layer 170 and the
n
+
source regions SOURCE, Figure 19)
a drain directly or indirectly connected to the n-type semiconductor layer on a side opposite to the source (see e.g.,
n
+
type layer 100b forms the drain of the MESFET and
n
+
type layer 106, opposite to the drain, forms the source of the MESFET, Col. 9, Lines 20-25, Figure 19),
wherein the n-type semiconductor layer comprises a withstand voltage layer located between the bottoms of the trenches and a bottom surface of the n-type semiconductor layer (see e.g., the portion of the n-type substrate 100a between the bottom of the trenches and the bottom surface of the n-type substrate 100a, Figure 19), a channel layer located above the bottoms of the trenches and being in contact with the side surfaces of the gate electrodes (see e.g., portion of the n-type substrate 100a above the bottoms of the trenches and in contact with the side surfaces of the gate layer 170, Figure 19), and a contact layer (see e.g.,
n
+
source regions SOURCE, Figure 19).
Yu does not explicitly teach
“n-type semiconductor layer comprising a
G
a
2
O
3
-based single crystal”
In a similar field of endeavor Li teaches
n-type semiconductor layer comprising a
G
a
2
O
3
-based single crystal (see e.g., a 10-µm n--Ga2O3 drift layer grown on a (001) n+-Ga2O3 substrate, Device Design and Fabrication, Figure 1)
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Li’s teachings of n-type semiconductor layer comprising a
G
a
2
O
3
-based single crystal in the device of Yu since gallium oxide has an ultra-wide bandgap which allows for operation at high voltages, temperatures, and frequencies.
Yu does not explicitly teach
“a source electrode connected to the mesa-shaped portions;
second insulators…. to insulate the gate electrodes and the source electrode;
a drain electrode directly or indirectly connected to the n-type semiconductor layer on a side opposite to the source electrode,
a contact layer provided between an upper end of the channel layer and the source electrode to provide an ohmic connection between the source electrode and the n-type semiconductor layer”
In a similar field of endeavor Bencuya teaches
a source electrode connected to the mesa-shaped portions (see e.g., metal contact member 45 overlies the active area of the device. The metal contact member 45 is in ohmic contact with the N-type regions 12 of ridges 21 and is supported on the surface of the filler material 40 between the ridges, Col 6, Lines 15-26, Figure 8);
second insulators…. to insulate the gate electrodes and the source electrode (see e.g., the filler material 40 isolates the gate contact 35 from the metal contact member 45, Figure 8);
a drain electrode directly or indirectly connected to the n-type semiconductor layer on a side opposite to the source electrode (see e.g., metal layer 46 serves as the drain contact and is connected to the N-type layer 11, Col. 6, Lines 27-40, Figure 8),
a contact layer provided between an upper end of the channel layer and the source electrode to provide an ohmic connection between the source electrode and the n-type semiconductor layer (see e.g., N-type regions 12 of the ridges 21 provided between the upper end of channel 31and the metal contact member 45. The metal contact member 45 is in ohmic contact with the N-type regions 12, Col 6, Lines 15-26, Figure 8).
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Bencuya’s teachings of a source electrode connected to the mesa-shaped portions; second insulators…. to insulate the gate electrodes and the source electrode; a drain electrode directly or indirectly connected to the n-type semiconductor layer on a side opposite to the source electrode, a contact layer provided between an upper end of the channel layer and the source electrode to provide an ohmic connection between the source electrode and the n-type semiconductor layer in the device of Yu in order to provide electrical connections to external circuitry and support the basic operation of a transistor.
Regarding claim 5, Yu, as modified by Li and Bencuya, teaches the limitations of claim 1 as mentioned above. Yu further teaches
wherein a thickness of the first insulator is in a range of not less than 50 nm and not more than 300 nm (see e.g., about 3000 angstroms (300nm) of oxide 108b is filled in the bottom of the trenches, Col. 6, Lines 40-46, Figure 6).
Regarding claim 10, Yu, as modified by Li and Bencuya, teaches the limitations of claim 1 as mentioned above. Yu does not explicitly teach
“wherein the n-type semiconductor layer is stacked on an n-type semiconductor substrate that is formed of an n-type Ga203-based single crystal, and wherein the drain electrode is connected to a bottom surface of the n-type semiconductor substrate on opposite side to the n-type semiconductor layer”.
In a similar field of endeavor Li teaches
wherein the n-type semiconductor layer is stacked on an n-type semiconductor substrate that is formed of an n-type Ga203-based single crystal (see e.g., a 10-µm n--Ga2O3 drift layer grown on a (001) n+-Ga2O3 substrate, device Design and Fabrication, Figure 1) and wherein the drain electrode is connected to a bottom surface of the n-type semiconductor substrate on opposite side to the n-type semiconductor layer (see e.g., the drain electrode is connected to a bottom surface of the n+-Ga2O3 substrate on opposite side of the n--Ga2O3 drift layer).
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Li’s teachings of wherein the n-type semiconductor layer is stacked on an n-type semiconductor substrate that is formed of an n-type Ga203-based single crystal, and wherein the drain electrode is connected to a bottom surface of the n-type semiconductor substrate on opposite side to the n-type semiconductor layer to form a high performance Ga2O3 vertical transistor.
Regarding claim 11, Yu, as modified by Li and Bencuya, teaches the limitations of claim 10 as mentioned above. Yu does not explicitly teach
“wherein a plane orientation of the n- type semiconductor substrate on which the n-type semiconductor layer is formed is a (001) plane or a (011) plane”.
In a similar field of endeavor Li teaches
wherein a plane orientation of the n- type semiconductor substrate on which the n-type semiconductor layer is formed is a (001) plane or a (011) plane (see e.g., the n+-Ga2O3 substrate is (001) plane, Device Design and Fabrication, Figure 1).
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Li’s teachings of wherein a plane orientation of the n- type semiconductor substrate on which the n-type semiconductor layer is formed is a (001) plane or a (011) plane in the device of Yu to provide high performance Ga2O3 device.
Regarding claim 12, Yu, as modified by Lin and Bencuya, teaches the limitations of claim 1 as mentioned above. Yu does not explicitly teach
“wherein the source electrode connected to the mesa-shaped portion is a single source electrode that extends across the plurality of trenches”.
In a similar field of endeavor Bencuya teaches
wherein the source electrode connected to the mesa-shaped portion is a single source electrode that extends across the plurality of trenches (see e.g., metal contact member 45 overlies the active area of the device. The metal contact member 45 is in ohmic contact with the N-type regions 12 of ridges 21 and is supported on the surface of the filler material 40 between the ridges, Col 6, Lines 15-26, Figure 8).
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Bencuya’s teachings of wherein the source electrode connected to the mesa-shaped portion is a single source electrode that extends across the plurality of trenches in the device of Yu in order to provide electrical connections to external circuitry and support the basic operation of a transistor.
Regarding claim 13, Yu, as modified by Lin and Bencuya, teaches the limitations of claim 1 as mentioned above. Yu does not explicitly teach
“wherein the second insulators are in contact with the source electrode and the entirety of each second insulator is respectively buried in the plurality of trenches to insulate the gate electrodes and the source electrode”.
In a similar field of endeavor Bencuya teaches
wherein the second insulators are in contact with the source electrode and the entirety of each second insulator is respectively buried in the plurality of trenches to insulate the gate electrodes and the source electrode (see e.g., metal contact member 45 overlies the active area of the device. The metal contact member 45 is in ohmic contact with the N-type regions 12 of ridges 21 and is supported on the surface of the filler material 40 which are buried in the plurality of trenches between the ridges 21, Col 6, Lines 15-26, Figure 8).
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Bencuya’s teachings of wherein the second insulators are in contact with the source electrode and the entirety of each second insulator is respectively buried in the plurality of trenches to insulate the gate electrodes and the source electrode in the device of Yu in order to provide electrical connections to external circuitry and support the basic operation of a transistor.
Claims 4, 6, 7 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Yu et al. (US 7,262,461 B1; hereafter Yu) in view of Li et al., ("Single and multi-fin normally-off Ga2O3 vertical transistors with a breakdown voltage over 2.6 kV," 2019 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, USA, 2019, pp. 12.4.1-12.4.4, doi: 10.1109/IEDM19573.2019.8993526; hereafter Li, Date of Conference 07-11 December 2019), Bencuya et al. (4,566,172; hereafter Bencuya) and further in view of Siergiej et al. (US 5,945,701 A1; hereafter Siergiej).
Regarding claim 4, Yu, as modified by Li and Bencuya, teaches the limitations of claim 1 as mentioned above. Yu does not explicitly teach
“wherein a donor concentration in a region of the n-type semiconductor layer between a bottom of the trench and a bottom surface of the n-type semiconductor layer is not more than
7
x
10
16
c
m
-
3
”.
"[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955). Furthermore, "[i]t is a settled principle of law that a mere carrying forward of an original patented conception involving only change of form, proportions, or degree, or the substitution of equivalents doing the same thing as the original invention, by substantially the same means, is not such an invention as will sustain a patent, even though the changes of the kind may produce better results than prior inventions." In re Williams, 36 F.2d 436, 438 (CCPA 1929).
In a similar field of endeavor Siergiej teaches
wherein a donor concentration in a region of the n-type semiconductor layer between a bottom of the trench and a bottom surface of the n-type semiconductor layer is not more than
7
x
10
16
c
m
-
3
(see e.g., the doping level in the drift layer 38 may be in the order of 1.times.10.sup.16 cm.sup.-3 or 1 to 5.times.10.sup.15 cm.sup.-3, Figures 9-11).
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Siergiej’s teachings of a donor concentration in a region of the n-type semiconductor layer between a bottom of the trench and a bottom surface of the n-type semiconductor layer is not more than
7
x
10
16
c
m
-
3
in the device of Yu in order yield desirable I.sub.max, low values of V.sub.GS for V.sub.max, and desirable transconductance and voltage gain.
Regarding claim 6, Yu, as modified by Li and Bencuya, teaches the limitations of claim 1 as mentioned above. Yu does not explicitly teach
“wherein a donor concentration in the channel layer is more than 5x1015cm-3 and not more than 1x1016 cm-3”.
"[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955). Furthermore, "[i]t is a settled principle of law that a mere carrying forward of an original patented conception involving only change of form, proportions, or degree, or the substitution of equivalents doing the same thing as the original invention, by substantially the same means, is not such an invention as will sustain a patent, even though the changes of the kind may produce better results than prior inventions." In re Williams, 36 F.2d 436, 438 (CCPA 1929).
In a similar field of endeavor Siergiej teaches
wherein a donor concentration in the channel layer is more than 5x1015cm-3 and not more than 1x1016 cm-3 (see e.g., the doping in the channel region 36 is maintained at 1.times.10.sup.16 cm.sup.-3, Figures 9-11).
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Siergiej’s teachings of wherein a donor concentration in the channel layer is more than 5x1015cm-3 and not more than 1x1016 cm-3 in the device of Yu in order yield desirable I.sub.max, low values of V.sub.GS for V.sub.max, and desirable transconductance and voltage gain.
Regarding claim 7, Yu, as modified by Li and Bencuya, teaches the limitations of claim 1 as mentioned above. Yu does not explicitly teach
“wherein Schottky Barriers are formed at interfaces between the channel layer and the side surfaces of the gate electrodes”.
In a similar field of endeavor Siergiej teaches
wherein Schottky Barriers are formed at interfaces between the channel layer and the side surfaces of the gate electrodes (see e.g., Schottky barrier formed between the channel layer 36 and the gate 22, Col. 2, Lines 11-15, Figures 1 and 12)
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Siergiej’s teachings of wherein Schottky Barriers are formed at interfaces between the channel layer and the side surfaces of the gate electrodes in the device of Yu in order to control the channel’s conductivity.
Regarding claim 9, Yu, as modified by Li, Bencuya and Siergiej, teaches the limitations of claim 7 as mentioned above. Yu does not explicitly teach
“wherein a donor concentration in the channel layer is more than 5x1015cm-3 and not more than 1x1016 cm-3”.
"[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955). Furthermore, "[i]t is a settled principle of law that a mere carrying forward of an original patented conception involving only change of form, proportions, or degree, or the substitution of equivalents doing the same thing as the original invention, by substantially the same means, is not such an invention as will sustain a patent, even though the changes of the kind may produce better results than prior inventions." In re Williams, 36 F.2d 436, 438 (CCPA 1929).
In a similar field of endeavor Siergiej teaches
wherein a donor concentration in the channel layer is more than 5x1015cm-3 and not more than 1x1016 cm-3 (see e.g., the doping in the channel region 36 is maintained at 1.times.10.sup.16 cm.sup.-3, Figures 9-11).
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Siergiej’s teachings of wherein a donor concentration in the channel layer is more than 5x1015cm-3 and not more than 1x1016 cm-3 in the device of Yu in order yield desirable I.sub.max, low values of V.sub.GS for V.sub.max, and desirable transconductance and voltage gain.
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Yu et al. (US 7,262,461 B1; hereafter Yu) in view of Li et al., ("Single and multi-fin normally-off Ga2O3 vertical transistors with a breakdown voltage over 2.6 kV," 2019 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, USA, 2019, pp. 12.4.1-12.4.4, doi: 10.1109/IEDM19573.2019.8993526; hereafter Li, Date of Conference 07-11 December 2019), Bencuya et al. (4,566,172; hereafter Bencuya) and further in view of Lalinský,et al. (AlGaN/GaN high electron mobility transistors with nickel oxide based gates formed by high temperature oxidation. Applied Physics Letters 2012. 100. 10.1063/1.3690047; hereafter Lalinsky).
Regarding claim 2, Yu, as modified by Li and Bencuya, teaches the limitations of claim 1 as mentioned above. Yu does not explicitly teach
“wherein the gate electrodes comprises NiO”.
In a similar field of endeavor Lalinsky teaches
wherein the gate electrodes comprises NiO (see e.g., nickel oxide (NiO) as the gate interfacial layer of the transistor shown in Figure 1).
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Lalinsky’s teachings of gate electrodes comprises NiO in the device of Yu since NiO gate contact layers show an excellent dc performance with higher peak transconductance, larger gate voltage swing.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Yu et al. (US 7,262,461 B1; hereafter Yu) in view of Li et al., ("Single and multi-fin normally-off Ga2O3 vertical transistors with a breakdown voltage over 2.6 kV," 2019 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, USA, 2019, pp. 12.4.1-12.4.4, doi: 10.1109/IEDM19573.2019.8993526; hereafter Li, Date of Conference 07-11 December 2019), Bencuya et al. (4,566,172; hereafter Bencuya) and Siergiej et al. (US 5,945,701 A1; hereafter Siergiej) and further in view of Lalinský,et al. (AlGaN/GaN high electron mobility transistors with nickel oxide based gates formed by high temperature oxidation. Applied Physics Letters 2012. 100. 10.1063/1.3690047; hereafter Lalinsky).
Regarding claim 8, Yu, as modified by Li, Bencuya and Siergiej, teaches the limitations of claim 7 as mentioned above. Yu does not explicitly teach
“wherein the gate electrodes are formed of NiO”.
In a similar field of endeavor Lalinsky teaches
wherein the gate electrodes are formed of NiO (see e.g., nickel oxide (NiO) as the gate interfacial layer of the transistor shown in Figure 1).
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Lalinsky’s teachings of wherein the gate electrodes are formed of NiO in the device of Yu since NiO gate contact layers show an excellent dc performance with higher peak transconductance, larger gate voltage swing.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Yu et al. (US 7,262,461 B1; hereafter Yu) in view of Li et al., ("Single and multi-fin normally-off Ga2O3 vertical transistors with a breakdown voltage over 2.6 kV," 2019 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, USA, 2019, pp. 12.4.1-12.4.4, doi: 10.1109/IEDM19573.2019.8993526; hereafter Li, Date of Conference 07-11 December 2019), Bencuya et al. (4,566,172; hereafter Bencuya) and further in view of Baba et al. (US 2018/0097102 A1; hereafter Baba).
Regarding claim 3, Yu, as modified by Li and Bencuya, teaches the limitations of claim 1 as mentioned above. Yu does not explicitly teach
“wherein a curvature radius at an apex of a curve at an edge of a bottom portion of the gate electrodes in a cross section in a width direction of the trench is not less than 0.1 µm”.
"[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955). Furthermore, "[i]t is a settled principle of law that a mere carrying forward of an original patented conception involving only change of form, proportions, or degree, or the substitution of equivalents doing the same thing as the original invention, by substantially the same means, is not such an invention as will sustain a patent, even though the changes of the kind may produce better results than prior inventions." In re Williams, 36 F.2d 436, 438 (CCPA 1929).
In a similar field of endeavor Baba teaches
wherein a curvature radius at an apex of a curve at an edge of a bottom portion of the gate electrodes in a cross section in a width direction of the trench is not less than 0.1 µm (see e.g., The trench has a rounded shape with a radius of curvature R1 and an opening width D. The gate electrode 22 has a rounded shape with a radius of curvature R2. R1 meets the expression D/10≦R1≦D/2 and R2≦R1. The opening width D of the trench T is in the range of 2μm to 1.5μm therefore, R2=R1 will be greater than or equal to 0.2μm to 0.15μm, Paras [0044] - [0046], Figure 2).
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Baba’s teachings of a curvature radius at an apex of a curve at an edge of a bottom portion of the gate electrodes in a cross section in a width direction of the trench is not less than 0.1 µm in the device of Yu so that the capacitance between the gate electrode and the n-type layer in the bottom part of the trench is reduced, whereby the gate-drain capacitance can be reduced. In addition, with this structure, the change in sectional geometry of the gate electrode is made gradual, whereby an electric field concentration in the corners is difficult to be generated. Thereby, the breakdown voltage can be further increased.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/FAKEHA SEHAR/Examiner, Art Unit 2893 /YARA B GREEN/Supervisor Patent Examiner, Art Unit 2893