Prosecution Insights
Last updated: October 02, 2026
Application No. 17/789,429

DISPLAY SUBSTRATE AND DISPLAY APPARATUS

Non-Final OA §102§103
Filed
Jun 27, 2022
Priority
Oct 21, 2020 — CN 202011132725.8 +1 more
Examiner
KIM, JAHAE
Art Unit
2897
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
BOE Technology Group Co., Ltd.
OA Round
3 (Non-Final)
73%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
92%
With Interview

Examiner Intelligence

Grants 73% — above average
73%
Career Allowance Rate
35 granted / 48 resolved
+4.9% vs TC avg
Strong +19% interview lift
Without
With
+18.8%
Interview Lift
resolved cases with interview
Typical timeline
3y 6m
Avg Prosecution
22 currently pending
Career history
75
Total Applications
across all art units

Statute-Specific Performance

§103
52.8%
+12.8% vs TC avg
§102
16.0%
-24.0% vs TC avg
§112
28.3%
-11.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 48 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Response to Amendment The amendment filed on 08/18/2025 has been entered. Claims 1, 9, and 14 have been amended. Claims 4-6 and 16 are withdrawn under 37 CFR 1.142(b) as being directed to a nonelected invention. Applicant’s amendments to the claim are noted. Therefore, claims 1-3, 7-15, and 17 have been fully considered in examination. Response to Arguments Applicant's arguments filed on 8/18/2025 have been fully considered but they are not persuasive. Regarding the arguments on pages 8-16, Yoon (US20220077242A1) teaches the buffer layer of the at least one base has a one first opening provided at a position of the buffer layer corresponding to the island region, and the first opening is in the bridge regions and is not in the clearance regions (Para [0273], upper surface 100cUS of the second base layer 100 c may be exposed at (e.g., in or on) the first auxiliary area AA1). Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claim 1 is rejected under 35 U.S.C. 102(a)(1)/102(a)(2) as being anticipated by Yoon (US20220077242A1). Regarding claim 1, Yoon teaches a display substrate having a plurality of island regions (Fig. 12, first extension area LA1), bridge regions (Fig. 12, intermediate display area MDA) and clearance regions (Fig. 12, second through portion PNP2), the bridge regions being disposed around the island regions (Para [0120], intermediate display area MDA may be arranged between the front display area FDA and the corner display area CDA.), the display substrate comprising: at least one base, each of the at least one base comprising a sub-base (Fig. 12, substrate 100) and a buffer layer (Fig. 12, buffer layer 111), wherein the sub-base comprises a first surface and a second surface opposite to each other, and the buffer layer is disposed on a side of the second surface of the sub-base away from the first surface (Para [0165-0167] & Fig. 12, upper surface 100cUS of the second base layer 100c); and in the at least one base, the sub-base of any base has a same orientation (Para [0168] & Fig. 12); a plurality of sub-pixels (Fig. 12, pixel circuit layer PCL) on a side of the buffer layer of an outermost base of the at least one base away from the sub-base of the outermost base, each sub- pixel comprising a light-emitting device and a pixel circuit, wherein each island region is provided with at least one of the sub-pixels (Para [0169-0171]); and a plurality of signal lines connected to the pixel circuit (Para [0094], driving circuit providing an electrical signal), wherein the plurality of signal lines are distributed in the bridge regions (intermediate display area MDA); wherein the buffer layer of the at least one base has a one first opening provided at a position of the buffer layer corresponding to the island region, and the first opening is in the bridge regions and is not in the clearance regions (Para [0273], upper surface 100cUS of the second base layer 100 c may be exposed at (e.g., in or on) the first auxiliary area AA1). PNG media_image1.png 607 921 media_image1.png Greyscale Claim(s) 1-3 and 7-8 is/are rejected under 35 U.S.C. 102(a)(1)/102(a)(2) as being anticipated by Hong (US20180052493A1). Regarding claim 1, Hong teaches a display substrate having a plurality of island regions (Fig. 4, island 112), bridge regions (Fig. 4, bridge region1 14) and clearance regions (Fig. 4, peripheral area PA), the bridge regions being disposed around the island regions, the display substrate comprising: at least one base, each of the at least one base comprising a sub-base (Fig. 11, carrier substrate 140) and a buffer layer (Fig. 11, substrate 120), wherein the sub-base comprises a first surface and a second surface opposite to each other, and the buffer layer is disposed on a side of the second surface of the sub-base away from the first surface (Fig. 11 & Para [0085], substrate 120 fixed to the carrier substrate 140); and in the at least one base, the sub-base of any base has a same orientation (Fig. 11); a plurality of sub-pixels (Fig. 4, pixel 111) on a side of the buffer layer of an outermost base of the at least one base away from the sub-base of the outermost base, each sub- pixel comprising a light-emitting device and a pixel circuit, wherein each island region is provided with at least one of the sub-pixels (Para [0054], pixel 111 is disposed in each of the island 112); and a plurality of signal lines connected to the pixel circuit, wherein the plurality of signal lines are distributed in the bridge regions (Para [0055], pixels 111 disposed in the islands 112 can be driven by receiving power and electrical signals through the wires disposed in the bridge 114); wherein the buffer layer of the at least one base has a one first opening (Fig. 11, opening 116) provided at a position of the buffer layer corresponding to the island region, and the first opening is in the bridge regions and is not in the clearance regions (Fig. 11, opening 116 is in the bridge region 114 but not in the peripheral area PA). Regarding claim 2, Hong teaches the display substrate according to claim 1, wherein the first opening comprises a plurality of first sub-openings (Fig. 4, dumbbell-shaped) and a plurality of second sub- openings (Fig. 4, dumbbell-shaped) arranged at intervals along a first direction (Para [0080]), and wherein an extending direction of the plurality of first sub-openings intersects with an extending direction of the plurality of second sub-openings (Fig. 4). Regarding claim 3, Hong teaches the display substrate according to claim 2, wherein the plurality of first sub-openings are connected to the plurality of second sub-openings to form the first opening, and the first opening has a first side and a second side opposite to each other in the first direction (Fig. 4 & Para [0062]), the first side has a plurality of first peaks and a plurality of first valleys; and the second side has a plurality of second peaks and a plurality of second valleys (Fig. 4 &Para [0062]), wherein the first peaks and the second valleys are arranged in one-to-one correspondence, and the second peaks and the first valleys are arranged in one- to-one correspondence (Fig. 4 & Para [0062]), and any one of the first peaks is close to a second valley between two second peaks on two sides of the first peak, with respect to a connection line between the two second peaks (Fig. 4 & Para [0062]). PNG media_image2.png 516 560 media_image2.png Greyscale Regarding claim 7, Hong teaches the display substrate according to claim 1, wherein the pixel circuits comprise a plurality of transistors (TFT), and orthographic projections of the plurality of transistors on the buffer layer do not overlap the first opening (Fig. 11 & Para [0085], transistors formed on the substrate 120 between the first opening and the second opening). Regarding claim 8, Hong teaches the display substrate according to any one of claim 1, wherein the first opening penetrates a corresponding buffer layer (Fig. 11 & Para [0087], opening 116 extend not only through the insulating layers 130 but also through the substrate 120, so that the carrier substrate 140 may be exposed). Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 9-12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hong (US20180052493A1) as applied to claim 1 above, and further in view of Zhao (US20220285464A1). Regarding claim 9, Hong teaches the display substrate according to claim 1 respectively, but does not teach at least one inorganic film layer laminated with the buffer layer of the outermost base of the at least one base, wherein the at least one inorganic film layer has a second opening provided at a position of the at least one inorganic film layer corresponding to the island region. However, Zhao teaches at least one inorganic film layer laminated with the buffer layer of the outermost base of the at least one base (Fig. 9 & Para [0059], encapsulation layer 012 may be a single-layer or multi-layer structure formed from an inorganic compound), wherein the at least one inorganic film layer has at least one second opening provided at a position of the at least one inorganic film layer corresponding to the island region (Para [0057], at least one groove W). It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the invention, to modify a display panel of Hong (US20180052493A1) and further integrating the alternative structure of display panel disclosed by Zhao (US20220285464A1). The combination of these familiar elements can lower the probability of cracking in the display panel by reducing stress, as described in paragraph [0051] of Zhao. Regarding claim 10, Hong in view of Zhao teaches the display substrate according to claim 9, wherein an orthographic projection of the second opening on the buffer layer has an overlap region with the first opening (Fig. 9 & Para [0087], grooves W are on the surface of the encapsulation layer 012 distal from the display film layer, wherein the orthographic projections of the three grooves W on the base substrate 1). Regarding claim 11, Hong in view of Zhao teaches the display substrate according to claim 10, wherein the second opening and the first opening are provided in one-to-one correspondence, and have a same shape (Para [0057], base layer 011 and the encapsulation layer 012 are in a rectangular shape). Regarding claim 12, Hong in view of Zhao teaches the display substrate according to claim 10, wherein the second opening penetrates a corresponding inorganic film layer (Fig. 8 & Para [0087], at least one groove W is on a surface of the encapsulation layer 01). Claim(s) 13-15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hong (US20180052493A1) as applied to claim 1 above, and further in view of Ebisuno (US20250143082A1). Regarding claim 13, Hong teaches the display substrate according to claim 1 respectively, but does not teach the sub- base of any one of the at least one base is a flexible base; the at least one base comprises a first base and a second base, the first base comprises a first sub-base and a first buffer layer, and the second base comprises a second sub-base and a second buffer layer; and wherein a thickness of the second sub-base is 40% to 60% of a thickness of the first sub-base. However, Ebisuno teaches the sub- base of any one of the at least one base is a flexible base (Para [0075]); the at least one base comprises a first base (Fig. 9, second base layer 105 and third barrier layer 106) and a second base (Fig. 9, first base layer 101 and second barrier layer 104), the first base comprises a first sub-base (Fig. 9, second base layer 105) and a first buffer layer (Fig. 9, third barrier layer 106), and the second base comprises a second sub-base (Fig. 9. first base layer 101) and a second buffer layer (Fig. 9, second barrier layer 104); and Wherein a thickness of the second sub-base is 40% to 60% of a thickness of the first sub-base (Para [0203]). It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the invention, to modify a display panel of Hong (US20180052493A1) and further integrating the alternative structure of display substrate disclosed by Ebisuno (US20250143082A1). The combination of these familiar elements can reduce infiltration of a foreign material, moisture, and/or ambient air from below the substrate 100 and may provide a flat surface on the substrate, as described in paragraph [00157] of Ebisuno. Regarding claim 14, Hong teaches the display substrate according to claim 1, wherein each of the at least one base has corner regions, and the island regions, the bridge regions and the clearance regions are provided in only the corner regions (Fig. 4, opening 116 surround the pixels 111 and islands 112), But does not specify the base is a rigid base. However, Ebisuno teaches the base is a rigid base (Fig. 9 & Para [0075]). Regarding claim 15, Hong in view of Ebisuno teaches a display apparatus (Para [0067], display apparatus 1), comprising the display substrate according to claim 1 (Fig. 9). Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Hong (US20180052493A1) and Zhao (US20220285464A1) as applied to claim 10 above, and further in view of Zeng (US20190333940A1). Regarding claim 17, Hong in view of Zhao teaches the display substrate according to claim 10, wherein the second opening has a depth less than a thickness of the corresponding inorganic film layer (Para [0055-0057]), but does not specify the second opening has a depth less than half a thickness of the corresponding inorganic film layer. However, Zeng teaches the second opening has a depth less than half a thickness of the corresponding inorganic film layer (Fig. 2 & Para [0047]). It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the invention, to modify a display panel of Hong (US20180052493A1) and further integrating the alternative structure of array substrate disclosed by Zeng (US20190333940A1). The combination of these familiar elements can prevent breakage of the film by reducing bending stress, as described in paragraph [0039] of Zeng. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAHAE KIM whose telephone number is (571)270-1844. The examiner can normally be reached M-F 9-5. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Fernando Toledo can be reached at (571) 271-1867. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /FERNANDO L TOLEDO/Supervisory Patent Examiner, Art Unit 2897 /JAHAE KIM/Examiner, Art Unit 2897
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Prosecution Timeline

Jun 27, 2022
Application Filed
May 21, 2025
Non-Final Rejection mailed — §102, §103
Aug 18, 2025
Response Filed
Oct 02, 2025
Final Rejection mailed — §102, §103
Dec 30, 2025
Request for Continued Examination
Jan 22, 2026
Response after Non-Final Action
Sep 29, 2026
Non-Final Rejection mailed — §102, §103 (current)

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Prosecution Projections

3-4
Expected OA Rounds
73%
Grant Probability
92%
With Interview (+18.8%)
3y 6m (~0m remaining)
Median Time to Grant
High
PTA Risk
Based on 48 resolved cases by this examiner. Grant probability derived from career allowance rate.

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