DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The amendment filed on 10/28/2025 has been entered. Applicant’s amendments to the claim rejections under 35 USC 112 have overcome each objection set forth in the Non-Final Office Action mailed on 08/18/2025. Accordingly, the rejections are withdrawn. Claim 1 has been amended, claim 20 cancelled, and claim 21 newly added.
Therefore, claims 1-3, 18-19, and 21 have been fully considered.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim 21 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 21 recites that “first scan line and the second scan line are disposed in the second metal layer.” However, specification does not describe the first scan line and the second scan line as being disposed in the second metal layer, nor do the drawing depict such an arrangement. Accordingly, claim 21 contains subject matter which was not described in the application as originally field.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 21 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 21 recites “a first initialization signal line,’ which lacks proper antecedent basis. It is unclear whether this limitation refers to “the first initialization signal line” previously recited in claim 1.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3 and 18-19 are rejected under 35 U.S.C. 103 as being unpatentable over Mou (US20220044636A1), and further in view of Tian (CN113777847B).
Regarding claim 1, Mou teaches a display panel (display substrate 100), comprising a plurality of light-emitting devices (organic light emitting element 220) arranged in an array and a pixel driving circuit (Fig. 8, pixel circuit 221) configured to drive one of the light-emitting devices (Para [0134], pixel circuit 221 is used to drive the organic light emitting element 220 to emit light.), wherein the pixel driving circuit comprises:
a first initialization transistor (Fig. 8, first reset transistor T6) connected to a first initialization signal line and configured to input a first initialization signal to a first node under a control of a first scan signal (Para [0147], first electrode of the first reset transistor T6 is configured to be electrically connected to a first reset power supply terminal Vinit1 to receive a first reset signal);
a switch transistor (Fig. 8, data writing transistor T2) configured to input a data signal to a second node under a control of a second scan signal (Para [0147], second electrode of the data writing transistor T2 is configured to be electrically connected to a data line Vd to receive the data signal, and a gate electrode of the data writing transistor T2 is configured to be electrically connected to a first scanning signal line Ga1 to receive the scanning signal);
a driving transistor (Fig. 8, driving transistor T1) configured to drive one of the light-emitting devices to emit light under a control of potentials of the first node and the second node (Para [0146-0147]); and
a compensation transistor (Fig. 8, compensation transistor T3) connected to the driving transistor through the first node and the third node, and configured to compensate a threshold voltage of the driving transistor under a control of a third scan signal (Para [0147], gate electrode of the threshold compensation transistor T3 is configured to be electrically connected to a second scanning signal line Ga2 to receive a compensation control signal);
wherein the compensation transistor comprises a first gate and a second gate connected to each other, and the first initialization transistor comprises a third gate and a fourth gate connected to each other; wherein the display panel further comprises a shielding metal (Fig. 9D, shielding line 344), a first active pattern (Para [0163] active semiconductor layer 310 includes an active layer pattern and a doped region pattern) is disposed between the first gate and the second gate (Fig. 9A), and a second active pattern (Para [0163] one of the active semiconductor layer 310 of transistors T1-T7 includes an active layer pattern and a doped region pattern) is disposed between the third gate and the fourth gate (Fig. 9A); and the shielding metal is disposed on at least one of the first active pattern and the second active pattern (Para [0192], light shielding portion S1 overlaps with the active semiconductor layer 310 between the two gate electrodes of the threshold compensation transistor T3).
But Mou does not teach the compensation transistor and the first initialization transistor both have a dual-gate structure, the compensation transistor comprises a first gate and a second gate connected to each other and perpendicular to each other. And the first initialization transistor comprises a third gate and a fourth gate connected to each other and perpendicular to each other.
However, Tian teaches dual-gate TFT including first gate 41 and the second gate 42 are vertically connected to each other to form an L-shaped structure, and are disposed on one side of the gate line 2 close to the sub-pixel unit. That is, the first gate electrode 41 and the second gate electrode 42 are disposed perpendicular to each other at the overlapping position of the gate line 2 and the signal line 3 (see paragraph marked [1] in attached translation). So that by using dual-gate structure of TFT in method of Mou, the method would comprise the compensation transistor and the first initialization transistor both have a dual-gate structure, the compensation transistor comprises a first gate and a second gate connected to each other and perpendicular to each other. And the first initialization transistor comprises a third gate and a fourth gate connected to each other and perpendicular to each other.
It would have been obvious to modify the thin film transistor of Mou (US20220044636A1) to include a second gate electrode disposed perpendicular to the first gate electrode as taught by Tian (CN113777847B) in order to improve channel controllability and reduce leakage current, which are recognized advantage of dual-gate structure (see paragraph marked [2] in attached translation)
Regarding claim 2, Mou in view of Tian teaches the display panel according to claim 1, wherein the shielding metal is disposed on the first active pattern between the first gate and the second gate, or the shielding metal is disposed on the second active pattern between the third gate and the fourth gate (Para [0192], light shielding portion S1 overlaps with the active semiconductor layer 310 between the two gate electrodes of the threshold compensation transistor T3).
Regarding claim 3, Mou in view of Tian teaches the display panel according to claim 2, wherein the shielding metal is disposed on the first active pattern between the first gate and the second gate.
Regarding claim 18, Mou in view of Tian teaches the display panel according to claim 1, wherein the pixel driving circuit further comprises a storage capacitor (Para [0147] and Fig. 8, capacitor C), one end of the storage capacitor is connected to a power high potential signal line (Para [0147] and Fig. 8, capacitor C is electrically connected to the first voltage terminal VDD), and another end of the storage capacitor is connected to the first node (Para [0147] and Fig. 8, capacitor C is electrically connected to the first electrode of the first rese transistor T6).
Regarding claim 19, Mou in view of Tian teaches the display panel according to claim 1, wherein the first initialization transistor is a low temperature polysilicon thin film transistor (Para [0163-0164], active layer of T6 include an low-temperature polysilicon layer), the compensation transistor is the 1 low temperature polysilicon thin film transistor (Para [0163-0164], active layer of T3 include an low-temperature polysilicon layer), there is a gap between projections of the first gate and the second gate on the first active pattern (Fig. 10A-C, gap between projection of compensation transistor T3’s gates electrodes), and there is a gap between projections of the third gate and the fourth gate on the second active pattern (Fig. 10A-C, gap between projection of the first reset transistor T6’s gate electrodes).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure. Zhou (US20180342198A1) teaches the dual-gate TFT relates to the technical of method of pixel circuit, comprising a compensation unit, a driving unit, a light-emitting unit, a capacitor and an external power supply, wherein the compensation unit comprises a data strobe transistor and a compensation transistor.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/FERNANDO L TOLEDO/Supervisory Patent Examiner, Art Unit 2897
/JAHAE KIM/Examiner, Art Unit 2897