DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant's claim for foreign priority based on an application filed in China on 06/23/2022. It is noted, however, that applicant has not filed a certified copy of the CN111430413A application as required by 37 CFR 1.55.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 12/29/2026 has been entered.
Response to Amendment
The amendment filed on 12/29/2025 has been accepted and entered. Claims 1-8 remain pending in this application.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al (US20200091273-Lee73) in view of Chung et al. (US 20210265271-Chung71).
Regarding Claim 1: Lee73 discloses a display panel (Abstract Line L1), wherein the display panel comprises:
a substrate having a first surface and a second surface opposite to each other (Substrate SUB having a first/top surface and a second/bottom surface and top surface and bottom surface are opposite to each other-See Examiner's annotated Fig 11 below);
a driving circuit layer disposed on a side of the substrate (Integrated Circuit IC on bottom of substrate: [0013]L11-12; Fig 20), and the driving circuit layer comprises
a plurality of thin film transistors (Thin film transistor-[0077]L6; there is a plurality of pixel, and each pixel includes a plurality of subpixels, and each subpixel SP includes a transistor and an OLED, so there is a plurality of transistors and OLEDs-[0053]L1-5);
a plurality of light-emitting units (There is a plurality of pixel, and each pixel includes a plurality of subpixels, and each subpixel SP includes a transistor and an OLED, so there is a plurality of transistors and OLEDs-[0053]L1-5) disposed on a side of the driving circuit layer (OLED is on top of Driving circuit DR-See Examiner's annotated Fig 11 below) away from the substrate (OLED is on top away from substate in the bottom-See Examiner's annotated Fig 11 below);
a planarization layer (the OC layer can be a planarization film-[0082]L7-8) disposed on a surface of the side of the substrate away from the driving circuit layer (The planarization layer OC is on the side of the OLED as seen in Examiner's annotated Fig 11, and the Drive Circuit IC is in the bottom of the substrate SUB as seen in Fig 20, so the layer OC is away from the Drive circuit IC),
a plurality of scanning lines (Signal lines [0060] L 5-6, DL1 or DL2-Fig 10) and
a plurality of data lines (Data lines [0077] L2-3, lines GL1 or GL2-Fig 10);
wherein the display panel further comprises a plurality of vias (Plurality of Vias CHV-Fig 12);
and the data lines and the scanning lines are electrically connected to the thin film transistors through the vias, respectively (The data lines and the power line, and sensing lines are electrically connected through the via to the thin film transistor, penetrating insulating layer-[0077]);
wherein the display panel comprises a plurality of display areas arranged in an array ([0044] L1), and
each of the display areas is correspondingly provided with one of the light-emitting units (each subpixel SP includes a transistor and an OLED-[0053]L1-5) and
one of the thin film transistors (each subpixel SP includes a transistor and an OLED-[0053]L1-5) electrically connected to
the one of the light-emitting units ((the transistor and the OLED are connected to signal lines [0053] L5-7),
one of the scanning lines (the transistors are connected to the data lines [0077] L16-18), and
one of the data lines (the transistor and the OLED are connected to signal lines [0053] L5-7), respectively, and
wherein the plurality of thin film transistors and the plurality of light-emitting units are disposed over the first surface of the substrate (transistor DR and light-emitting unit OLE disposed over first/top surface of substrate SUB-Fig 11), and
the plurality of scanning lines and the plurality of data lines are disposed over the second surface of the substrate (Scanning lines DL connected to OHV, OHV are on the backside/bottom/second surface of Substrate SUB-Fig 10, Fig 13B; Data lines GL are connected to OHH, OHH are on the backside/second surface of Substrate SUB-Fig 10, Fig 15B; so the plurality of scanning lines and the plurality of data lines are disposed over the second surface of the substrate-Fig 10, Fig 13B, Fig 15B).
Lee73 does not disclose a display panel
Wherein a plurality of scanning lines and a plurality of data lines disposed on a side of the planarization layer away from the substrate;
wherein each of the plurality of vias is extended through both the substrate and the planarization layer.
Chung 71 teaches a display panel
Wherein a plurality of scanning lines (BLL-Fig 4A)-and a plurality of data lines (CSLL-Fig 4A) disposed on a side of the planarization layer away from the substrate (scanning lines BLL and data lines CSLL are disposed on layer 207-[0050] L3-6; layer 207 is on Planarization layer 220-Fig 8; BLL and CSLL are disposed on the planarization layer 220);
wherein each of the plurality of vias (plurality of vias ETHV-Fig 7) is extended through both the substrate and the planarization layer (ETHV is extended through both the substrate 201 and the planarization layer 220-Examiner’s annotated Fig 8).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the display panel of Lee73 as taught by Chung71 for the purpose of improving the overall reliability (Chung71: [0058] L21).
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Claim(s) 2-4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al (US20200091273-Lee73) in view of Chung et al. (US 20210265271-Chung71), and further in view of Yan et al (US20210331441-Yan41).
Regarding claim 2, Lee73 and Chung71 combination discloses all the elements of claim 1, as noted above.
Lee73 further discloses a display panel wherein the display panel further comprises
gap areas defined among the plurality of display areas (gap area WA defined among the plurality of display areas EMA-Fig 10), wherein the display panel further comprises
a buffer layer disposed between the substrate and the driving circuit layer (buffer layer BUF is between the substrate layer SUB and the driving circuit DR -See Examiner's annotated Fig 11 below).
Lee73 and Chung71 combination fails to disclose a display panel wherein
the buffer layer is defined
with grooves
in the gap areas.
Yan41 teaches a display panel wherein
the buffer layer is defined
with grooves (buffer layer 102' includes a plurality of grooves 1-See Fig8)
in the gap areas (Grooves are located in the gap area between display areas 103-Fig 8).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the display panel of Lee73 in view of Chung71, as taught by Yan41 for the purpose of releasing the stress generating during the process (Yan41: [0040] Lines L11-14).
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Regarding claim 3, Lee73, Chung71, and Yan 41 combination discloses all the elements of claim 2, as noted above.
Yan41 further teaches a display panel wherein
any two adjacent ones of the display areas (two adjacent display areas 103-Fig 8) form a display area group (a group of two adjacent display areas 103-Fig 8), and
each of the gap areas in the display area group is defined with one of the grooves (Groove 1 is present in gap area between two adjacent display areas 103-Fig 8).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the display panel of Lee73 in view of Chung71, as taught by Yan41 for the purpose of releasing the stress generating during the process (Yan41: [0040] Lines L11-14).
Regarding claim 4, Lee73, Chung71, and Yan 41 combination discloses all the elements of claim 2, as noted above.
Yan41 further teaches a display panel wherein
any two adjacent ones of the display areas form a display area group (a group of two adjacent display areas 103-Fig 8), and the gap areas in a part of the display area groups are defined with the grooves (Grooves 1 are present in gap area between two adjacent display areas 103-Fig 8).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the display panel of Lee73 in view of Chung71, as taught by Yan41 for the purpose of releasing the stress generating during the process (Yan41: [0040] Lines L11-14).
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al (US20200091273-Lee73) in view of Chung et al. (US 20210265271-Chung71), in view of Yan et al (US20210331441-Yan41), and further in view of Kwon et al. (US20190131377-Kwon77).
Regarding claim 5, Lee73, Chung71, and Yan 41 combination discloses all the elements of claim 2, as noted above.
Lee73 further discloses a display panel wherein the display panel further comprises
an encapsulation layer disposed on a side of the light-emitting units away from the driving circuit layer (encapsulation layer OC is on top of the display, under the light emitting unit OLE, so away from the driving circuit layer DR-See Examiner’s annotated Fig 11 below, [0044] L4-7).
Lee73 and Yan41 combination fails to teach a display panel wherein
the encapsulation layer comprises
an encapsulation cover plate, and
a hardness of the encapsulation cover plate is greater than a hardness of the substrate.
Kwon77 teaches a display panel wherein
the encapsulation layer (Layer 370/500-Fig 2)comprises
an encapsulation cover plate(Cover plate 500-Fig 2), and
a hardness of the encapsulation cover plate is greater than a hardness of the substrate (Cover plate 500 can be a glass substrate-[0036]LL4-5; the base substrate can be a polyimide substrate-[0006] L5-6; the Young’s modulus of Glass is larger than 30GPa (Karabulut01: Table 2), while the Young’s modulus of polyimide is 2.5GPa (mit.edu). Glass’s Young’s modulus being 10 at least 10 times the polyimide’s one, the hardness of the glass is greater than the polyimide’s one. Consequently the hardness of the cover plate 500 is higher than the base substrate).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the display panel of Lee73, in view of Chung71 and further in view of Yan41, as taught by Kwon77 for the purpose of preventing cracks in release process (Kwon77: [0076] L22-23).
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Claim(s) 6 and 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al (US20200091273-Lee73) in view of Chung et al. (US 20210265271-Chung71), in view of Yan et al (US20210331441-Yan41), and further in view of Kim et al (US 20230215979-Kim79).
Regarding claim 6, Lee73, Chung71, and Yan 41 combination discloses all the elements of claim 2, as noted above.
Lee73, Chung71, and Yan 41 combination fails to disclose a display panel
wherein a surface roughness of the side of the substrate away from the driving circuit layer is greater than a surface roughness of a side of the substrate facing the driving circuit layer.
Kim79 teaches a display panel
wherein a surface roughness of the side of the substrate away from the driving circuit layer is greater than a surface roughness of a side of the substrate facing the driving circuit layer (The roughness, shown by the small “waves” d0, of the substrate layer 40 on the side of the light emitting element, side 40a, has a higher roughness than on the other side, side 40b, where there is no “wave”-See Examiner's annotated Fig 4 below).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the display panel of Lee73 in view of Chung71 and further in view of Yan41, as taught by Kim79 for the purpose of increasing the adhesive force between light emitting elements and the substrate (Kim79:[0007] L4-10).
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Regarding claim 8, Lee73, Chung71, Yan 41, and Kim79 combination discloses all the elements of claim 6, as noted above.
Lee73 further discloses a display panel wherein the display panel further comprises
a first metal layer (DL1-See Examiner’s annotated Fig12 below) disposed on the side of the planarization layer away from the substrate (OC is the Planarization film-[0082]L7-8; DL1 is on top of the interlayer insulating layer ILD under the planarization layer OC-See Examiner's annotated Fig12 below),
an interlayer insulating layer disposed on a side of the first metal layer away from the planarization layer (OC is the Planarization film-[0082]L7-8; DL1 is on top of the interlayer insulating layer ILD under the planarization layer OC-See Examiner's annotated Fig12 below), and
a second metal layer (GLI-Fig 14) disposed on a side of the interlayer insulating layer away from the first metal layer (disposed on the bottom of the interlayer insulating layer ILD away from the first metal layer DL1 which is on top of the interlayer insulating layer ILD-Fig 14, See Examiner's annotated Fig 12 below), wherein
the first metal layer comprises the scanning lines (DL1 is connected to OHV-Fig 12; OHV is connected to Vertical lines DL1, Dl2, DL3, and DL4-Fig 10; ), and
the second metal layer comprises the data lines (Horizontal lines are connected on GLI through OHH-[0093]L9-12, Fig 14).
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Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al (US20200091273-Lee73) in view of Chung et al. (US 20210265271-Chung71), in view of Yan et al (US20210331441-Yan41), in view of Kim et al (US 20230215979-Kim79), and further in view of Liu et al. (US11488987-Liu87).
Regarding claim 7, Lee73, Chung71, Yan 41, and Kim79 combination discloses all the elements of claim 6, as noted above.
Lee73, Chung71, Yan41, and Kim79 combination does not disclose a display panel
wherein an opening area of each of the vias gradually increases in a direction of the substrate away from the driving circuit layer.
Liu87 teaches a display panel
wherein an opening area of each of the vias gradually increases in a direction of the substrate away from the driving circuit layer (Vias 4 have a conic shape which gradually open up from TFT to substrate-See Examiner's annotated Fig.2).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the display panel of Lee73 in view of Chung71, in view of Yan41, and further in view of Kim79, as taught by Liu87 for the purpose of minimizing bezel size (Liu87: C5L15-17).
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Response to Arguments
Applicant’s arguments with respect to claim 1, pages 8-9 of Remarks filed on 12/29/2026, have been fully considered but they are not persuasive.
The applicant states that Lee73 does not disclose claim 1 new limitation, especially “the plurality of thin film transistors and the plurality of light-emitting units are disposed over the first surface of the substrate, and the plurality of scanning lines and the plurality of data lines are disposed over the second surface of the substrate”. As noted above, Lee73 discloses a display panel wherein
the plurality of thin film transistors and the plurality of light-emitting units are disposed over the first surface of the substrate (transistor DR and light-emitting unit OLE disposed over first/top surface of substrate SUB-Fig 11), and
the plurality of scanning lines and the plurality of data lines are disposed over the second surface of the substrate (Scanning lines DL connected to OHV, OHV are on the backside/second surface of Substrate SUB-Fig 10, Fig 13B; Data lines GL are connected to OHH, OHH are on the backside/second surface of Substrate SUB-Fig 10, Fig 15B; so the plurality of scanning lines and the plurality of data lines are disposed over the second surface of the substrate). Therefore, Lee73 clearly discloses that the claimed elements are on the same side or over the same surface of the substrate, and applicant’s arguments are not persuasive.
Applicant further argues that Chung71 is non-analogous art because Chung 71 does not disclose a display panel but rather discloses a 3D memory device (See Remarks at Pages 9-10). In response to applicant's argument that Chung 71 is nonanalogous art, it has been held that a prior art reference must either be in the field of the inventor' s endeavor or, if not, then be reasonably pertinent to the particular problem with which the inventor was concerned, in order to be relied upon as a basis for rejection of the claimed invention. See In re Oetiker, 977 F.2d 1443, 24 USPQ2d 1443 (Fed. Cir. 1992). In this case,
MPEP 214.01 (a) states “In re Bigio, 381 F.3d 1320, 1325, 72 USPQ2d 1209, 1212 (Fed. Cir. 2004). A reference is analogous art to the claimed invention if:
(1) the reference is from the same field of endeavor as the claimed invention (even if it addresses a different problem); or
(2) the reference is reasonably pertinent to the problem faced by the inventor (even if it is not in the same field of endeavor as the claimed invention).
Note that “same field of endeavor” and “reasonably pertinent” are two separate tests for establishing analogous art; it is not necessary for a reference to fulfill both tests in order to qualify as analogous art. See Bigio, 381 F.3d at 1325, 72 USPQ2d at 1212.”
Chung71 addresses the wiring layer position and the position on their associated vias compared to the substrate and possible other component in the PS layer which may include various control circuits in other words transistors ([026], [039]). While not disclosing a display panel, Chung71 is still disclosing a semiconductor device with a specific wiring position to isolate the transistor from the common source line and to improve the reliability of the semiconductor device ([058]). In doing so, Chung71 addresses the same specific technical problem which is improving the performance of the transistors as application 17516915 related to the source/drain contact for transistors (See application’s [015]). So Chung71 is reasonably pertinent to the problem, therefore, Chung71 is an analogous art as defined by MPEP 214.01 (a).
Applicant also argues that since Chung 71 is only directed to the 3D semiconductor memory device, the device cannot include any of the light emitting units as the conductive lines an second conductive lines do not correspond to the to the data lines and scanning lines of the claimed invention as these elements do not supply scan signals/data signals. (see Remarks at page 10). The examiner respectfully disagrees.
While Chung71 is directed to a memory device, it is cited for the purpose of demonstrating that the position of the data lines and scanning lines on the opposite side of a substrate is a feature known in analogous art for the same reasons cited above.
Lastly, Applicant argues that there is a lack of motivation to combine Lee73 with Chung71 for the purpose of improving reliability. (see Remarks at page 10). The Examiner respectfully disagrees.
Chung71 was cited for the purpose of demonstrating that the position of the data lines and scanning lines on the opposite side of a substrate improves a noise characteristics of the common source line CSL, which thus shows an improvement in the overall reliability (Chung71:[058] L14-15, L19-20). Therefore, there is a proper motivation to combine Lee73 with Chung71 for the purpose of improving reliability.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Wang et al. (US 20220199650 A1-Wang50) discloses a display panel comprising a substrate having a first surface and a second surface opposite to each other (BS having a top/bottom surfaces-Fig 5), wherein the plurality of transistors (TFT-Fig 5) and the plurality of light-emitting units (LE-Fig5) are disposed over the first surface of the substrate (TFT and LE disposed over first/top surface of substrate BS-Fig 5), and the plurality of scanning lines and the plurality of data lines are disposed over the second surface of the substrate (signal lines LL are on the backside/second surface of Substrate BS in the V-area-Fig 5).
Li et al. (CN 113380846 A with machine translation-Li46) discloses a display panel comprising a substrate having a first surface and a second surface opposite to each other (10 having a top/bottom surfaces-Fig 4e), wherein the plurality of transistors (driving circuit 22-Fig 4e) and the plurality of light-emitting units (micro-diode 30-Fig4e) are disposed over the first surface of the substrate (22 and 30 disposed over first/top surface of substrate 10-Fig 4e), and the plurality of scanning lines and the plurality of data lines are disposed over the second surface of the substrate (signal lines 12 are on the backside/second surface of Substrate 10-Fig 4e).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NATHALIE R FAYETTE whose telephone number is (571)272-1220. The examiner can normally be reached Monday-Friday 8:30 am-6pm ET.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Christine Kim can be reached at (571) 272-8458. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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NATHALIE R. FAYETTE
Examiner
Art Unit 2812
/NATHALIE R FAYETTE/Examiner, Art Unit 2812 02/12/2026
/CHRISTINE S. KIM/Supervisory Patent Examiner, Art Unit 2812