DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 02/02/2026 has been entered.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 29-31, 33, 36 and 37 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 29 recites the limitation "the first width" in the first line of the claim. There is insufficient antecedent basis for this limitation in the claim.
Claim 29 recites the limitation "the second width" in the second line of the claim. There is insufficient antecedent basis for this limitation in the claim.
Claim 33 recites the limitation "the first width" in the first line of the claim. There is insufficient antecedent basis for this limitation in the claim.
Claim 33 recites the limitation "the second width" in the second line of the claim. There is insufficient antecedent basis for this limitation in the claim.
Claim 36 recites the limitation "the first width" in the second line of the claim. There is insufficient antecedent basis for this limitation in the claim.
Claim 36 recites the limitation "the second width" in the third line of the claim. There is insufficient antecedent basis for this limitation in the claim.
Claim 37 recites the limitation "the first width" in the second line of the claim. There is insufficient antecedent basis for this limitation in the claim.
Claim 37 recites the limitation "the second width" in the fourth line of the claim. There is insufficient antecedent basis for this limitation in the claim.
Claims 30-31 are rejected because they depend on the rejected claim 29.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 26-28 and 32-39 is/are rejected under 35 U.S.C. 103 as being unpatentable over Xiao (US 2020/0312868 A1) in view of Xu et al. (CN 110277404 A, please see the machine translation in this office action).
Regarding claim 26, Xiao teaches in Fig. 1A, a memory array (100; [0036]) comprising: a plurality of word lines (106s except the bottommost 106; [0040]) arranged in a vertical stack (see Fig. 1A); and a memory pillar (120/122/124/118; [0044, 0045]) extending through at least the plurality of word lines (106s except the bottommost 106), the memory pillar (120/122/124/118) further including: (see Fig. 1A); a channel (122/118; [0044-0045]) extending vertically through the plurality of word lines (106s except the bottommost 106), wherein the channel (122/118) comprises a first region (the upper half portion of 122/118; [0044-0045]) and a second region (the lower half portion of 122/118; [0044-0045]) below the first region (the upper half portion of 122/118); and a pillar core (124; [0044]) including non-conductive material (dielectric materials; [0044]) and surrounded by both the first region (the upper half portion of 122/118) and the second region (the lower half portion of 122/118) of the channel (122/118; see Fig. 1A), wherein the second region (the lower half portion of 122/118) of the channel (122/118) surrounds the pillar core (124), and extends adjacent to a select gate source (SGS) (the bottommost 106, a SGS of the memory array, the source select gate controlling the channel 118; Fig. 1A, [0039, 0045]).
Xiao does not teach the second region of the channel to come into contact with a current common source that is located below the memory pillar.
In the same field of endeavor of memory devices, Xu et al. teaches the second region of the channel (the lower half portion of 171/177; Fig. 3e, [0127]) to come into contact with a current common source (212; Fig. 3e, [0128]) that is located below the memory pillar (171/177/176; Fig. 3e, [0128-0129]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the inventions of Xiao and Xu et al. and to further include the current common source 212 of Xu et al. into the top surface of the substrate of Xiao, because the current common source 212 of Xu et al., which is a n-type doped region ([0111]), can provide a conductive path from the channel to the source line ([0128, 0132]).
Regarding claim 27, Xiao teaches in Fig. 1A, the memory array of claim 26, further comprising: a layer (the bottommost 106; [0039]) underneath the plurality of word lines (106s except the bottommost 106), wherein the channel (122/118) extends through at least a part of the layer (the bottommost 106), wherein the first region of the channel (122) extends through the plurality of word lines (106s except the bottommost 106), and wherein the second region of the channel (118) extends through at least a part of the layer (the bottommost 106) underneath the plurality of word lines (106s except the bottommost 106).
Regarding claim 28, Xiao teaches in Fig. 1A, the memory array of claim 27, wherein the layer (the bottommost 106) is one of (i) the SGS of the memory array, or (ii) an isolation layer to isolate a first memory deck of the memory array from a second memory deck of the memory array (the option (i), the bottommost 106, a SGS of the memory array, the source select gate controlling the channel 118; Fig. 1A, [0039, 0045]).
Regarding claim 32, Xiao teaches in Fig. 1A, the memory array of claim 26, wherein: the SGS (the bottommost 106, a SGS of the memory array, the source select gate controlling the channel 118; Fig. 1A, [0039, 0045]) arranged underneath the plurality of word lines (106s except the bottommost 106); a trench (the trench of 134 filled with 120/122/124/118; see Fig. 1A) extends across the plurality of word lines (106s except the bottommost 106) and the SGS (the bottommost 106); and the first region (the upper half portion of 122/118) and the second region (the lower half portion of 122/118) of the channel (122/118) are formed within the trench (the trench of 134 filled with 120/122/124/118; see Fig. 1A).
Regarding claim 33, Xiao teaches in Fig. 1A, the memory array of claim 26, wherein the first width (a horizontal width of 122), and the second width (a horizontal width of 118).
Xia does not teach the first width is at least 10 nanometers, and the second width is in a range of 4-7 nanometers (emphasis added).
Parameters such as the first width (a horizontal width of 122) and the second width (a horizontal width of 118) in the art of semiconductor manufacturing process are subject to routine experimentation and optimization to achieve the desired channel properties during device fabrication ([0044-0045]). Therefore, it would have been obvious to one of the ordinary skill in the art at the time the invention was made to incorporate the first width and the second width within the range as claimed in order to the desired channel properties ([0044-0045]).
Regarding claim 34, Xiao teaches in Fig. 1A, the memory array of claim 26, further comprising: a plurality of memory cells ([0039]), each memory cell formed at a corresponding junction of a corresponding WL (106s except the bottommost 106; [0040, 0044-0045]) and the channel (122/118; [0039, 0044, 0045]).
Regarding claim 35, Xiao teaches in Fig. 1A, the memory array of claim 26, wherein the channel (122/118) is a Doped Hollow Channel (DHC) (see Fig. 1A, 122/118 has a hollow center).
Regarding claim 36, Xiao teaches in Fig. 1A, the memory array of claim 26, wherein: the first width (an average horizontal width of the upper half portion of 122/118) is an average horizontal width of the first region of the channel (the upper half portion of 122/118); and the second width (an average horizontal width of the lower half portion of 122/118) is an average horizontal width of the second region of the channel (the lower half portion of 122/118; see Fig. 1A).
Regarding claim 37, Xiao teaches in Fig. 1A, the memory array of claim 26, wherein: the first width (a maximum horizontal width of the upper half portion of 122/118) is a maximum horizontal width of the first region of the channel (the upper half portion of 122/118) along a vertical length of the first region (the upper half portion of 122/118); and the second width (a minimum horizontal width of the lower half portion of 122/118) is a minimum horizontal width of the second region of the channel (the lower half portion of 122/118) along a vertical length of the second region (the lower half portion of 122/118; see Fig. 1A).
Regarding claim 38, Xiao teaches in Fig. 1A, the memory array of claim 26, wherein the first and second widths (a horizontal width of 122 and a horizontal width of 122; see Fig. 1A) are uniform along the first and second regions (the upper half portion of 122/118 and the lower half portion of 122/118), respectively, such that a minimum width of the first region (a minimum horizontal width of 122 of the upper half portion of 122/118) is less than 1 nm (0 nm indicated in Fig. 1A) different than a maximum width of the first region (a maximum horizontal width of 122 of the upper half portion of 122/118), and a minimum width of the second region (a minimum horizontal width of 122 of the lower half portion of 122/118) is less than 1 nm (0 nm indicated in Fig. 1A) different than a maximum width of 112 of the second region (a maximum horizontal width of 122 of the lower half portion of 122/118).
Regarding claim 39, Xiao teaches in Fig. 1A, the memory array of claim 26, wherein the memory array (100) is three-dimensional (3D) NAND flash memory array (100; [0039]), and a plurality of memory cells (memory cells in 3D memory device 100; [0039]) are formed at a plurality of junctions (the junction where 106s except the bottommost 106 meet 120; [0039, 0044]) of the plurality word lines (106s except the bottommost 106) and the memory pillar (120/122/124/118; implied in [0039, 0044]).
Claim(s) 29-31 is/are rejected under 35 U.S.C. 103 as being unpatentable over Xiao and Xu et al. as applied to claim 26 above, and further in view Kim et al. (US 2018/0331119 A1).
Regarding claim 29, Xiao teaches in Fig. 1A, the memory array of claim 26, wherein the first width (a horizontal width of 122) of the first region (the upper half portion of 122/118) and the second width (a horizontal width of 118) of the second region (the lower half portion of 122/118; see Fig 1A).
Xia does not teach the first width of the first region is at least 3 nm less than the second width of the second region (emphasis added).
In the same field of endeavor of the semiconductor memories, Kim et al. teach the first width of the first region (the horizontal width of 140) is 5 nm to 10 nm (Fig. 7A, [0093]).
It would have been obvious to one of ordinary skill in the art at the time of invention was made to combine the inventions of Xia and Kim et al., and to use the upper channel layer of 5 nm to 10 nm as taught by Kim et al. ([0093]), because Xia is silent about the horizontal width of the upper channel layer (122 of Xia) while Kim et al. teach that the horizontal width of the upper channel layer (140 of Kim et al.) can have a width of 5 nm to 10 nm (Fig. 7A, [0093]).
The combination of Xia and Kim et al. teach “the first width of the first region is at least 3 nm less than the second width of the second region”, because Xia teaches the first width (a horizontal width of 122 of Xia) of the first region (the upper half portion of 122/118 of Xia) is at least one times the first width less than the second width (a horizontal width of 118) of the second region (the lower half portion of 122/118; see Fig 1A, a horizontal width of 118 is more than twice a horizontal width of 122) and Kim et al. teach one times the first width (the horizontal width of 140; Fig. 7A, [0039] of Kim et al.) is 5 nm to 10 nm (Fig. 7A, [0093] of Kim et al.).
Regarding claim 30, Xiao teaches in Fig. 1A, the memory array of claim 29, wherein: the plurality of word lines (106s except the bottommost 106) is a first plurality of word lines (106s except the bottommost 106 of 134; [0043]), and the channel (122/118) is a first channel (122/118); the first plurality of word lines (106s except the bottommost 106 of 134; [0043]) and the first channel (122/118) are included in a first memory deck (134; [0043]) of the memory array (100); the memory array (100) further comprises a second memory deck (136; [0043]) comprising a second plurality of word lines (106s except the bottommost 106 of 136) and a second channel (130/116; [0044]); the first memory deck (134; see Fig. 2A) and the second memory deck (136) are separated by an inter-deck plug (126) and an isolation region (138; [0043]); and the second channel (130/116) comprises a third region (130; [0044]) and a fourth region (116; [0044]), the third region (130) of the second channel (130/116) having a third width (the horizontal width of 130) that is different from a fourth width (the horizontal width of 116) of the fourth region (116) of the second channel (130/116), the third width (the horizontal width of 130) being different from the fourth width (the horizontal width of 116).
Xia does not teach the third width being at least 1 nm different from the fourth width (emphasis added).
Parameters such as the third width (the horizontal width of 130) and the fourth width (the horizontal width of 116) in the art of semiconductor manufacturing process are subject to routine experimentation and optimization to achieve the desired channel properties during device fabrication ([0047]). Therefore, it would have been obvious to one of the ordinary skill in the art at the time the invention was made to incorporate the third width and the fourth width within the range as claimed such that the third width being at least 1 nm different from the fourth width in order to the desired channel properties ([0044-0045]).
Regarding claim 31, Xiao teaches in Fig. 1A, the memory array of claim 30, wherein: the first memory deck (134) is underneath the second memory deck (136); the first plurality of word lines (106s except the bottommost 106 of 134; [0043]) of the first memory deck (134) are above the SGS (the bottommost 106, a SGS of the memory array, the source select gate controlling the channel 118; Fig. 1A, [0039, 0045]), and the second plurality of word lines (106s except the bottommost 106 of 136) of the second memory deck (136) are above the isolation region (138); the first region (the upper half portion of 122/118) of the first channel (122/118) is laterally adjacent to the word lines (106s except the bottommost 106) of the first plurality of word lines (106s except the bottommost 106 of 134; [0043]); the second region of the channel (the lower half portion of 122/118) is laterally adjacent to the SGS (the bottommost 106), the second width (a horizontal width of 118) being greater than the first width (a horizontal width of 122); the third region (130) of the second channel (130/116) is laterally adjacent to the word lines (106s except the bottommost 106) of the second plurality of word lines (106s except the bottommost 106 of 136); and the fourth region (116) of the second channel (130/116) is laterally adjacent to the isolation region (138) and the inter-deck plug (126), the fourth width (the horizontal width of 116) being greater than the third width (the horizontal width of 130).
Claim(s) 40 is/are rejected under 35 U.S.C. 103 as being unpatentable over Xiao and Xu et al. as applied to claim 26 above, and further in view of Nguyen et al. (US 2019/0371414 A1) and Kim et al. (US 2018/0331119 A1).
Regarding claim 40, Xiao teaches in Fig. 1A, the memory array of claim 26, wherein the memory array (100).
Xiao does not teach the memory array is attached to a printed circuit board, the first region of the channel has a first width that is at least 1 nm less than a second width of the second region of the channel (emphasis added).
In the same field of endeavor of memory devices, Nguyen et al. teach the memory array (memory array of the memory element 123; Fig. 1, [0048]) is attached to a printed circuit board ([0053]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the inventions of Xiao and Nguyen et al., and to further include the printed circuit board as taught by Nguyen et al., because the printed circuit board can be used to provide a mechanical and electrical support structure to the semiconductor chips or packages to form a computing device as taught by Nguyen et al. ([0053]).
In the same field of endeavor of the semiconductor memories, Kim et al. teach the first region of the channel (140; Fig. 3, [0042]) has a first width (the horizontal width of 140) that is 5 nm to 10 nm (Fig. 7A, [0093]).
It would have been obvious to one of ordinary skill in the art at the time of invention was made to combine the inventions of Xia and Kim et al., and to use the upper channel layer of 5 nm to 10 nm as taught by Kim et al. ([0093]), because Xia is silent about the horizontal width of the upper channel layer (122 of Xia) while Kim et al. teach that the horizontal width of the upper channel layer (140 of Kim et al.) can have a width of 5 nm to 10 nm (Fig. 7A, [0093]).
The combination of Xia and Kim et al. teach “the first region of the channel has a first width that is at least 1 nm less than a second width of the second region of the channel”, because Xia teaches the first region of the channel (122 of Xia) has a first width (a horizontal width of 122) that is at least one times the first width less than a second width (a horizontal width of 118) of the second region of the channel (118; see Fig 1A, a horizontal width of 118 is more than twice a horizontal width of 122) and Kim et al. teach one times the first width (the horizontal width of 140; Fig. 7A, [0039] of Kim et al.) is 5 nm to 10 nm (Fig. 7A, [0093] of Kim et al.).
Claim(s) 41 is/are rejected under 35 U.S.C. 103 as being unpatentable over Xiao and Xu et al. as applied to claim 26 above, and further in view of Nagashima et al. (US 2020/0098784 A1).
Regarding claim 41, Xiao teaches in Fig. 1A, the memory array of claim 26, wherein: the first width (a horizontal width of 122) is measured along a vertical length of the first region (the upper half portion of 122/118; [0044-0045]; see Fig. 1A); the second width (a horizontal width of 118) is measured along a vertical length of the second region (the lower half portion of 122/118; [0044-0045]; see Fig. 1A); and the SGS (the bottommost 106, a SGS of the memory array, the source select gate controlling the channel 118; Fig. 1A, [0039, 0045]) is arranged laterally adjacent to the vertical length of the second region of the channel (the lower half portion of 122/118; [0044-0045]), and configured to control a current density flowing along the vertical length of the second region of the channel (the lower half portion of 122/118; [0044-0045], this function is implied in [0045], where 118 functions as a channel, i.e. a channel for flowing the current or current density, and controlled by the bottommost 106 as a source select gate; [0039, 0045]).
Xiao does not teach the SGS is configured to control a current density flowing along the vertical length of the second region of the channel during an erase operation of the memory array (emphasis added).
In the same field of endeavor of semiconductor, Nagashima et al. teaches the SGS (the bottommost 102; Fig. 5, [0076]) is configured to control a current density (the current density of the erase current; [0076]) flowing along the vertical length of the second region of the channel (the vertical length of 105; Fig. 5; [0121]) during an erase operation of the memory array ([0076]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the inventions of Xiao and Nagashima et al., and to use the SGS of Xiao during an erase operation of the memory array as taught by Nagashima et al., because Xiao is silent about the usage of the SGS in different modes of operation, and Nagashima et al. teach that the SGS can be used during an erase operation of the memory array ([0076] of Nagashima et al.).
Response to Arguments
Applicant's arguments with respect to claim 26 have been considered but are moot in view of the new ground(s) of rejection.
Conclusion
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/HSIN YI HSIEH/Primary Examiner, Art Unit 2899 3/7/2026