DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Status
Claims 5, 6, and 8-10 have been cancelled. Claims 2-4, and 27-36 remain withdrawn as belonging to unelected groups in the restriction dated 16 April 2025.
Claim Objections
Claim 14 is objected to because of the following informality:
The word “comprise” in “...the plurality of first pixel circuits further comprise...” in claim 14 should be written as “comprises”, because a plurality is treated as singular.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 7, 11-16, 19-23, and 37-38 are rejected under 35 U.S.C. 103 as being unpatentable over Chen (US 202203110705 A1, hereinafter “Chen”), in view of Han et al (US 20210217821 A1, hereinafter “Han”), and further in view of Matsueda (US 20220199726 A1, hereinafter “Matsueda”).
Regarding Claim 1 – Chen discloses a display panel (Chen [0005]), comprising a first display region (light transmission region, Chen [0007], 200 in Chen [0049] and Fig. 6) and a second display region (main display region, Chen [0007] , 100 in Chen [0049] and Fig. 6), wherein the first display region comprises a plurality of first sub-pixels (second sub-pixels, Chen [0015] and [0029]), and the second display region comprises a plurality of second sub-pixels (first sub-pixels, Chen [0015] and [0029]); a first sub-pixel of the plurality of first sub-pixels comprises a first-type first sub-pixel (e.g. R2, Chen [0063]), a second sub-pixel of the plurality of second sub-pixels comprises a first-type second sub-pixel (e.g. R1, Chen [0063]), and an emitted color of the first-type first sub-pixel is the same as an emitted color of the first-type second sub-pixel (e.g. red, Chen [0063]); the first-type first sub-pixel comprises a first anode (402, Chen [0063]), and the first-type second sub-pixel comprises a second anode (401, Chen [0063]); and an area of the first anode is less than an area of the second anode (ratio 402 to 401 is 0.2-0.6, Chen [0074]); wherein a pixel distribution density of the plurality of first sub-pixels is equal to a pixel distribution density of the plurality of second sub-pixels (“Within the same unit area, the number of the first sub-pixels 11 included in the main display region 100 is equal to the number of the second sub-pixels 21 included in the display light transmission region 200.“, Chen [0064]): wherein the plurality of first sub-pixels comprise a first red sub-pixel, a first green sub-pixel and a first blue sub-pixel (R2, G2, and B2, Chen [0063]): the first-type first sub-pixel comprises the first green sub-pixel and at least one of the first red sub-pixel, or the first blue sub-pixel (G2 and at least one R2 or B2, Chen [0063]): and the second sub-pixel comprises a second green sub-pixel (G1, Chen [0063]).
PNG
media_image1.png
347
540
media_image1.png
Greyscale
Chen fails to disclose the first display region further comprises a plurality of first pixel circuits, the second display region further comprises a plurality of second pixel circuits, a first pixel circuit of the plurality of first pixel circuits is configured to drive a first sub-pixel corresponding to the first pixel circuit to emit light, and a second pixel circuit of the plurality of second pixel circuits is configured to drive a second sub-pixel corresponding to the second pixel circuit to emit light; and the first pixel circuit comprises a first sub-pixel circuit configured to drive the first green sub-pixel to emit light, and the second pixel circuit comprises a second sub-pixel circuit configured to drive the second green sub-pixel to emit light; and a channel width-to-length ratio of a drive transistor in the first sub-pixel circuit is greater than a channel width-to-length ratio of a drive transistor in the second sub-pixel circuit.
However, Han discloses the first display region further comprises a plurality of first pixel circuits (drive circuits in bb, Han [0048]), the second display region further comprises a plurality of second pixel circuits (drive circuits in aa, Han [0048]), a first pixel circuit of the plurality of first pixel circuits is configured to drive a first sub-pixel corresponding to the first pixel circuit to emit light (Han [0051]), and a second pixel circuit of the plurality of second pixel circuits is configured to drive a second sub-pixel corresponding to the second pixel circuit to emit light (Han [0050]); and the first pixel circuit comprises a first sub-pixel circuit configured to drive the first green sub-pixel to emit light (each green sub-pixel G in shaded areas in bb has a light-emitting element with a drive circuit, Han [0051]), and the second pixel circuit comprises a second sub-pixel circuit configured to drive the second green sub-pixel to emit light (each green sub-pixel G in aa has a light-emitting element with a drive circuit, Han [0050]).
Han is analogous to Chen because they both present display panels. While Chen is silent on the subject of including pixel circuits in the first display region, Han teaches including circuits that drive multiple sub-pixels in that region for the benefit of increased screen transmittance (Han [0032]). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to include circuits the drive multiple sub- pixels in the first display region for the benefit of increased screen transmittance.
Han fails to disclose a channel width-to-length ratio of a drive transistor in the first sub-pixel circuit is greater than a channel width-to-length ratio of a drive transistor in the second sub-pixel circuit.
However, Matsueda discloses a channel width-to-length ratio of a drive transistor in the first sub-pixel circuit is greater than a channel width-to-length ratio of a drive transistor in the second sub-pixel circuit (Matsueda [0025]).
Matsueda describes a similar display device to Chen. Matsueda teaches a larger channel width in a low density region for the advantage of higher luminance to compensate for lower pixel density (Matsueda [0027]). This is analogous to the first display region of the instant application, wherein the effective light-emitting area is less dense because of smaller anodes. Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to make the drive circuit channel width larger in the first display region for the advantage of higher luminance per light-emitting device.
Regarding Claim 7 – Chen modified by Han, and further modified by Matsueda, discloses all the limitations for claim 1.
The combination of Chen, Han, and Matsueda further discloses the first-type first sub-pixel further comprises a first pixel opening (202, Chen [0063]), and the first-type second sub-pixel further comprises the second pixel opening (201, Chen [0063]); the first anode comprises a first anode effective region (effective area, Chen [0071]), and a vertical projection of the first pixel opening on a plane where the first anode is located covers the first anode effective region (effective area depends on opening size, Chen [0071]); the second anode comprises the second anode effective region (effective area, Chen [0071]), and the vertical projection of the second pixel opening on a plane where the second anode is located covers the second anode effective region (effective area depends on opening size, Chen [0071]); an area of the first anode effective region is less than an area of the second anode effective region (area ratio 0.2-0.6, Chen [0071]); and an area of the first pixel opening is less than or equal to an area of the second pixel opening (201 > 202, Chen [0053]).
Regarding Claim 11 – Chen modified by Han, and further modified by Matsueda, discloses all the limitations for claim 1.
The combination of Chen, Han, and Matsueda further discloses the first sub-pixel circuit is configured to drive at least two first green sub-pixels to emit light (Chen [0079]).
Regarding Claim 12 – Chen modified by Han, and further modified by Matsueda, discloses all the limitations for claim 11.
The combination of Chen, Han, and Matsueda further discloses two first sub-pixel circuits are configured to drive four first green sub-pixels to emit light (Chen [0079], Fig. 7).
Regarding Claim 13 – Chen modified by Han, and further modified by Matsueda, discloses all the limitations for claim 1.
The combination of Chen, Han, and Matsueda further discloses the first pixel circuit further comprises a third sub-pixel circuit (60 connected to R2, Chen [0079]) and a fourth sub-pixel circuit (60 connected to B2, Chen [0079]), wherein the third sub-pixel circuit is configured to drive the first red sub-pixel to emit light, and the fourth sub-pixel circuit is configured to drive the first blue sub-pixel to emit light (Chen [0079]); and the third sub-pixel circuit is configured to drive at least two first red sub-pixels to emit light (Chen [0079], Fig. 7); or the fourth sub-pixel circuit is configured to drive at least two first blue sub-pixels to emit light (Chen [0079], Fig. 7); or the third sub-pixel circuit is configured to drive at least two first red sub-pixels to emit light, and the fourth sub-pixel circuit is configured to drive at least two first blue sub-pixels to emit light (Chen [0079], Fig. 7).
Regarding Claim 14 – Chen modified by Han, and further modified by Matsueda, discloses all the limitations for claim 1.
The combination of Chen, Han, and Matsueda further discloses the plurality of first pixel circuits further comprises a third sub-pixel circuit (60 connected to R2, Chen [0079]) and a fourth sub-pixel circuit (60 connected to B2, Chen [0079]), wherein the third sub-pixel circuit is configured to drive the first red sub-pixel to emit light, and the fourth sub-pixel circuit is configured to drive the first blue sub-pixel to emit light (Chen [0079]); and at least one of the first sub-pixel circuit, the third sub-pixel circuit or the fourth sub-pixel circuit is configured to drive at least two first sub-pixels electrically connected to the at least one of the first sub-pixel circuit, the third sub-pixel circuit or the fourth sub-pixel circuit to emit light (Chen [0080] and Fig. 7).
PNG
media_image2.png
334
545
media_image2.png
Greyscale
Regarding Claim 15 – Chen modified by Han, and further modified by Matsueda, discloses all the limitations for claim 11.
The combination of Chen, Han, and Matsueda further discloses at least two first sub-pixels driven by a same first pixel circuit of the plurality of first pixel circuits are electrically connected by a transparent conductive layer (Chen [0080]).
Regarding Claim 16 – Chen modified by Han, and further modified by Matsueda, discloses all the limitations for claim 14.
The combination of Chen, Han, and Matsueda further discloses the first sub-pixel circuit is configured to drive at least two first sub-pixels electrically connected to the first sub-pixel circuit to emit light (60 connected to G2, Chen [0079]), the third sub-pixel circuit is configured to drive at least two first sub-pixels electrically connected to the third sub-pixel circuit to emit light (60 connected to R2, Chen [0079]), and the fourth sub-pixel circuit is configured to drive at least two first sub-pixels electrically connected to the fourth sub-pixel circuit to emit light (60 connected to B2, Chen [0079]); the first sub-pixel comprises a first-color light-emitting sub-pixel, a second-color light-emitting sub-pixel and a third-color light-emitting sub-pixel (G2, R2, and B2, Chen [0079]); at least two first-color light-emitting sub-pixels driven by a same pixel circuit are electrically connected by a first transparent conductive layer (Chen [0080]); at least two second-color light-emitting sub-pixels driven by a same pixel circuit are electrically connected by a second transparent conductive layer (Chen [0080]); and at least two third-color light-emitting sub-pixels driven by a same pixel circuit are electrically connected by a third transparent conductive layer (Chen [0080]); the display panel further comprises a substrate (Chen [0007]), wherein on a plane where the substrate is located, a vertical projection of the first transparent conductive layer overlaps a vertical projection of a first pixel circuit configured to drive the first-color light-emitting sub-pixel to emit light; or on a plane where the substrate is located, a vertical projection of the first transparent conductive layer does not overlap a vertical projection of the first pixel circuit (The traces to each set of sub-pixels, G2, R2,and B2, are shown in Figure 7 as not overlapping the circuits 60); a vertical projection of at least part of the second transparent conductive layer on the plane where the substrate is located overlaps a vertical projection of at least one of the following on the plane where the substrate is located: a first pixel circuit configured to drive the first-color light-emitting sub-pixel or a first pixel circuit configured to drive the third-color light-emitting sub-pixel to emit light (A transparent layer used to drive a second sub-pixel (R2) overlaps a transparent layer used to drive a third sub-pixel (B2) at one G2, Chen Fig. 7. The transparent layer is part of the drive circuit.); and a vertical projection of at least part of the third transparent conductive layer on the plane where the substrate is located overlaps a vertical projection of at least one of the following on the plane where the substrate is located: the first pixel circuit configured to drive the first-color light-emitting sub-pixel or a first pixel circuit configured to drive the second-color light-emitting sub-pixel to emit light (A transparent layer used to drive a third sub-pixel (B2) overlaps a transparent layer used to drive a second sub-pixel (R2) at one G2, Chen Fig. 7. The transparent layer is part of the drive circuit.).
Regarding Claim 19 – Chen modified by Han, and further modified by Matsueda, discloses all the limitations for claim 15.
The combination of Chen, Han, and Matsueda further discloses the first pixel circuit comprises a drive transistor (T1, Matsueda [0038]) and a storage capacitor (C1, Matsueda [0038]), and a gate of the drive transistor and a capacitor plate of the storage capacitor are electrically connected to each other at a first node (C1T1, annotated Matsueda Fig. 2); and the display panel further comprises a substrate (Chen [0007]), wherein a vertical projection of the transparent conductive layer on a plane where the substrate is located does not overlap a vertical projection of the first node on the plane where the substrate is located (Chen Fig. 7).
While Chen is silent regarding the use of a storage capacitor connected to a drive transistor, Matsueda teaches the benefit of including a storage capacitor on the same electrical node to retain the drive transistor control voltage over one frame period (Matsueda [0043]). Therefore, it would have been obvious to one of ordinary skill in the art prior to the claimed invention to use a storage capacitor on the same electrical node as the drive transistor to hold the drive transistor voltage for the desired time period.
PNG
media_image3.png
613
471
media_image3.png
Greyscale
Regarding Claim 20 – Chen modified by Han, and further modified by Matsueda, discloses all the limitations for claim 15.
The combination of Chen, Han, and Matsueda further discloses the at least two first sub-pixels driven by the same first pixel circuit (60, Chen [0080]) comprise a first sub-pixel A and a first sub-pixel B (plurality of sub-pixels, Chen [0080]); and a first anode of the first sub-pixel A is electrically connected to the first pixel circuit through a via (through hole, Chen [0080]), and the first anode of the first sub-pixel A is electrically connected to a first anode of the first sub-pixel B by the transparent conductive layer (transparent trace to connect anodes of second sub-pixels, Chen [0080]).
Regarding Claim 21 – Chen modified by Han, and further modified by Matsueda, discloses all the limitations for claim 20.
The combination of Chen, Han, and Matsueda further discloses the plurality of first pixel circuits are arranged in an array and comprise a plurality of first pixel circuit groups (unit area bounded by solid black line, Han [0034]), and a first pixel circuit group of the plurality of first pixel circuit groups comprises at least two adjacent first pixel circuit columns (unit area has six columns, Han Fig. 2A); and the display panel further comprises a substrate (Han [0044]), wherein a vertical projection of the first sub-pixel A on a plane where the substrate is located overlaps a vertical projection of the first pixel circuit group on the plane where the substrate is located (one of the sub-pixels contains a drive transistor, Han [0059]); and a vertical projection of at least part of the first sub-pixel B on the plane where the substrate is located overlaps a vertical projection of a gap between two adjacent first pixel circuit groups of the plurality of first pixel circuit groups on the plane where the substrate is located (other sub-pixels are connected to a drive transistor by wiring 001, thus are between circuits, Han [0059]).
While Chen is silent on the subject, Han teaches pixel circuit groups in a unit area array containing columns for the benefit of independently displaying a pixel point (Han [0033]). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to use pixel circuit groups arranged in columns for the benefit of independently displaying a pixel point.
PNG
media_image4.png
574
551
media_image4.png
Greyscale
Regarding Claim 22 – Chen modified by Han, and further modified by Matsueda, discloses all the limitations for claim 20.
The combination of Chen, Han, and Matsueda further discloses the plurality of first pixel circuits are arranged in an array and comprise a plurality of second pixel circuit groups (unit area bounded by solid black line, Han [0034]), one second pixel circuit group of the plurality of second pixel circuit groups comprises at least two adjacent first pixel circuit rows (unit area has at least two rows, Han Fig. 2A), and two adjacent first pixel circuit rows in the one second pixel circuit group are staggered in a row direction (sub-pixels staggered in rows, Han Fig. 2A), wherein the row direction is an extension direction of the at least two adjacent first pixel circuit rows; and the display panel further comprises a substrate (Han [0044]), wherein on a plane where the substrate is located, a vertical projection of the first sub-pixel A overlaps a vertical projection of one second pixel circuit group of the plurality of second pixel circuit groups; and on the plane where the substrate is located (one of the sub-pixels contains a drive transistor, Han [0059]), a vertical projection of at least part of the first sub-pixel B overlaps a vertical projection of a gap between two adjacent first pixel circuits in one first pixel circuit row of at least two adjacent first pixel circuit rows in one second pixel circuit group of the plurality of second pixel circuit groups (other sub-pixels are connected to a drive transistor by wiring 001, thus are between circuits, Han [0059]).
While Chen is silent on the subject, Han teaches pixel circuit groups in a unit area array containing staggered rows for the benefit of independently displaying a pixel point (Han [0033]). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to use pixel circuit groups arranged in columns for the benefit of independently displaying a pixel point.
Regarding Claim 23 – Chen modified by Han, and further modified by Matsueda, discloses all the limitations for claim 22.
The combination of Chen, Han, and Matsueda further discloses the plurality of second pixel circuit groups comprise N second pixel circuit groups, wherein N denotes a positive integer (a defined quantity of units areas as in Han [0035] and Fig. 1A); each second pixel circuit group of the N second pixel circuit groups comprises M sub-pixel circuit groups (defined quantity of circuits in a unit area of region bb in Han Fig. 2A), and an mth sub-pixel circuit group of the M sub-pixel circuit groups comprises an mth first pixel circuit in a first first pixel circuit row in a same second pixel circuit group of the N second pixel circuit groups and an mth first pixel circuit in a second first pixel circuit row in the same second pixel circuit group, wherein M denotes a positive integer, and 1 ≤ m ≤ M (as in the example of Han [0057] and Fig. 2A); and the first display region further comprises M first data signal lines (001, Han [0059]), wherein an mth first data signal line of the M first data signal lines is configured to provide data signals for two first pixel circuits in an (m + n - 1)th sub-pixel circuit group in an nth second pixel circuit group of the N second pixel circuit groups, wherein 1 ≤ n ≤ N (Han [0060]).
Han teaches an organized array, same size array of drive circuits with lower density in the light transmissive display area (bb) versus the normal display area (aa) (Han [0035]) for the benefit of using the same fine metal mask (Han [0034]). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to use a unit area array of drive circuits the same size both display areas for the benefit of using the same fine metal mask.
PNG
media_image5.png
550
547
media_image5.png
Greyscale
Regarding Claim 37 – Chen discloses a display device (Chen [0005]), comprising a first display region (light transmission region, Chen [0007], 200 in Chen [0049] and Fig. 6) and a second display region (main display region, Chen [0007] , 100 in Chen [0049] and Fig. 6), wherein the first display region comprises a plurality of first sub-pixels (second sub-pixels, Chen [0015] and [0029]), and the second display region comprises a plurality of second sub-pixels (first sub-pixels, Chen [0015] and [0029]); a first sub-pixel of the plurality of first sub-pixels comprises a first-type first sub-pixel (e.g. R2, Chen [0063]), a second sub-pixel of the plurality of second sub-pixels comprises a first-type second sub-pixel (e.g. R1, Chen [0063]), and an emitted color of the first-type first sub-pixel is the same as an emitted color of the first-type second sub-pixel (e.g. red, Chen [0063]); the first-type first sub-pixel comprises a first anode (402, Chen [0063]), and the first-type second sub-pixel comprises a second anode (401, Chen [0063]); and an area of the first anode is less than an area of the second anode (ratio 402 to 401 is 0.2-0.6, Chen [0074]); wherein a pixel distribution density of the plurality of first sub-pixels is equal to a pixel distribution density of the plurality of second sub-pixels (“Within the same unit area, the number of the first sub-pixels 11 included in the main display region 100 is equal to the number of the second sub-pixels 21 included in the display light transmission region 200.“, Chen [0064]): wherein the plurality of first sub-pixels comprise a first red sub-pixel, a first green sub-pixel and a first blue sub-pixel (R2, G2, and B2, Chen [0063]): the first-type first sub-pixel comprises the first green sub-pixel and at least one of the first red sub-pixel, or the first blue sub-pixel (G2 and at least one R2 or B2, Chen [0063]): and the second sub-pixel comprises a second green sub-pixel (G1, Chen [0063]).
Chen fails to disclose the first display region further comprises a plurality of first pixel circuits, the second display region further comprises a plurality of second pixel circuits, a first pixel circuit of the plurality of first pixel circuits is configured to drive a first sub-pixel corresponding to the first pixel circuit to emit light, and a second pixel circuit of the plurality of second pixel circuits is configured to drive a second sub-pixel corresponding to the second pixel circuit to emit light; and the first pixel circuit comprises a first sub-pixel circuit configured to drive the first green sub-pixel to emit light, and the second pixel circuit comprises a second sub-pixel circuit configured to drive the second green sub-pixel to emit light; and a channel width-to-length ratio of a drive transistor in the first sub-pixel circuit is greater than a channel width-to-length ratio of a drive transistor in the second sub-pixel circuit.
However, Han discloses the first display region further comprises a plurality of first pixel circuits (drive circuits in bb, Han [0048]), the second display region further comprises a plurality of second pixel circuits (drive circuits in aa, Han [0048]), a first pixel circuit of the plurality of first pixel circuits is configured to drive a first sub-pixel corresponding to the first pixel circuit to emit light (Han [0051]), and a second pixel circuit of the plurality of second pixel circuits is configured to drive a second sub-pixel corresponding to the second pixel circuit to emit light (Han [0050]); and the first pixel circuit comprises a first sub-pixel circuit configured to drive the first green sub-pixel to emit light (each green sub-pixel G in shaded areas in bb has a light-emitting element with a drive circuit, Han [0051]), and the second pixel circuit comprises a second sub-pixel circuit configured to drive the second green sub-pixel to emit light (each green sub-pixel G in aa has a light-emitting element with a drive circuit, Han [0050]).
Han is analogous to Chen because they both present display panels. While Chen is silent on the subject of including pixel circuits in the first display region, Han teaches including circuits that drive multiple sub-pixels in that region for the benefit of increased screen transmittance (Han [0032]). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to include circuits the drive multiple sub- pixels in the first display region for the benefit of increased screen transmittance.
Han fails to disclose a channel width-to-length ratio of a drive transistor in the first sub-pixel circuit is greater than a channel width-to-length ratio of a drive transistor in the second sub-pixel circuit.
However, Matsueda discloses a channel width-to-length ratio of a drive transistor in the first sub-pixel circuit is greater than a channel width-to-length ratio of a drive transistor in the second sub-pixel circuit (Matsueda [0025]).
Matsueda describes a similar display device to Chen. Matsueda teaches a larger channel width in a low density region for the advantage of higher luminance to compensate for lower pixel density (Matsueda [0027]). This is analogous to the first display region of the instant application, wherein the effective light-emitting area is less dense because of smaller anodes. Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to make the drive circuit channel width larger in the first display region for the advantage of higher luminance per light-emitting device.
Regarding Claim 38 – Chen modified by Han, and further modified by Matsueda, discloses all the limitations for claim 37.
The combination of Chen, Han, and Matsueda further discloses the display device according to claim 37, further comprising a sensor (photosensitive element, Chen [0049]), wherein the display panel further comprises a sensor reserved region (200, Chen [0049]), the sensor is disposed in the sensor reserved region (Chen [0049]), and the first display region also serves as the sensor reserved region (Chen [0049]).
Claims 17-18 are rejected under 35 U.S.C. 103 as being unpatentable over Chen (US 202203110705 A1, hereinafter “Chen”), in view of Yi et al (US 20220310743 A1, hereinafter “Yi”).
Regarding Claim 17 – Chen modified by Han, and further modified by Matsueda, discloses all the limitations for claim 16.
The combination of Chen, Han, and Matsueda fails to disclose an extension length of the first transparent conductive layer is less than an extension length of the second transparent conductive layer and an extension length of the third transparent conductive layer.
However, Yi discloses an extension length of the first transparent conductive layer (201, Yi Fig. 2A) is less than an extension length of the second transparent conductive layer (301, Yi Fig. 2A) and an extension length of the third transparent conductive layer (401, Yi Fig. 2A).
Yi is analogous to Chen, because they both present display panels. Yi teaches making the extension lengths and widths of the various driving line segments different from each other to reduce a risk of light interference or diffraction problems (Yi [0036]). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to vary the lengths and widths of conductive line extensions used in driving LEDs for the advantage of reducing a risk of light interference or diffraction.
Regarding Claim 18 – Chen modified by Han, and further modified by Matsueda and Yi, discloses all the limitations for claim 17.
The combination of Chen, Han, Matsueda, and Yi further discloses a line width of the first transparent conductive layer is less than a line width of the second transparent conductive layer and a line width of the third transparent conductive layer (201 drawn narrower than 301 or 401, Yi Fig. 2A).
Claim 24 is rejected under 35 U.S.C. 103 as being unpatentable over Chen (US 202203110705 A1, hereinafter “Chen”), in view of Han et al (US 20210217821 A1, hereinafter “Han”), and further in view of Matsueda (US 20220199726 A1, hereinafter “Matsueda”), and further in view of Lee et al (US 20210351259 A1, hereinafter “Lee”).
Regarding Claim 24 – Chen modified by Han, and further modified by Matsueda, discloses all the limitations for claim 23.
The combination of Chen, Han, and Matsueda fails to disclose a first data signal line of the M first data signal lines comprises a plurality of first line segments and a plurality of second line segments alternately connected, wherein an extension direction of a first line segment of the plurality of first line segments is parallel to an extension direction of the at least two adjacent first pixel circuit columns, and an extension direction of a first line segment of the plurality of second line segments intersects the extension direction of the at least two adjacent first pixel circuit columns; and an extension length of the first line segment is greater than an extension length of the second line segment.
However, Lee discloses a first data signal line of the M first data signal lines comprises a plurality of first line segments (201b, Lee [0190] and Fig. 4) and a plurality of second line segments (201a, Lee [0190] and Fig. 4) alternately connected, wherein an extension direction of a first line segment of the plurality of first line segments is parallel to an extension direction of the at least two adjacent first pixel circuit columns (parallel to pixel columns, Lee Fig. 4), and an extension direction of a first line segment of the plurality of second line segments intersects the extension direction of the at least two adjacent first pixel circuit columns (perpendicular to pixel columns, Lee Fig. 4); and an extension length of the first line segment is greater than an extension length of the second line segment (1st Segment longer than 2nd Segment).
Lee presents a display panel and device analogous to Chen. Lee teaches a zigzag pattern of data lines in the display area to reduce a dead area in the corners without a reduction in display area (Lee [0187]). Thus, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to consider using a zigzag pattern of date lines to reduce a dead area in the corners of the display.
PNG
media_image6.png
646
406
media_image6.png
Greyscale
Claims 25 and 26 are rejected under 35 U.S.C. 103 as being unpatentable over Chen (US 202203110705 A1, hereinafter “Chen”), in view of Han et al (US 20210217821 A1, hereinafter “Han”), and further in view of Matsueda (US 20220199726 A1, hereinafter “Matsueda”), and further in view of Cai et al (US 20210202885 A1, hereinafter “Cai”).
Regarding Claim 25 – Chen modified by Han, and further modified by Matsueda, discloses all the limitations for claim 22.
The combination of Chen, Han, and Matsueda further discloses the plurality of second pixel circuit groups comprise N second pixel circuit groups, wherein N denotes a positive integer (a defined quantity of units areas as in Han [0035] and Fig. 1A); each second pixel circuit group of the N second pixel circuit groups comprises M sub-pixel circuit groups (defined quantity of circuits in a unit area of region bb in Han Fig. 2A), and an mth sub-pixel circuit group of the M sub-pixel circuit groups comprises an mth first pixel circuit in a first first pixel circuit row in a same second pixel circuit group of the N second pixel circuit groups and an mth first pixel circuit in a second first pixel circuit row in the same second pixel circuit group, wherein M denotes a positive integer, and 1 ≤ m ≤ M (as in the example of Han [0057] and Fig. 2A).
The combination of Chen, Han, and Matsueda fails to disclose the first display region further comprises M first voltage signal lines, wherein an mth first voltage signal line of the M first voltage signal lines is configured to provide voltage signals for two first pixel circuits in an (m + n - 1)th sub-pixel circuit group in an nth second pixel circuit group of the N second pixel circuit groups, wherein 1 ≤ n ≤N.
However, Cai discloses the display region further comprises M first voltage signal lines (VDD lines in array example in Cai Fig. 3, described in Cai [0051]), wherein an mth first voltage signal line of the M first voltage signal lines is configured to provide voltage signals for two first pixel circuits in an (m + n - 1)th sub-pixel circuit group in an nth second pixel circuit group of the N second pixel circuit groups, wherein 1 ≤ n ≤N (VDD supplied to multiple circuit groups by way of multiple connected segments parallel and perpendicular to the column direction in Cai Fig. 3).
Like Chen, Cai presents an OLED display panel. Cai teaches connecting VDD to pixel circuits by way of staggered line segments to enable supplying a positive voltage to sub-pixel anodes in the display (Cai [0051] and Fig. 3). Therefore, it would been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to connect an array of pixel circuits by staggered line segments to enable powering them with a supply voltage.
PNG
media_image7.png
529
826
media_image7.png
Greyscale
Regarding Claim 26 – Chen modified by Han, and further modified by Matsueda, and further modified by Cai, discloses all the limitations for claim 25.
The combination of Chen, Han, Matsueda, and Cai further discloses a first voltage signal line of the M first voltage signal lines comprises a plurality of third line segments (3rd segments, annotated Cai Fig. 3) and a plurality of fourth line segments (4th segments, annotated Cai Fig. 3) alternately connected, wherein an extension direction of a third line segment of the plurality of third line segments is parallel to an extension direction of the at least two adjacent first pixel circuit columns (3rd segments parallel to the column direction, annotated Cai Fig. 3), and an extension direction of a fourth line segment of the plurality of fourth line segments intersects the extension direction of the at least two adjacent first pixel circuit columns (4th segments perpendicular to the column direction, annotated Cai Fig. 3); and wherein an extension length of the third line segment is greater than an extension length of the fourth line segment (3rd Segments longer than 4th segments, annotated Cai Fig. 3).
Response to Arguments
Applicant's arguments filed 23 January 2026 have been fully considered but they are not persuasive.
The applicant argues that Matsueda fails to teach modification of the channel width to length ratio in a drive transistor. The examiner respectfully disagrees, as the drain current of a transistor is inherently dependent on the ratio of channel width to length. This is well-known in the industry. Matsueda teaches the drive current is increased by increasing the channel width. This teaching inherently means the channel width to length ratio was increased, because the drive current increases. To produce this result, the channel length was either not increased, or increased to a lesser percentage than the width, making the channel width to length ratio increase to produce mode drive (drain) current.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JASON MCDONALD whose telephone number is (571) 272-5944. The examiner can normally be reached M-F 8a-6p Eastern, alternating Fridays out of office.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio Maldonado can be reached at (571) 272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/JASON MCDONALD/Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
Prosecution Insights