DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 11 October 2022, 16 March 2023 and 25 April 2024 were filed prior to the mailing date of this office correspondence. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Election/Restrictions
Applicant’s election without traverse of Invention II, claims 1-15 in the reply filed on 17 December 2025 is acknowledged.
Claim 16 is withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Invention I, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 17 December 2025.
Claim Objections
Claims 4-7 are objected to because of the following informalities:
In claim 4, lines 3-4: “when the performing heat treatment is performed is less than 12 nm” should read:
-- when performing the heat treatment is less than 12 nm --
In claim 5, lines 2-3: “after the performing heat treatment.” should read:
-- after performing the heat treatment. --
In claim 6, “further comprises implanting ions from the bonded surface of the piezoelectric wafers to a depth that becomes the delamination interface prior to the bonding.” should read:
-- further comprises, prior to the bonding, implanting ions from the surface of the piezoelectric wafers to a depth that becomes a delamination interface. --
In claim 7, “wherein the ion species implanted in the implanting ions is” should read:
-- wherein the ion species implanted in the ion implantation is --
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-15 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation "the non-bonded surface" in line 6. There is insufficient antecedent basis for this limitation in the claim.
Claim 4 recites the limitation "the roughness" in line 3. There is insufficient antecedent basis for this limitation in the claim.
Claim 6 recites the limitation " the delamination interface" in line 3. There is insufficient antecedent basis for this limitation in the claim.
Claim 11 recites the limitation "the roughness" in line 2. There is insufficient antecedent basis for this limitation in the claim.
Claims 2-15 depend on claim 1. Therefore, claims 1-15 are rejected.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 3 and 5-15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Akiyama (WO 2018088093, see US 20200058842 for English Translation).
[AltContent: textbox (support wafer)][AltContent: ][AltContent: ][AltContent: textbox (mirror surface)][AltContent: textbox (piezoelectric wafer)][AltContent: arrow]
PNG
media_image1.png
564
541
media_image1.png
Greyscale
Annotated Fig. 6, Akiyama.
Regarding claim 1, Akiyama teaches, a manufacturing method of a composite substrate (composite substrate 1, Fig. 7, see TI, Abstract, and Figs. 5 to 8) in which a piezoelectric wafer (piezoelectric single crystal substrate 200, see annotated Fig. 6), which is a lithium tantalate wafer or lithium niobate wafer (piezoelectric single crystal substrate 200…, such as lithium tantalate (LT) and lithium niobate (LN), para. [0077]), and a support wafer (support substrate 100) are bonded together (see Fig. 6(a)), comprising:
bonding the piezoelectric wafer and the support wafer (the composite substrate 1 having the piezoelectric single crystal substrate 200 joined to the support substrate 100, para. [0085]); and
performing heat treatment (two substrates were bonded to each other and subjected to heat treatment at a temperature of 120° C., and then the LT was ground and polished to reduce the thickness, para. [0091]) of the wafer bonded in the bonding, with the non-bonded surface of the piezoelectric wafer being a mirror surface (subsequently, the piezoelectric single crystal substrate 200 is ground and polished, Fig. 6(b), para. [0084], after polishing to provide a mirror surface, para. [0139]).
Regarding claim 3, Akiyama teaches the recited limitations with respect to claim 1. Akiyama further teaches, the manufacturing method as claimed in claim 1, further comprises mirroring the non-bonded surface of the piezoelectric wafer after the bonding (bonded to the surface of the second intermediate layer 320… Subsequently, the piezoelectric single crystal substrate 200 is ground and polished, see Figs. 6(a) and 6(b), para. [0083-0084]).
Regarding claim 5, Akiyama teaches the recited limitations with respect to claim 1. Akiyama further teaches, the manufacturing method as claimed in claim 1, further comprises thinning the piezoelectric wafers (heating the bonded substrates at a low temperature (e.g., 120° C.)…the thickness of the piezoelectric single crystal substrate 200 is reduced to a thickness of about 20 μm, para. [0083-0084]).
Regarding claim 6, Akiyama teaches the recited limitations with respect to claim 5. Akiyama further teaches, the manufacturing method as claimed in claim 5, further comprises implanting ions from the bonded surface of the piezoelectric wafers to a depth that becomes the delamination interface prior to the bonding (a process of ion implantation into the piezoelectric single crystal substrate is included prior to the step of bonding, para. [0053]).
Regarding claim 7, Akiyama teaches the recited limitations with respect to claim 6. Akiyama further teaches, the manufacturing method as claimed in claim 6, wherein the ion species implanted in the implanting ions is H+ or H2+ (in the step of performing the ion implantation process, a hydrogen ion may be implanted, para. [0054]).
Regarding claim 8, Akiyama teaches the recited limitations with respect to claim 5. Akiyama further teaches, the manufacturing method as claimed in claim 5, wherein the thinning is done by grinding and/or polishing (the piezoelectric single crystal substrate 200 is ground and polished…the thickness of the piezoelectric single crystal substrate 200 is reduced to a thickness of about 20 μm, para. [0083-0084]).
Regarding claim 9, Akiyama teaches the recited limitations with respect to claim 1. Akiyama further teaches, the manufacturing method as claimed in claim 1, further comprises forming an intervening layer on the bonded surface of the piezoelectric wafer prior to the bonding (a second intermediate layer 320 is formed…second intermediate layer 320 including an inorganic material on the surface of the piezoelectric single crystal substrate 200, see Figs. 5d and 6, para. [0078]).
Regarding claim 10, Akiyama teaches the recited limitations with respect to claim 9. Akiyama further teaches, the manufacturing method as claimed in claim 9, wherein the type of the intervening layer includes any of SiO2, SiON, SiN, or amorphous Si (the material of the second intermediate layer 320 includes any one of SiOx (e.g. SiO2),…SiN, SiON, para. [0078]).
Regarding claim 11, Akiyama teaches the recited limitations with respect to claim 10. Akiyama further teaches, the manufacturing method as claimed in claim 10, wherein the roughness of the surface of the intervening layer on the bonded surface of the piezoelectric wafer is less than 12 nm in arithmetic mean roughness Ra (LT substrate, a 200 nm SiO.sub.2 film was deposited in a thickness of about 10 μm film by PVD, the film was polished to a thickness of 50 nm, the surface was mirror-finished. It was confirmed that the surface roughness was 1.0 nm or less in RMS, para. [0139]).
Regarding claim 12, Akiyama teaches the recited limitations with respect to claim 9. Akiyama further teaches, the manufacturing method as claimed in claim 1, further comprises applying a surface activation treatment to the piezoelectric wafer (second intermediate layer 320, Fig. 5) and/or the support wafer prior to the bonding step (an activation process may be applied to at least one surface of the first intermediate layer and the second intermediate layer, and then the surface of the first intermediate layer may be bonded, para. [0046]).
Regarding claim 13, Akiyama teaches the recited limitations with respect to claim 12. Akiyama further teaches, the manufacturing method as claimed claim 12, wherein the surface activation treatment includes any of plasma activation, vacuum ion beam activation, activation by ozonated water treatment, or UV ozone treatment (the surface activation process may be any one of ozone water treatment, UV ozone treatment, ion beam treatment, and plasma treatment, para. [0047]).
Regarding claim 14, Akiyama teaches the recited limitations with respect to claim 1. Akiyama further teaches, the manufacturing method as claimed in claim 1, wherein the support wafer is selected from silicon, silicon with an oxide film, sapphire, glass, quartz, and alumina (support substrate 100 is selected from silicon, sapphire, …and silica glass, para. [0070]).
Regarding claim 15, Akiyama teaches the recited limitations with respect to claim 1. Akiyama further teaches, a composite substrate (composite substate 1, Fig. 7, para. [0077]) manufactured by the manufacturing method according to claim 1.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2 and 4 are rejected under 35 U.S.C. 103 as being unpatentable over Akiyama as applied to claim 1 above, and further in view of Nomoto (WO 2018056210).
Regarding claim 2, Akiyama does not teach, mirroring the non-bonded surface of the piezoelectric wafer prior to the bonding. However, Nomoto teaches a composite substrate 10 in Fig. 1, including a support substrate 14, a piezoelectric substrate 12 and bonding the piezoelectric substrate 12 to the support substrate 14, in which, the manufacturing method as claimed in claim 1, further comprises mirroring the non-bonded surface of the piezoelectric wafer prior to the bonding (prior to the bonding step, (a) the surface of the support substrate is polished to a finish, para. [0009]). Therefore, in view of the teachings of Nomoto, it would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to modify the method of manufacturing the composite substrate of Akiyama and to include polishing the piezoelectric wafer prior to bonding as Nomoto taught in para. [0009] so that it enables forming a piezoelectric layer having a desired pore density and surface roughness Ra as Nomoto disclosed in para. [0009].
Regarding claim 4, though, Akiyama teaches the surface roughness of piezoelectric wafer is 230 nm, Akiyama does not explicitly teach, the roughness of the non-bonded surface of the piezoelectric wafer when the performing heat treatment is less than 12 nm. However, Nomoto further teaches, the manufacturing method as claimed in claim 1, wherein the roughness of the non-bonded surface of the piezoelectric wafer when the performing heat treatment is performed is less than 12 nm in arithmetic mean roughness Ra(before directly bonding the functional substrate and the support substrate, it is preferable to (a) polish and finish the surface of the support substrate so that the number of pores present on the surface of the support substrate is 30 or less per 100 μm × 100 μm area, (b) polish and finish the surface of the support substrate so that the center line average roughness (Ra) in a measurement range of 100 μm × 140 μm on the surface of the support substrate is 1 nm or less…Similarly, to the surface of the support substrate, the surface of the functional substrate is also preferably polished to satisfy at least one of (a) to (c), para. [0009, 0024]). Therefore, in view of the teachings of Nomoto, it would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to modify the method of manufacturing the composite substrate of Akiyama and to include polishing the piezoelectric wafer prior to bonding as Nomoto taught in para. [0024] so that it enables forming a piezoelectric layer having a desired pore density and surface roughness Ra as Nomoto disclosed in para. [0009].
Conclusion
Prior art Akiyama (US 20190097596) teaches a manufacturing method of a composite substrate comprising bonding a lithium tantalate wafer or lithium niobate wafer and a support wafer; and performing heat treatment of the wafer bonded in the bonding, with the non-bonded surface of the piezoelectric wafer being a mirror surface.
Prior art Iwamoto (US 20140130319) teaches a composite substrate comprising bonding a piezoelectric wafer and a support wafer; and performing heat treatment of the wafer bonded in the bonding, with the non-bonded surface of the piezoelectric wafer being a mirror surface.
Prior art Ito (US 20130307372) teaches a composite substrate including bonding a piezoelectric wafer and a support wafer; and performing heat treatment of the wafer bonded in the bonding, with the non-bonded surface of the piezoelectric wafer being a mirror surface.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOSE K. ABRAHAM whose telephone number is (571)270-1087. The examiner can normally be reached Monday-Friday 8:30-4:30 EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, THOMAS J. HONG can be reached at (571) 272-0993. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/JOSE K ABRAHAM/Examiner, Art Unit 3729