DETAILED ACTION
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The amendment with respect to claims 1, 9,11, and 17 filed on 01/23/2026 have been fully considered for examination based on their merits. The previously presented claims 4-8, 10, 12-16, and 18-20 have been considered. Claims 2-3 are canceled.
Response to Arguments
Applicant’s arguments, see Remarks, pages 8-17, filed 01/23/2026, with respect to claim(s) 1, and 4-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1, and 4-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Taichi Karino et al, (hereinafter KARINO), US 20150200309 A1, in view of Jae Hoon Park et al, (hereinafter PARK), US 20150187868 A1.
Regarding Claim 1, KARINO teaches a semiconductor device (Fig. 1, 100, high voltage JFET) comprising:
a semiconductor chip (Fig. 2A, 102/103, first/second JFET part) which has a main surface (Fig. 2A, 1, p-semiconductor substrate);
a high potential region (Fig. 2A, 5/8, n-drain region/n+ drain region) which is formed in a surface layer portion of the main surface (Fig. 2A, 1, p-semiconductor substrate);
a low potential region (Fig. 2A, 3/7, n-source region/n+ source region) which is formed in the surface layer portion of the main surface (Fig. 2A, 1, p-semiconductor substrate) at an interval (annotated Figure 2A) from the high potential region (Fig. 2A, 5/8, n-drain region/n+ drain region);
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a drift region of a first conductivity type (Fig. 2A, 4, n-drift region) which is formed as a current path ([0084]) in a region (Fig. 2A, p-floating region, [0084]) between the high potential region (Fig. 2A, 5/8, n-drain region/n+ drain region) and the low potential region (Fig. 2A, 5/8, n-drain region/n+ drain region) in the surface layer portion of the main surface (Fig. 2A, 1, p-semiconductor substrate); and
resurf regions of the first conductivity type which have a first conductivity type impurity concentration higher than a first conductivity type impurity concentration of the drift region, and which are formed partially in a surface layer portion of the drift region as current paths having a resistance lower than a resistance of the drift region (Fig. 2A, RESURF (structurally similar to p-floating region, 18, but not functionally similar to p-floating region and its conductivity type) structure lowers the resistance and the ON resistance further meaning, a higher doping concentration than the drift region and with n-type impurities similar to drift region; [0089]);
wherein the resurf regions (Fig. 2A, RESURF (structurally similar to p-floating region, 18, but not functionally similar to p-floating region and its conductivity type) structure; [0089]) are formed in the surface layer portion of the drift region (Fig. 2A, 4, n-drift region) at an interval from each other (annotated Figure 2A),
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the resurf regions (Fig. 2A, RESURF (structurally similar to p-floating region, 18, but not functionally similar to p-floating region and its conductivity type) structure; [0089]) are each formed as a line extending in an opposing direction in which the high potential region (Fig. 2A, 5/8, n-drain region/n+ drain region) and the low potential region (Fig. 2A, 3/7, n-source region/n+ source region) oppose each other, and expose a part (annotated Figure 2A) of the drift region (Fig. 2A, 4, n-drift region) as a line from the main surface (Fig. 2A, 1, p-semiconductor substrate), and
the resurf regions (Fig. 2A, RESURF (structurally similar to p-floating region, 18, but not functionally similar to p-floating region and its conductivity type) are formed in the surface layer portion of the drift region (Fig. 2A, 4, n-drift region) at an interval (annotated Figure 2A) from a bottom portion of the drift region (Fig. 2A, 4, n-drift region) toward the main surface (Fig. 2A, 1, p-semiconductor substrate) and exposed from the main surface (Fig. 2A, 1, p-semiconductor substrate).
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Though KARINO teaches the resurf regions similar to p-floating region (18), which is of second type conductivity, but based on the lower resistance and the ON resistance of the resurf region, [0089], the resurf region is believed to possess higher impurity concentration than the drift region with similar first type conductivity, such as n-type.
However, KARINO does not explicitly disclose or suggest that a semiconductor device comprising: resurf regions of the first conductivity type which have a first conductivity type impurity concentration higher than a first conductivity type impurity concentration of the drift region, and which are formed partially in a surface layer portion of the drift region as current paths the drift region.
PARK teaches a semiconductor device (Fig. 1, power semiconductor device, [0035]) comprising:
resurf regions (Fig. 1, 180, [0082-0083]) of the first conductivity which have a first conductivity type (Fig. 1, 180a, n-type first semiconductor region, [0027], [0083]) impurity concentration higher than a first conductivity type impurity concentration of the drift region, and which are formed partially in a surface layer portion of the drift region (Fig. 1, 110, drift region may be formed by injecting an n-type impurity at a low concentration, [0051]) as current paths the drift region ([0008], [0110]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have modified KARINO to incorporate the teachings of PARK such that a semiconductor device comprising: a semiconductor device comprising: resurf regions of the first conductivity type which have a first conductivity type impurity concentration higher than a first conductivity type impurity concentration of the drift region, and which are formed partially in a surface layer portion of the drift region as current paths the drift region. This enables the active area in which the current may flow may be maximized in the power semiconductor device, thereby improving performance of the semiconductor device (PARK, [0110]).
Regarding Claim 4, KARINO as modified by PARK teaches the semiconductor device according to Claim 1.
PARK further teaches the semiconductor device (Fig. 1, power semiconductor device, [0035]), wherein
the resurf regions (Fig. 1, 180, [0082-0083]) are formed in a striped shape (Fig. 1, 180 or 180a/180b, [0094]) extending in the opposing direction (Fig. 1, X or -X direction) and expose a part of the drift region (Fig. 1, 110, drift region may be formed by injecting an n-type impurity at a low concentration, [0051]) in a striped shape (Fig. 1, 180 or 180a/180b, [0094]) from the main surface (Fig. 1, 111, buffer region).
Regarding Claim 5, KARINO as modified by PARK teaches the semiconductor device according to Claim 1.
PARK further teaches the semiconductor device (Fig. 1, power semiconductor device, [0035]), further comprising:
a field insulating film (Fig. 1, 161, insulating film) which covers the drift region (Fig. 1, 110, drift region may be formed by injecting an n-type impurity at a low concentration, [0051]) and the resurf regions (Fig. 1, 180, [0082-0083]) on the main surface (Fig. 1, 111, buffer region, and
KARINO further teaches a semiconductor device (Fig. 1, 100, high voltage JFET), further comprising:
a field electrode (Figs. 10A/10B, 80, polysilicon electrode) which is led around as a line on the field insulating film (Fig. 10B, 81, interlayer insulating layer) and traverses the resurf region (Figs. 2A/10B, RESURF (structurally similar to p-floating region, 18, but not functionally similar to p-floating region and its conductivity type); [0008]) in a plan view (Fig 10A, 81 (not explicitly shown), [0008]).
Regarding Claim 6 KARINO as modified by PARK teaches the semiconductor device according to Claim 5.
KARINO further teaches a semiconductor device (Fig. 1, 100, high voltage JFET), wherein
the field electrode (Figs. 10A/10B, 80, polysilicon electrode) traverses the resurf regions multiple times in a plan view (Figs. 2A/10B, RESURF (structurally similar to p-floating region, 18, but not functionally similar to p-floating region and its conductivity type); 79, LOCOS oxide film, [0008]).
Regarding Claim 7, KARINO as modified by PARK teaches the semiconductor device according to Claim 5.
KARINO further teaches a semiconductor device (Fig. 1, 100, high voltage JFET), wherein
the field electrode (Figs. 10A/10B, 80, polysilicon electrode) surrounds the high potential region multiple times (Figs. 10A/10B, 75/78, n-drain region/n+ drain region, [0008]).
Regarding Claim 8, KARINO as modified by PARK teaches the semiconductor device according to Claim 5.
KARINO further teaches the semiconductor device (Fig. 1, 100, high voltage JFET), wherein
the field electrode (Figs. 10A/10B, 80, polysilicon electrode) is constituted of a field resistance film (Fig. 10B, 79, LOCOS oxide film, [0008]) which is electrically connected to the high potential region and the low potential region (Figs. 10A/10B, [0008], [0079]).
Regarding Claim 9, KARINO as modified by PARK teaches the semiconductor device according to Claim 5.
KARINO further teaches the semiconductor device (Fig. 1, 100, high voltage JFET) wherein
the high potential region includes a drain region of the first conductivity type (Fig. 2A, 5/8, n-drain region/n+ drain region) which is formed in a surface layer portion of the main surface (Fig. 2A, 1, p-semiconductor substrate);
the low potential region includes a body region of a second conductivity type (Fig. 2A, 2/6, p-gate region/p+ gate region) which is formed in the surface layer portion of the main surface (Fig. 2A, 1, p-semiconductor substrate) and a source region of the first conductivity type (Fig. 2A, 3/7, n-source region/n+ source region) which is formed in a surface layer (Fig. 2A, 19, pn junction) of the body region (Fig. 2A, 2/6, p-gate region/p+ gate region),
the drift region (Fig. 1, 110) is formed in a region between the drain region (Fig. 2A, 5/8, n-drain region/n+ drain region) and the body region (Fig. 2A, 2/6, p-gate region/p+ gate region) in the surface layer portion of the main surface (Fig. 2A, 1, p-semiconductor substrate), and
the resurf regions (Fig. 2A, RESURF (structurally similar to p-floating region, 18, but not functionally similar to p-floating region and its conductivity type) structure; [0089]) are formed in a region between the drain region (Fig. 2A, 5/8, n-drain region/n+ drain region) and the source region (Fig. 2A, 3/7, n-source region/n+ source region) in the surface layer portion of the drift region (Fig. 2A, 4, n-drift region).
Regarding Claim 10, KARINO as modified by PARK teaches the semiconductor device according to Claim 9.
PARK further teaches the semiconductor device (Fig. 1, power semiconductor device, [0035]), wherein
the resurf regions (Fig. 1, 180) are connected to the body region (Fig. 1, 181, deep body region).
Regarding Claim 11, KARINO as modified by PARK teaches the semiconductor device according to Claim 9.
KARINO further teaches the semiconductor device (Fig. 1, 100, high voltage JFET) wherein
the high potential region (Fig. 2A, VH, high voltage terminal) includes a well region of the first conductivity type (Fig. 2A, 5, n-drain region) which is formed in the surface layer portion of the main surface (Fig. 2A, 1, p-semiconductor substrate) and the drain region (Fig. 2A, 8, n+ drain region) which is formed in a surface layer portion of the well region (Fig. 2A, 5, n-drain region), and
the resurf regions (Fig. 2A, RESURF (structurally similar to p-floating region, 18, but not functionally similar to p-floating region and its conductivity type) structure; [0089]) are formed in a region between the well region (Fig. 2A, 5, n-drain region) and the source region (Fig. 2A, 3/7, n-source region/n+ source region) in the surface layer portion of the drift region (Fig. 1, 110).
Regarding Claim 12, KARINO as modified by PARK teaches the semiconductor device according to Claim 11.
KARINO further teaches the semiconductor device (Fig. 1, 100, high voltage JFET) wherein
the resurf regions (Fig. 2A, RESURF (structurally similar to p-floating region, 18, but not functionally similar to p-floating region and its conductivity type) structure; [0089]) are connected to the well region (Fig. 2A, 5, n-drain region).
Regarding Claim 13, KARINO as modified by PARK teaches the semiconductor device according to Claim 9.
KARINO further teaches the semiconductor device (Fig. 1, 100, high voltage JFET) wherein
the resurf regions (Fig. 2A, RESURF (structurally similar to p-floating region, 18, but not functionally similar to p-floating region and its conductivity type) structure; [0089]) are formed only in a region sandwiched between the source region (Fig. 2A, 3/7, n-source region/n+ source region) and the drain region (Fig. 2A, 8, n+ drain region) in the drift region (Fig. 1, 110).
Regarding Claim 14, KARINO as modified by PARK teaches the semiconductor device according to Claim .
KARINO further teaches the semiconductor device (Fig. 1, 100, high voltage JFET) wherein
the body region (Figs. 1/2A, 2/6, p-gate region/p+ gate region) surrounds the drain region (Figs. 1/2A, 8, n+ drain region), and the source region is formed (Figs. 1/2A, 3/7, n-source region/n+ source region) in a shape (Fig. 1, circular shape, [0009]) having ends in the surface layer portion of the body region (Figs. 1/2A, 2/6, p-gate region/p+ gate region).
Regarding Claim 15, KARINO as modified by PARK teaches the semiconductor device according to Claim 9.
PARK further teaches the semiconductor device (Fig. 1, power semiconductor device, [0035]), further comprising:
a channel region (Fig. 1, 140/142, conductive material in the trench gate, channel C formed, [0068-0070]) which is formed between the drift region (Fig. 1, 110) and the source region (Fig. 1, 130, emitter region) in the surface layer portion of the body region (Fig. 1, 120),
a gate insulating film (Fig. 1, 141, gate insulating layer) which covers the channel region (Fig. 1, 140/142, conductive material in the trench gate, channel C formed, [0068-0070]) on the main surface (Fig. 111, buffer region), and
a gate electrode (Fig. 1, 142, [0067])which is formed on the gate insulating film (Fig. 1, 141, gate insulating layer).
Regarding Claim 16, KARINO as modified by PARK teaches the semiconductor device according to Claim 15.
KARINO further teaches the semiconductor device (Fig. 1, 100, high voltage JFET) wherein
the gate insulating film (Fig. 2A, 11, interlayer insulating film) covers the drift region (Fig. 1, 110) and the resurf regions (Fig. 2A, RESURF (structurally similar to p-floating region, 18, but not functionally similar to p-floating region and its conductivity type) structure; [0089]).
Regarding Claim 17, KARINO teaches a semiconductor device (Fig. 1, 100, high voltage JFET) comprising:
a semiconductor chip (Fig. 2A, 102/103, first/second JFET part) which has a main surface (Fig. 2A, 1, p-semiconductor substrate);
a high potential region (Fig. 2A, 5/8, n-drain region/n+ drain region) which is formed in a surface layer portion of the main surface (Fig. 2A, 1, p-semiconductor substrate);
a drift region of a first conductivity type (Fig. 2A, 4, n-drift region) which is formed as a current path ([0084]) in a region (Fig. 2A, p-floating region, [0084]) between the high potential region (Fig. 2A, 5/8, n-drain region/n+ drain region) and the low potential region (Fig. 2A, 5/8, n-drain region/n+ drain region) in the surface layer portion of the main surface (Fig. 2A, 1, p-semiconductor substrate);
resurf regions of the first conductivity type which have a first conductivity type impurity concentration higher than a first conductivity type impurity concentration of the drift region, and which are formed partially in a surface layer portion of the drift region as current paths having a resistance lower than a resistance of the drift region (Fig. 2A, RESURF (structurally similar to p-floating region, 18, but not functionally similar to p-floating region and its conductivity type) structure lowers the resistance and the ON resistance further meaning, a higher doping concentration than the drift region and with n-type impurities similar to drift region; [0089]) and extends as a line in an opposing direction in which the high potential region (Fig. 2A, 5/8, n-drain region/n+ drain region) and the low potential region (Fig. 2A, 3/7, n-source region/n+ source region) oppose each other, and expose a part (annotated Figure 2A) of the drift region (Fig. 2A, 4, n-drift region) as a line from the main surface (Fig. 2A, 1, p-semiconductor substrate),
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a field insulating film (Fig. 10B, 81, interlayer insulating layer) which covers the drift region (Fig. 10B, 74) and the resurf regions (Figs. 2A/10B, RESURF (structurally similar to p-floating region, 18, but not functionally similar to p-floating region and its conductivity type); [0008]), and
a field electrode (Figs. 10A/10B, 80, polysilicon electrode) which is led around as a line on the field insulating film (Fig. 10B, 81, interlayer insulating layer) and traverses the resurf region (Figs. 2A/10B, RESURF (structurally similar to p-floating region, 18, but not functionally similar to p-floating region and its conductivity type); [0008]) in a plan view (Fig 10A, 81 (not explicitly shown), [0008]).
wherein the resurf regions (Fig. 2A, RESURF (structurally similar to p-floating region, 18, but not functionally similar to p-floating region and its conductivity type) structure; [0089]) are formed in the surface layer portion of the drift region (Fig. 2A, 4, n-drift region) at an interval from each other (annotated Figure 2A), and
the resurf regions (Fig. 2A, RESURF (structurally similar to p-floating region, 18, but not functionally similar to p-floating region and its conductivity type) are formed in the surface layer portion of the drift region (Fig. 2A, 4, n-drift region) at an interval (annotated Figure 2A) from a bottom portion of the drift region (Fig. 2A, 4, n-drift region) toward the main surface (Fig. 2A, 1, p-semiconductor substrate) and exposed from the main surface (Fig. 2A, 1, p-semiconductor substrate).
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Though KARINO teaches the resurf regions similar to p-floating region (18), which is of second type conductivity, but based on the lower resistance and the ON resistance of the resurf region, [0089], the resurf region is believed to possess higher impurity concentration than the drift region with similar first type conductivity, such as n-type.
However, KARINO does not explicitly disclose or suggest that a semiconductor device comprising: resurf regions of the first conductivity type which have a first conductivity type impurity concentration higher than a first conductivity type impurity concentration of the drift region, and which are formed partially in a surface layer portion of the drift region as current paths the drift region.
PARK teaches a semiconductor device (Fig. 1, power semiconductor device, [0035]) comprising:
resurf regions (Fig. 1, 180, [0082-0083]) of the first conductivity which have a first conductivity type (Fig. 1, 180a, n-type first semiconductor region, [0027], [0083]) impurity concentration higher than a first conductivity type impurity concentration of the drift region, and which are formed partially in a surface layer portion of the drift region (Fig. 1, 110, drift region may be formed by injecting an n-type impurity at a low concentration, [0051]) as current paths the drift region ([0008], [0110]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have modified KARINO to incorporate the teachings of PARK such that a semiconductor device comprising: a semiconductor device comprising: resurf regions of the first conductivity type which have a first conductivity type impurity concentration higher than a first conductivity type impurity concentration of the drift region, and which are formed partially in a surface layer portion of the drift region as current paths the drift region. This enables the active area in which the current may flow may be maximized in the power semiconductor device, thereby improving performance of the semiconductor device (PARK, [0110]).
Regarding Claim 18, KARINO as modified by PARK teaches the semiconductor device according to Claim 17.
KARINO further teaches the semiconductor device (Fig. 1, 100, high voltage JFET), wherein
the field electrode (Figs. 10A/10B, 80, polysilicon electrode) is constituted of a field resistance film (Fig. 10B, 79, LOCOS oxide film, [0008]) which is electrically connected to the high potential region and the low potential region (Figs. 10A/10B, [0008], [0079]).
Regarding Claim 19, KARINO as modified by PARK teaches the semiconductor device according to Claim 17.
KARINO further teaches the semiconductor device (Fig. 1, 100, high voltage JFET), wherein
the field electrode (Fig. 1, 10, polysilicon gate electrode) has a portion which extends in a direction orthogonal to the resurf regions in a plan view (Figs. 1, RESURF (structurally similar to p-floating region, 18, but not functionally similar to p-floating region and its conductivity type); [0008]).
Regarding Claim 20, KARINO as modified by PARK teaches the semiconductor device according to Claim 1.
PARK teaches a semiconductor device (Fig. 1, power semiconductor device, [0035]) wherein
the resurf regions (Fig. 1, 180) each have a long side which extends in the opposing direction (Fig. 1, X direction or -X direction), and a short side (Fig. 1, Z direction or -Z direction) which is shorter than the long side (Fig. 1, Z direction of 180 << X direction of 180) and extends in an intersecting direction that intersects the opposing direction (Fig. 1, X/-X direction perpendicular to Z/-Z direction).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 20120043608 A1 – Figure 1
STATEMENT OF RELEVANCE – n-Well (110) defines a drift region for the NLDMOS structure (100) and n-RESURF (104) may be buried layer, RESURF layer; both drift region and RESURF layer have first type conductivity, for example: n-type.
US 20130037851 A1 – Figure 1
STATEMENT OF RELEVANCE – n (negative) type base layer and the n type RESURF layer both exhibit first type conductivity, wherein the RESURF layer has higher impurity (n) than the drift region (n-) and thus lower the resistance of the RESURF layer.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SESHA SAIRAMAN SRINIVASAN whose telephone number is (703)756-1389. The examiner can normally be reached Monday-Friday 7:30 AM -5:30 PM.
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/SESHA SAIRAMAN SRINIVASAN/Examiner, Art Unit 2817
/MARLON T FLETCHER/Supervisory Primary Examiner, Art Unit 2817
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