DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
1. Claims 1-16 are present for examination on 8/1/22.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
2. Claims 2, 4, 6-7, 9, 11-13 and 16 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 2, line 3, the phrase “wherein a drain of the first MOS transistor is connected to a first high level” is vague and indefinite. Does the “first high level” imply a high voltage level from a power supply? Or does it imply a voltage level from any other signal going through the drain terminal? Similarly, on line 5, the term “a first low level” is also similarly confusing since it does not particularly point out where is the source for this “low level”?
Claim 4, lines 3 & 5, for the same reason as claim 2 above, both the terms “a second high level” and “a second low level” also needs a clear introduction or where they come from.
Similarly, other claims 6-7 and 11-13 also contain the terms first or second high level and first or second low level, which also need proper antecedent basis.
Claim 9, line 1, the word “selecti” is mis-spelled.
Claim 9, last two lines, “the storage circuit” lacks a clear antecedent basis. Does it imply “the preset storage circuit” already recited on line 6?
Claim 16, line 1, the term “a computer-readable storage medium” should be revised as “a non-transitory computer-readable storage medium” as required by USPTO, see MPEP, section 35 USC 101 for further guidelines on the statutory subject matter definition.
Allowable Subject Matter
3. The following claims are allowable over prior arts of record for tentatively contain novel limitations, which are not clearly ungated by the prior arts cited heroin nor seen elsewhere at this time:
The independent claims 1 & 10 recites an apparatus and a method for generating a chip select signal, which comprise the following novel steps:
- receiving an external control signal input from a chip select port, and sampling the external control signal to obtain a first sampling signal and a second sampling signal;
- inputting the first sampling signal into a first vector file to generate a power supply control signal, and
- inputting the second sampling signal into a second vector file to generate a chip select control signal; wherein the power supply control signal and the chip select control signal comprise a high potential, a low potential and a high impedance state, and wherein the voltage values of the high potential of the power supply control signal and the chip select control signal are different, and wherein the voltage values of the low potential of the power supply control signal and the chip select control signal are different; and wherein the chip select signal is generated based on the power supply control signal and the chip select control signal, and wherein the chip select signal performs a power supply control operation and a chip select operation.
Additionally, except for the pending 112 issues as discussed above, all the dependent claims 2-9 & 11-16 further recite other novel limitations, which are also not clearly suggested by the prior arts cited herein nor seen elsewhere at this time.
4. Any inquiry concerning this communication or earlier communications from the examiner should be directed to VIET Q NGUYEN whose telephone number is (571)272-1788. The examiner can normally be reached M-F 7:30-3PM EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amir Zarabian can be reached at 571-272-1852. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/VIET Q NGUYEN/Primary Examiner, Art Unit 2827