DETAILED ACTION
Notice of Pre-AIA or AIA Status
Response to Amendment
(Submitted on 12/5/2025)
Applicant’s arguments with respect to claims 1, 5 and 6 been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. The examiner has mapped using new reference or more pertinent references from last Office Action to dependent claims that are not amended so as to ensure consistency of the rejections within the context of the new focus theme due to the amended independent claims.
In regard to 103 rejections
- On Page 8, the applicant cites the current prior arts used for rejecting the claims in the last Office Action. The applicant submits that the claims 1-6, 12, 13 and 19 have been amended and claim 7 is CANCELED.
- On Pages 9-14, the applicant argues the obviousness of the prior art in the last Office Action.
Examiner’s Response:
The examiner submits that the applicant argument is moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. The examiner uses two new references “AOUDIA” and “Shaked” and “Bila” to teach the amendments.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 5-6, 8-11, 15-18 and 20-21 are rejected under 35 U.S.C. 103 as being unpatentable over in view of AIT AOUDIA et.al. (hereinafter AOUDIA) US 2021/0211163 A1 [Foreign Priority: FI , 20205014, Filed: 2020-01-08], in view of Ohad Barsimantov (hereinafter Barsi) US 2020/0205771 A1.
In regard to claim 1: (Currently Amended)
AOUDIA discloses:
A computer implemented method for leaning a neural network, comprising: a learning a neural network using learning data including:
In [0034] :
The embodiments may employ one or more neural networks for machine learning. Neural networks (or specifically artificial neural networks) are computing systems comprised of highly interconnected “neurons” capable of information processing due to their dynamic state response to external inputs
In [0083]:
The apparatus combines, in block 501, a received digital signal with a digital dithering signal to produce a first combined digital signal. The apparatus may maintain said received digital signal
In [0083]:
received digital signal (or a plurality of received digital signals comprising said received digital signal) acting as training data in a memory of the apparatus
receiving, as an input digital signal, the low-bit signal and creating an estimated output signal by transforming the low-bit
In [0084]:
the processing in block 506 may comprise reconstructing the received digital signal with a resolution higher than the resolution of the second combined digital signal based on the second combined digital signal or performing bit-to-symbol demapping on the second combined digital signal. The apparatus calculates, in block 507, a value of a loss function. The loss function may be calculated at least based on the results of the processing and corresponding known target data associated with the received digital signal (e.g., the received digital signal itself or a sequence of bits corresponding to a transmitted signal).
In [0078]:
The binary cross entropy function measures how far away from the true value a prediction is. Specifically, binary cross-entropy function provides a measure of the difference between two probability distributions for a given binary random variable (here, corresponding to bits in a transmitted digital signal).
(BRI: the corresponding known target is what is quantized as a high-bit signal) and the estimated signal is the what is provided by entropy function that measures the difference )
and learning a parameter of the neural network by minimizing difference between the estimated output signal and the high-bit signal according to a value of a loss function by performing iterative backpropagation operations, the learnt neural network comprises
a multilayer structure including an input layer and an output layer, and
in [0035]:
multilayer perceptron network is a basic form a feedforward neural network and typically consists of an input layer, one or more hidden layers and an output layer
in [0074]:
To enable the training of the machine-learning algorithm 404, a value of a loss function is calculated in element 407. The loss function takes as its input the received digital signal y and a reconstructed received digital signal (i.e., the output of the signal reconstruction element 406).
In [0078]:
The binary cross entropy function measures how far away from the true value a prediction is. Specifically, binary cross-entropy function provides a measure of the difference between two probability distributions for a given binary random variable (here, corresponding to bits in a transmitted digital signal).
In [0109]:
The apparatus updates, in block 706, the parameters (or weights) of the neural network (i.e., in each copy of the neural network) by applying one step of stochastic gradient descent (SGD) on the total loss L for the batch B. The gradient descent is a first-order iterative optimization algorithm used to minimize a function by iteratively moving in the direction of steepest descent as defined by the negative of the gradient.
In [0035]:
The network uses forward passes and backpropagation to learn the weights and bias. Forward passes (from input to output) calculate the outputs, while backpropagation calculates the necessary updates for the weights and biases based on the error at the output layer.
- wherein the learnt neural network receives an input signal the [[a]] low-bit input signal and high-bit output signal obtained
In [0084]:
the processing in block 506 may comprise reconstructing the received digital signal with a resolution higher than the resolution of the second combined digital signal based on the second combined digital signal or performing bit-to-symbol demapping on the second combined digital signal. The apparatus calculates, in block 507, a value of a loss function. The loss function may be calculated at least based on the results of the processing and corresponding known target data associated with the received digital signal (e.g., the received digital signal itself or a sequence of bits corresponding to a transmitted signal).
(BRI: the corresponding known target is what is quantized as a high-bit signal)
as an estimated signal by quantizing the input signal to the second number of quantization bits,
In [0084]:
the processing in block 506 may comprise reconstructing the received digital signal with a resolution higher than the resolution of the second combined digital signal based on the second combined digital signal or performing bit-to-symbol demapping on the second combined digital signal. The apparatus calculates, in block 507, a value of a loss function. The loss function may be calculated at least based on the results of the processing and corresponding known target data associated with the received digital signal (e.g., the received digital signal itself or a sequence of bits corresponding to a transmitted signal).
In [0078]:
The binary cross entropy function measures how far away from the true value a prediction is. Specifically, binary cross-entropy function provides a measure of the difference between two probability distributions for a given binary random variable (here, corresponding to bits in a transmitted digital signal).
(BRI: the corresponding known target is what is quantized as a high-bit signal) and the estimated signal is the what is provided by entropy function that measures the difference )
- and the learnt neural network outputs the estimated output signal expressed in the second number of quantization bits by adding [[an]] the output signal from the output layer to input digital signal.
In [0084]:
If the second combined digital signal is processed, in block 506, by performing bit-to-symbol demapping on the second combined digital signal
In [0035]:
The network uses forward passes and backpropagation to learn the weights and bias. Forward passes (from input to output) calculate the outputs, while backpropagation calculates the necessary updates for the weights and biases based on the error at the output layer.
(BRI: the results of the loss function measured estimated is the output and the process of de-mapping a second digital signal (often a recovered or corrected signal) onto a second combined digital signal generally represents a superposition or combining operation, which can indeed be the result of adding an output signal (or correction factor) back to a reference or input digital signal.
AOUDIA does not explicitly disclose:
- a low-bit signal obtained by quantizing an analog input signal to the low-bit signal expressed in a first number of quantization bits, and a high-bit signal obtained by quantizing the analog input signal to the high-bit signal expressed in a second number of quantization bits larger than the first number of quantization bits,
However, Barsi discloses:
- a low-bit signal obtained by quantizing an analog input signal to the low-bit signal expressed in a first number of quantization bits, and a high-bit signal obtained by quantizing the analog input signal to the high-bit signal expressed in a second number of quantization bits larger than the first number of quantization bits,
In [0051]:
A BioPack MP-150 data acquisition system was used to collect and digitalize (at 2000 Hz) the analog data
In [0254]:
Analog to Digital Converter (ADC) is necessary as an input device to read analog signals.
In [0253]:
The sensitive and low noise Silicon Design Model 1221 accelerometer was used throughout the early experiments, which allowed accurate recordings and identify desired features within the acceleration signal. The signal was processed using the Bio-pack M-150 data acquisition system, which has 24-bit precision analog to digital converter. It was found that lower precision would suffice, and therefore a 16-bit ADC could be used. At least a 32-bit word and 16-bit precision should be used in the calculations.
(BRI: A 16-bit is a low-bit quantization and a 24-bit is a high bit quantization)
It would have obvious to one of ordinary skill in the art before the effective filing date of the present application to combine AOUDIA , and Barsi.
The examiner interprets the invention as “ using neural network to learn to extend the quantization and provide a high accuracy to reflect original signal in which the learning is performed by computing and inferring the loss function”.
AOUDIA teaches a method for learning, and learning device, representation of low and high signals and loss function.
Barsi teaches low-bit and high-bit quantization.
Within the context of the core of the invention, the prior art combinations teaches the invention making the case for “motivation to combine”.
Within the context of the core of the invention, the prior art combinations teaches the invention making the case for “motivation to combine”.
One of ordinary skill would have motivation to combine AOUDIA and Barsi that can reconstruct packets to reduce low and high frequence noises [Barsi [0159])
In regard to claim 5: (Currently Amended)
AOUDIA discloses:
- receiving, as an input digital signal,[[a]]the low-bit and creating an estimated output signal by transforming the low-bit signal expressed in the first number of quantization bits to the estimated output signal expressed in the second number of quantization bits,
In [0084]:
the processing in block 506 may comprise reconstructing the received digital signal with a resolution higher than the resolution of the second combined digital signal based on the second combined digital signal or performing bit-to-symbol demapping on the second combined digital signal. The apparatus calculates, in block 507, a value of a loss function. The loss function may be calculated at least based on the results of the processing and corresponding known target data associated with the received digital signal (e.g., the received digital signal itself or a sequence of bits corresponding to a transmitted signal).
In [0078]:
The binary cross entropy function measures how far away from the true value a prediction is. Specifically, binary cross-entropy function provides a measure of the difference between two probability distributions for a given binary random variable (here, corresponding to bits in a transmitted digital signal).
(BRI: the corresponding known target is what is quantized as a high-bit signal) and the estimated signal is the what is provided by entropy function that measures the difference )
- A learning device comprising a processor configured to execute operations comprising: learning a neural network that uses learning data, wherein the learning data comprises
In [0034] :
The embodiments may employ one or more neural networks for machine learning. Neural networks (or specifically artificial neural networks) are computing systems comprised of highly interconnected “neurons” capable of information processing due to their dynamic state response to external inputs
In [0083]:
The apparatus combines, in block 501, a received digital signal with a digital dithering signal to produce a first combined digital signal. The apparatus may maintain said received digital signal
In [0083]:
received digital signal (or a plurality of received digital signals comprising said received digital signal) acting as training data in a memory of the apparatus
(BRI: the apparatus is the learning device)
- learning a parameter of the neural network by minimizing difference between the estimated output signal and the high-bit signal according to a value of a loss function by performing iterative backpropagation operations, the learnt neural network comprises a multilayer structure including an input layer and an output layer,
in [0035]:
multilayer perceptron network is a basic form a feedforward neural network and typically consists of an input layer, one or more hidden layers and an output layer
in [0074]:
To enable the training of the machine-learning algorithm 404, a value of a loss function is calculated in element 407. The loss function takes as its input the received digital signal y and a reconstructed received digital signal (i.e., the output of the signal reconstruction element 406).
In [0078]:
The binary cross entropy function measures how far away from the true value a prediction is. Specifically, binary cross-entropy function provides a measure of the difference between two probability distributions for a given binary random variable (here, corresponding to bits in a transmitted digital signal).
In [0109]:
The apparatus updates, in block 706, the parameters (or weights) of the neural network (i.e., in each copy of the neural network) by applying one step of stochastic gradient descent (SGD) on the total loss L for the batch B. The gradient descent is a first-order iterative optimization algorithm used to minimize a function by iteratively moving in the direction of steepest descent as defined by the negative of the gradient.
In [0035]:
The network uses forward passes and backpropagation to learn the weights and bias. Forward passes (from input to output) calculate the outputs, while backpropagation calculates the necessary updates for the weights and biases based on the error at the output layer.
- the learnt neural network outputs [[an]] the estimated output signal expressed in the second number of quantization bits by adding the output digital signal from the output layer to the input digital signal.
In [0084]:
If the second combined digital signal is processed, in block 506, by performing bit-to-symbol demapping on the second combined digital signal
In [0035]:
The network uses forward passes and backpropagation to learn the weights and bias. Forward passes (from input to output) calculate the outputs, while backpropagation calculates the necessary updates for the weights and biases based on the error at the output layer.
(BRI: the results of the loss function measured estimated is the output and the process of de-mapping a second digital signal (often a recovered or corrected signal) onto a second combined digital signal generally represents a superposition or combining operation, which can indeed be the result of adding an output signal (or correction factor) back to a reference or input digital signal).
AOUDIA does not explicitly disclose:
- a low-bit signal obtained by quantizing an analog input signal to the low-bit signal expressed in a first number of quantization bits, and a high-bit signal obtained by quantizing the analog input signal to the high-bit signal expressed in a second number of quantization bits larger than the first number of quantization bits,
However, Barsi discloses:
- a low-bit signal obtained by quantizing an analog input signal to the low-bit signal expressed in a first number of quantization bits, and a high-bit signal obtained by quantizing the analog input signal to the high-bit signal expressed in a second number of quantization bits larger than the first number of quantization bits,
In [0051]:
A BioPack MP-150 data acquisition system was used to collect and digitalize (at 2000 Hz) the analog data
In [0254]:
Analog to Digital Converter (ADC) is necessary as an input device to read analog signals.
In [0253]:
The sensitive and low noise Silicon Design Model 1221 accelerometer was used throughout the early experiments, which allowed accurate recordings and identify desired features within the acceleration signal. The signal was processed using the Bio-pack M-150 data acquisition system, which has 24-bit precision analog to digital converter. It was found that lower precision would suffice, and therefore a 16-bit ADC could be used. At least a 32-bit word and 16-bit precision should be used in the calculations.
(BRI: A 16-bit is a low-bit quantization and a 24-bit is a high bit quantization)
It would have obvious to one of ordinary skill in the art before the effective filing date of the present application to combine AOUDIA , and Barsi.
The examiner interprets the invention as “ using neural network to learn to extend the quantization and provide a high accuracy to reflect original signal in which the learning is performed by computing and inferring the loss function”.
AOUDIA teaches a method for learning, and learning device, representation of low and high signals and loss function.
Barsi teaches low-bit and high-bit quantization.
Within the context of the core of the invention, the prior art combinations teaches the invention making the case for “motivation to combine”.
Within the context of the core of the invention, the prior art combinations teaches the invention making the case for “motivation to combine”.
One of ordinary skill would have motivation to combine AOUDIA and Barsi that can reconstruct packets to reduce low and high frequence noises [Barsi [0159])
In regard to claim 6: (Currently Amended)
AOUDIA discloses:
- A signal estimation device comprising a processor executing a computer-executable instructions that cause the signal estimation device to perform operations comprising:
In [0034] :
The embodiments may employ one or more neural networks for machine learning. Neural networks (or specifically artificial neural networks) are computing systems comprised of highly interconnected “neurons” capable of information processing due to their dynamic state response to external inputs
In [0083]:
The apparatus combines, in block 501, a received digital signal with a digital dithering signal to produce a first combined digital signal. The apparatus may maintain said received digital signal
In [0083]:
received digital signal (or a plurality of received digital signals comprising said received digital signal) acting as training data in a memory of the apparatus
in [0084]:
The apparatus processes, in block 506, the second combined digital signal. Specifically, the processing in block 506 may comprise reconstructing the received digital signal with a resolution higher than the resolution of the second combined digital signal based on the second combined digital signal
In [0084]:
The apparatus calculates, in block 507, a value of a loss function. The loss function may be calculated at least based on the results of the processing and corresponding known target data associated with the received digital signal (e.g., the received digital signal itself or a sequence of bits corresponding to a transmitted signal). Said target data (or a plurality of sets of target data corresponding to a plurality of received digital signals) may be maintained in a memory of the apparatus. If the second combined digital signal is processed, in block 506, by reconstructing the received digital signal with a resolution higher than a resolution of the second combined digital signal based on the second combined digital signal
(BRI: the apparatus is the estimated device)
- receiving, as input to a neural network that has been trained
In [0052]:
As indicated above, the one or more extracted features are used as an input of a machine-learning algorithm implemented in element 207. Here, it is assumed that the machine-learning algorithm is already trained.
- the neural network has been further trained by learning a parameter of the neural network by minimizing difference between the estimated output signal and the high-bit signal according to a value of a loss function by performing iterative backpropagation operations,
In [0052]:
As indicated above, the one or more extracted features are used as an input of a machine-learning algorithm implemented in element 207. Here, it is assumed that the machine-learning algorithm is already trained. The training of the machine-learning algorithm is discussed below in relation to FIGS. 4, 5, 6A, 6B and 7. The trained machine-learning algorithm is used, in element 207, for calculating one or more input parameters for waveform generation at least based on the one or more features extracted from the combined digital signal by DFE 206. The trained machine-learning algorithm 207 may have been trained specifically for optimizing the performing of signal processing in element 209. The machine-learning algorithm may be a neural network (NN) (or a neural network-based algorithm employing using one or more neural networks), as illustrated in FIG. 2. Said one or more neural networks may comprise one or more feedforward neural networks and/or one or more recurrent neural networks.
In [0084]:
the processing in block 506 may comprise reconstructing the received digital signal with a resolution higher than the resolution of the second combined digital signal based on the second combined digital signal or performing bit-to-symbol demapping on the second combined digital signal. The apparatus calculates, in block 507, a value of a loss function. The loss function may be calculated at least based on the results of the processing and corresponding known target data associated with the received digital signal (e.g., the received digital signal itself or a sequence of bits corresponding to a transmitted signal).
In [0078]:
The binary cross entropy function measures how far away from the true value a prediction is. Specifically, binary cross-entropy function provides a measure of the difference between two probability distributions for a given binary random variable (here, corresponding to bits in a transmitted digital signal).
(BRI: the corresponding known target is what is quantized as a high-bit signal) and the estimated signal is the what is provided by entropy function that measures the difference )
- creating, by the neural network that has been trained, the estimated output signal expressed in the second number of quantization bits by adding an output signal from the output laver to the low-bit input signal: outputting the estimated output signal.
In [0084]:
If the second combined digital signal is processed, in block 506, by performing bit-to-symbol demapping on the second combined digital signal
In [0035]:
The network uses forward passes and backpropagation to learn the weights and bias. Forward passes (from input to output) calculate the outputs, while backpropagation calculates the necessary updates for the weights and biases based on the error at the output layer.
(BRI: the results of the loss function measured estimated is the output and the process of de-mapping a second digital signal (often a recovered or corrected signal) onto a second combined digital signal generally represents a superposition or combining operation, which can indeed be the result of adding an output signal (or correction factor) back to a reference or input digital signal)
AOUDIA does not explicitly disclose:
- a low-bit input signal obtained by quantizing an analog input signal to the low-bit input signal expressed in a first number of quantization bits
- and the second number of quantization bits larger than the first number of quantization bits;
However, Barsi discloses:
- a low-bit input signal obtained by quantizing an analog input signal to the low-bit input signal expressed in a first number of quantization bits
In [0051]:
A BioPack MP-150 data acquisition system was used to collect and digitalize (at 2000 Hz) the analog data
In [0254]:
Analog to Digital Converter (ADC) is necessary as an input device to read analog signals.
In [0253]:
The sensitive and low noise Silicon Design Model 1221 accelerometer was used throughout the early experiments, which allowed accurate recordings and identify desired features within the acceleration signal. The signal was processed using the Bio-pack M-150 data acquisition system, which has 24-bit precision analog to digital converter. It was found that lower precision would suffice, and therefore a 16-bit ADC could be used. At least a 32-bit word and 16-bit precision should be used in the calculations.
(BRI: A 16-bit is a low-bit quantization and a 24-bit is a high bit quantization)
- and the second number of quantization bits larger than the first number of quantization bits;
In [0051]:
A BioPack MP-150 data acquisition system was used to collect and digitalize (at 2000 Hz) the analog data
In [0254]:
Analog to Digital Converter (ADC) is necessary as an input device to read analog signals.
In [0253]:
The sensitive and low noise Silicon Design Model 1221 accelerometer was used throughout the early experiments, which allowed accurate recordings and identify desired features within the acceleration signal. The signal was processed using the Bio-pack M-150 data acquisition system, which has 24-bit precision analog to digital converter. It was found that lower precision would suffice, and therefore a 16-bit ADC could be used. At least a 32-bit word and 16-bit precision should be used in the calculations.
(BRI: A 16-bit is a low-bit quantization and a 24-bit is a high bit quantization)
It would have obvious to one of ordinary skill in the art before the effective filing date of the present application to combine AOUDIA , and Barsi.
The examiner interprets the invention as “ using neural network to learn to extend the quantization and provide a high accuracy to reflect original signal in which the learning is performed by computing and inferring the loss function”.
AOUDIA teaches a method for learning, and learning device, representation of low and high signals and loss function.
Barsi teaches low-bit and high-bit quantization.
Within the context of the core of the invention, the prior art combinations teaches the invention making the case for “motivation to combine”.
Within the context of the core of the invention, the prior art combinations teaches the invention making the case for “motivation to combine”.
One of ordinary skill would have motivation to combine AOUDIA and Barsi that can reconstruct packets to reduce low and high frequence noises [Barsi [0159])
In regard to claim 8: (Currently Amended)
AOUDIA does not explicitly disclose:
- wherein the low-bit signal corresponds to a music signal that is quantized based on an analog-digital conversion.
However, Barsi discloses:
- wherein the low-bit signal corresponds to a music signal that is quantized based on an analog-digital conversion.
In [0050]:
The evaluation function utilizes multiple linear regressions. The coefficient of determination is limited to two significant figures in order to provide sufficient
quantization noise to promote algorithm convergence.
In [0254]:
an Analog to Digital Converter (ADC) is necessary as an input device to read analog signals
In [0016]:
Wavelet analysis transforms signals into a two-dimensional time-frequency domain, utilizing a series of convolution operations on the signal against particular filters at various positions and time scales
In [0016]:
in addition, noises can be subtracted fairly easily from the recorded signal, which makes this tool very powerful in many applications: data compression, signal and image processing, music analysis,
in [0254]:
In the past few years ARM (Advanced RISC (reduced instruction set computer) Machines), has acquired big portion of the MCU market. This technology is wildly used in embedded devices such as smart phones, which may include Bluetooth, WI-FI, LCD or OLED display, variety of physical sensors, etc
(BRI: A smart phone can be used as an embedded music player)
In [0253]:
the signal was processed using the Bio-pack M-150 data acquisition system, which has 24-bit precision analog to digital converter. It was found that lower precision would suffice, and therefore a 16-bit ADC could be used. At least a 32-bit word and 16-bit precision should be used in the calculations.
(BRI: a 16-bit is a low-bit signal and music signals use data acquisition systems for recording, analysis and production)
It would have obvious to one of ordinary skill in the art before the effective filing date of the present application to combine AOUDIA , and Barsi.
The examiner interprets the invention as “ using neural network to learn to extend the quantization and provide a high accuracy to reflect original signal in which the learning is performed by computing and inferring the loss function”.
AOUDIA teaches a method for learning, and learning device, representation of low and high signals and loss function.
Barsi teaches low-bit and high-bit quantization.
Within the context of the core of the invention, the prior art combinations teaches the invention making the case for “motivation to combine”.
Within the context of the core of the invention, the prior art combinations teaches the invention making the case for “motivation to combine”.
One of ordinary skill would have motivation to combine AOUDIA and Barsi that can reconstruct packets to reduce low and high frequence noises [Barsi [0159])
In regard to claim 9: (Currently Amended)
AOUDIA discloses:
- wherein the low-bit signal corresponds to a sensor signal associated with a robot.
In [0020] :
Various techniques described herein may also be applied to a cyber-physical system (CPS) (a system of collaborating computational elements controlling physical entities). CPS may enable the implementation and exploitation of massive amounts of interconnected ICT devices (sensors, actuators, processors microcontrollers, etc.) embedded in physical objects at different locations. Mobile cyber physical systems, in which the physical system in question has inherent mobility, are a subcategory of cyber-physical systems. Examples of mobile physical systems include mobile robotics and electronics transported by humans or animals.
In [0054]:
the combined digital signal may be a one-bit digital signal while the digital signal produced by the signal reconstruction element 209 may be an 8-bit or 12-bit digital signal or other high-resolution digital signal (e.g., a signal having at least 8-bit resolution) providing a close approximation of the analog waveform of the original received signal.
In regard to claim 10: (Currently Amended)
AOUDIA does not explicitly disclose:
- wherein the first number quantization bits is substantially close to 16 bits, and wherein the second number of quantization bits is substantially close to 24 bits.
However, Barsi discloses:
- wherein the first number quantization is substantially close to 16 bits, and wherein the second number of quantization is substantially close to 24 bits.
In [0050]:
The evaluation function utilizes multiple linear regressions. The coefficient of determination is limited to two significant figures in order to provide sufficient
quantization noise to promote algorithm convergence.
In [0253]:
The sensitive and low noise Silicon Design Model 1221 accelerometer was used throughout the early experiments, which allowed accurate recordings and identify desired features within the acceleration signal. The signal was processed using the Bio-pack M-150 data acquisition system, which has 24-bit precision analog to digital converter. It was found that lower precision would suffice, and therefore a 16-bit ADC could be used. At least a 32-bit word and 16-bit precision should be used in the calculations.
It would have obvious to one of ordinary skill in the art before the effective filing date of the present application to combine AOUDIA , and Barsi.
The examiner interprets the invention as “ using neural network to learn to extend the quantization and provide a high accuracy to reflect original signal in which the learning is performed by computing and inferring the loss function”.
AOUDIA teaches a method for learning, and learning device, representation of low and high signals and loss function.
Barsi teaches low-bit and high-bit quantization.
Within the context of the core of the invention, the prior art combinations teaches the invention making the case for “motivation to combine”.
Barsi teaches quantization to 16-bit and 24-bits from ADC.
Within the context of the core of the invention, the prior art combinations teaches the invention making the case for “motivation to combine”.
One of ordinary skill would have motivation to combine AOUDIA and Barsi that can reconstruct packets to reduce low and high frequence noises [Barsi [0159])
In regard to claim 11: (Previously Presented)
AOUDIA discloses:
wherein the multilayer structure includes at least three layers
in [0035]:
multilayer perceptron network is a basic form a feedforward neural network and typically consists of an input layer, one or more hidden layers and an output layer
In regard to claim 15: (Currently Amended)
AOUDIA does not explicitly disclose:
- wherein the low-bit signal corresponds to a music signal that is quantized based on an analog-digital conversion.
However, Barsi discloses:
- wherein the low-bit signal corresponds to a music signal that is quantized based on an analog-digital conversion.
In [0050]:
The evaluation function utilizes multiple linear regressions. The coefficient of determination is limited to two significant figures in order to provide sufficient
quantization noise to promote algorithm convergence.
In [0254]:
an Analog to Digital Converter (ADC) is necessary as an input device to read analog signals
In [0016]:
Wavelet analysis transforms signals into a two-dimensional time-frequency domain, utilizing a series of convolution operations on the signal against particular filters at various positions and time scales
In [0016]:
in addition, noises can be subtracted fairly easily from the recorded signal, which makes this tool very powerful in many applications: data compression, signal and image processing, music analysis,
in [0254]:
In the past few years ARM (Advanced RISC (reduced instruction set computer) Machines), has acquired big portion of the MCU market. This technology is wildly used in embedded devices such as smart phones, which may include Bluetooth, WI-FI, LCD or OLED display, variety of physical sensors, etc
(BRI: A smart phone can be used as an embedded music player)
In [0253]:
the signal was processed using the Bio-pack M-150 data acquisition system, which has 24-bit precision analog to digital converter. It was found that lower precision would suffice, and therefore a 16-bit ADC could be used. At least a 32-bit word and 16-bit precision should be used in the calculations.
(BRI: a 16-bit is a low-bit signal and music signals use data acquisition systems for recording, analysis and production)
It would have obvious to one of ordinary skill in the art before the effective filing date of the present application to combine AOUDIA , and Barsi.
The examiner interprets the invention as “ using neural network to learn to extend the quantization and provide a high accuracy to reflect original signal in which the learning is performed by computing and inferring the loss function”.
AOUDIA teaches a method for learning, and learning device, representation of low and high signals and loss function.
Barsi teaches low-bit and high-bit quantization.
Within the context of the core of the invention, the prior art combinations teaches the invention making the case for “motivation to combine”.
Within the context of the core of the invention, the prior art combinations teaches the invention making the case for “motivation to combine”.
One of ordinary skill would have motivation to combine AOUDIA and Barsi that can reconstruct packets to reduce low and high frequence noises [Barsi [0159])
In regard to claim 16: (Currently Amended)
AOUDIA discloses:
- wherein the low-bit signal corresponds to a sensor signal associated with a robot.
In [0020] :
Various techniques described herein may also be applied to a cyber-physical system (CPS) (a system of collaborating computational elements controlling physical entities). CPS may enable the implementation and exploitation of massive amounts of interconnected ICT devices (sensors, actuators, processors microcontrollers, etc.) embedded in physical objects at different locations. Mobile cyber physical systems, in which the physical system in question has inherent mobility, are a subcategory of cyber-physical systems. Examples of mobile physical systems include mobile robotics and electronics transported by humans or animals.
In [0054]:
the combined digital signal may be a one-bit digital signal while the digital signal produced by the signal reconstruction element 209 may be an 8-bit or 12-bit digital signal or other high-resolution digital signal (e.g., a signal having at least 8-bit resolution) providing a close approximation of the analog waveform of the original received signal.
In regard to claim 17: (Currently Amended)
AOUDIA does not explicitly disclose:
- wherein the first number quantization is substantially close to 16 bits, and wherein the second number of quantization is substantially close to 24 bits.
However, Barsi discloses:
- wherein the first number quantization is substantially close to 16 bits, and wherein the second number of quantization is substantially close to 24 bits.
In [0050]:
The evaluation function utilizes multiple linear regressions. The coefficient of determination is limited to two significant figures in order to provide sufficient
quantization noise to promote algorithm convergence.
In [0253]:
The sensitive and low noise Silicon Design Model 1221 accelerometer was used throughout the early experiments, which allowed accurate recordings and identify desired features within the acceleration signal. The signal was processed using the Bio-pack M-150 data acquisition system, which has 24-bit precision analog to digital converter. It was found that lower precision would suffice, and therefore a 16-bit ADC could be used. At least a 32-bit word and 16-bit precision should be used in the calculations.
It would have obvious to one of ordinary skill in the art before the effective filing date of the present application to combine AOUDIA , and Barsi.
The examiner interprets the invention as “ using neural network to learn to extend the quantization and provide a high accuracy to reflect original signal in which the learning is performed by computing and inferring the loss function”.
AOUDIA teaches a method for learning, and learning device, representation of low and high signals and loss function.
Barsi teaches low-bit and high-bit quantization.
Within the context of the core of the invention, the prior art combinations teaches the invention making the case for “motivation to combine”.
Barsi teaches quantization to 16-bit and 24-bits from ADC.
Within the context of the core of the invention, the prior art combinations teaches the invention making the case for “motivation to combine”.
One of ordinary skill would have motivation to combine AOUDIA, and Barsi that can reconstruct packets to reduce low and high frequence noises [Barsi [0159])
AOUDIA discloses: In regard to claim 18: (Previously Presented)
wherein the multilayer structure includes at least three layers
in [0035]:
multilayer perceptron network is a basic form a feedforward neural network and typically consists of an input layer, one or more hidden layers and an output layer
In regard to claim 20: (Previously Presented)
AOUDIA does not explicitly disclose:
- wherein the low-bit signal corresponds to a music signal that is quantized based on an analog-digital conversion.
However, Barsi discloses:
- wherein the low-bit signal corresponds to a music signal that is quantized based on an analog-digital conversion.
In [0050]:
The evaluation function utilizes multiple linear regressions. The coefficient of determination is limited to two significant figures in order to provide sufficient
quantization noise to promote algorithm convergence.
In [0254]:
an Analog to Digital Converter (ADC) is necessary as an input device to read analog signals
In [0016]:
Wavelet analysis transforms signals into a two-dimensional time-frequency domain, utilizing a series of convolution operations on the signal against particular filters at various positions and time scales
In [0016]:
in addition, noises can be subtracted fairly easily from the recorded signal, which makes this tool very powerful in many applications: data compression, signal and image processing, music analysis,
in [0254]:
In the past few years ARM (Advanced RISC (reduced instruction set computer) Machines), has acquired big portion of the MCU market. This technology is wildly used in embedded devices such as smart phones, which may include Bluetooth, WI-FI, LCD or OLED display, variety of physical sensors, etc
(BRI: A smart phone can be used as an embedded music player)
In [0253]:
the signal was processed using the Bio-pack M-150 data acquisition system, which has 24-bit precision analog to digital converter. It was found that lower precision would suffice, and therefore a 16-bit ADC could be used. At least a 32-bit word and 16-bit precision should be used in the calculations.
(BRI: a 16-bit is a low-bit signal and music signals use data acquisition systems for recording, analysis and production)
It would have obvious to one of ordinary skill in the art before the effective filing date of the present application to combine AOUDIA , and Barsi.
The examiner interprets the invention as “ using neural network to learn to extend the quantization and provide a high accuracy to reflect original signal in which the learning is performed by computing and inferring the loss function”.
AOUDIA teaches a method for learning, and learning device, representation of low and high signals and loss function.
Barsi teaches low-bit and high-bit quantization.
Within the context of the core of the invention, the prior art combinations teaches the invention making the case for “motivation to combine”.
Within the context of the core of the invention, the prior art combinations teaches the invention making the case for “motivation to combine”.
One of ordinary skill would have motivation to combine AOUDIA and Barsi that can reconstruct packets to reduce low and high frequence noises [Barsi [0159])
In regard to claim 21: (Previously Presented)
AOUDIA discloses:
- wherein the low-bit signal corresponds to a sensor signal associated with a robot.
In [0020] :
Various techniques described herein may also be applied to a cyber-physical system (CPS) (a system of collaborating computational elements controlling physical entities). CPS may enable the implementation and exploitation of massive amounts of interconnected ICT devices (sensors, actuators, processors microcontrollers, etc.) embedded in physical objects at different locations. Mobile cyber physical systems, in which the physical system in question has inherent mobility, are a subcategory of cyber-physical systems. Examples of mobile physical systems include mobile robotics and electronics transported by humans or animals.
In [0054]:
the combined digital signal may be a one-bit digital signal while the digital signal produced by the signal reconstruction element 209 may be an 8-bit or 12-bit digital signal or other high-resolution digital signal (e.g., a signal having at least 8-bit resolution) providing a close approximation of the analog waveform of the original received signal.
Claims 2-3, 12-13 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over
in view of AIT AOUDIA et.al. (hereinafter AOUDIA) US 2021/0211163 A1[ Foreign Priority: FI , 20205014, Filed: 2020-01-08],
in view of Ohad Barsimantov (hereinafter Barsi) US 2020/0205771 A1.
further in view of Olexa Bilaniuk et.al(hereinafter Bila) Bit-Slicing FPGA Accelerator for Quantized Neural Networks, 2019 IEEE International Symposium on Circuits and Systems (ISCAS). IEEE, 2019.
In regard to claim 2: (Currently Amended)
AOUDIA discloses:
- wherein the neural network comprises [[a]] the multilayer structure including a layer that determines the output signal based on the input signal,
in [0035]:
multilayer perceptron network is a basic form a feedforward neural network and typically consists of an input layer, one or more hidden layers and an output layer. The network uses forward passes and backpropagation to learn the weights and bias. Forward passes (from input to output) calculate the outputs, while backpropagation calculates the necessary updates for the weights and biases based on the error at the output layer.
AOUDIA and Barsi do not explicitly disclose:
- and the output signal is determined based at least on a product of a first column of a plurality of values obtained by performing a first convolution linear transformation processing on the input signal and a second column of a plurality of values obtained by performing a second convolution linear transformation processing on the input signal based on a value.
However, Bila discloses:
- and the output signal is determined based at least on a product of a first column of a plurality of values obtained by performing a first convolution linear transformation processing on the input signal
In [1, Page 1]:
In this paper, a new QNN accelerator architecture supporting arbitrary low-precision fixed-point formats is introduced. The proposed architecture enables to process the inference pass in large neural networks while implementing an efficient streaming data flow in a flexible pipelined scheme that limits movement of data to off-chip memory
In [II C, Page 3]:
Weights tiles are n × n bits large and binary-only. For the purposes of quantized CNN, they map a subset of n input feature maps to n output feature maps. For RNN and GEMM, they are simply an n × n tile of the matrix product being implemented.
In [II, Page 2]:
A QNN accelerator design is therefore called to dedicate most of its resources to linear operations, while balancing them with non-linear activation throughput. This linear operation is most commonly the BLAS Level 3 operation GEMM (GEneral Matrix-Matrix product), since all linear operations can be expressed in terms of matrix multiplications.
In [II, Page 2]:
GEMM is not universally suitable as a primitive.
In [II, Page 2]:
Conceding that GEMM is not always ideal, we will instead adopt the BLAS Level 2 operation GEMV (GEneral Matrix-Vector product) as our basic linear operation.
(BRI: using a matrix-vector product as a basic operation is the definition and implementation of a linear transformation in which every matrix multiplication of a transformation matrix A by a vector v produces a new vector w which the result of a linear transformation)
In [II, Page 2]:
we will perform GEMV products with multibit operands bit-serially, yet the GEMV operation as a whole is parallelized using bit-slicing. Multiple independent GEMV units can be instantiated, and can provide extra, inter, or intra-layer parallelism; We will call these independent units Matrix-Vector Units. These MVUs communicate over an interconnect, sending messages containing the data vector they’re operating upon
In [II A, Page 2]: Matrix-Vector Unit
The matrix-vector product primitive suffices to implement almost all common linear operations in a neural network:
In [III, Page 3]: A. Linear operations
The use of matrix-vector products and our data layout allows us to implement all common varieties of convolution, as well as classic GEMM, by tiling them into their constituent matrix-vector products. Convolutions of any width or height, subsampled and/or dilated (a-trous)
In [II C Page 3]: Data and Weights Layout
Data vectors are 2n bits large, allowing for n ternary or binary elements. For the purposes of quantized CNN and RNN, element i of the data vector belongs to feature map i (mod n) of the convolutional or fully-connected layer. All elements also share the same spatial coordinates within the tensor
In [II A, Page 2]: Matrix-Vector Unit
The Matrix-Vector Unit (MVU) is at the heart of the design. Each MVU performs one n × n-element by n-element matrix-vector multiplication, where both the matrix and vector are binary (their elements are single bits). The result of such a product is a new n-element vector of ∼ log2 n bits each that is then accumulated into an n-wide vector accumulator register every clock cycle.
PNG
media_image1.png
435
506
media_image1.png
Greyscale
(BRI: the accumulating into n-wide vector provide the MVM result to each column of the matrix and this context, this is the first column operation)
(BRI: the context of highly optimized, extremely quantized CNNs, data vectors are often constructed by packing multiple low-precision elements together as described in the structural mapping above)
- and a second column of a plurality of values obtained by performing a second convolution linear transformation processing on the input signal based on a value.
In [1, Page 1]:
In this paper, a new QNN accelerator architecture supporting arbitrary low-precision fixed-point formats is introduced. The proposed architecture enables to process the inference pass in large neural networks while implementing an efficient streaming data flow in a flexible pipelined scheme that limits movement of data to off-chip memory
In [II C, Page 3]:
Weights tiles are n × n bits large and binary-only. For the purposes of quantized CNN, they map a subset of n input feature maps to n output feature maps. For RNN and GEMM, they are simply an n × n tile of the matrix product being implemented.
In [II, Page 2]:
A QNN accelerator design is therefore called to dedicate most of its resources to linear operations, while balancing them with non-linear activation throughput. This linear operation is most commonly the BLAS Level 3 operation GEMM (GEneral Matrix-Matrix product), since all linear operations can be expressed in terms of matrix multiplications.
In [II, Page 2]:
GEMM is not universally suitable as a primitive.
In [II, Page 2]:
Conceding that GEMM is not always ideal, we will instead adopt the BLAS Level 2 operation GEMV (GEneral Matrix-Vector product) as our basic linear operation.
In [II, Page 2]:
Conceding that GEMM is not always ideal, we will instead adopt the BLAS Level 2 operation GEMV (GEneral Matrix-Vector product) as our basic linear operation.
(BRI: using a matrix-vector product as a basic operation is the definition and implementation of a linear transformation in which every matrix multiplication of a transformation matrix A by a vector v produces a new vector w which the result of a linear transformation)
In [II, Page 2]:
we will perform GEMV products with multibit operands bit-serially, yet the GEMV operation as a whole is parallelized using bit-slicing. Multiple independent GEMV units can be instantiated, and can provide extra, inter, or intra-layer parallelism; We will call these independent units Matrix-Vector Units. These MVUs communicate over an interconnect, sending messages containing the data vector they’re operating upon
In [II A, Page 2]: Matrix-Vector Unit
The matrix-vector product primitive suffices to implement almost all common linear operations in a neural network:
In [III, Page 3]: A. Linear operations
The use of matrix-vector products and our data layout allows us to implement all common varieties of convolution, as well as classic GEMM, by tiling them into their constituent matrix-vector products. Convolutions of any width or height, subsampled and/or dilated (a-trous)
In [II C Page 3]: Data and Weights Layout
Data vectors are 2n bits large, allowing for n ternary or binary elements. For the purposes of quantized CNN and RNN, element i of the data vector belongs to feature map i (mod n) of the convolutional or fully-connected layer. All elements also share the same spatial coordinates within the tensor
In [II A, Page 2]: Matrix-Vector Unit
The Matrix-Vector Unit (MVU) is at the heart of the design. Each MVU performs one n × n-element by n-element matrix-vector multiplication, where both the matrix and vector are binary (their elements are single bits). The result of such a product is a new n-element vector of ∼ log2 n bits each that is then accumulated into an n-wide vector accumulator register every clock cycle.
PNG
media_image1.png
435
506
media_image1.png
Greyscale
(BRI: the accumulating into n-wide vector provide the MVM result to each column of the matrix and this context, this is the second column operation)
(BRI: the context of highly optimized, extremely quantized CNNs, data vectors are often constructed by packing multiple low-precision elements together as described in the structural mapping above)
It would have obvious to one of ordinary skill in the art before the effective filing date of the present application to combine AOUDIA , Barsi and Bila.
The examiner interprets the invention as “ using neural network to learn to extend the quantization and provide a high accuracy to reflect original signal in which the learning is performed by computing and inferring the loss function”
AOUDIA teaches a method for learning, and learning device, representation of low and high signals and loss function.
Barsi teaches low-bit and high-bit quantization.
Bila teaches the output signal performing linear transformation processing on the input signal.
Within the context of the core of the invention, the prior art combinations teaches the invention making the case for “motivation to combine”.
Within the context of the core of the invention, the prior art combinations teaches the invention making the case for “motivation to combine”.
One of ordinary skill would have motivation to combine AOUDIA, Barsi and Bila that can provide an improved hardware performance of neural network using low precision (Bila [ 1, Page 1])
In regard to claim 3: (Currently Amended)
AOUDIA discloses:
- wherein the neural network includes [[a]] the multilayer structure including a layer that determines the output signal based on the input signal
in [0035]:
multilayer perceptron network is a basic form a feedforward neural network and typically consists of an input layer, one or more hidden layers and an output layer. The network uses forward passes and backpropagation to learn the weights and bias. Forward passes (from input to output) calculate the outputs, while backpropagation calculates the necessary updates for the weights and biases based on the error at the output layer.
AOUDIA and Barsi do not explicitly disclose:
- and the output signal includes a product A x V', where A represents a column corresponding to a product of a column K of a plurality of values obtained by performing convolution linear transformation processing
W
K
on the input X and a column Q of a plurality of values obtained by performing convolution linear transformation processing WQ on the input signal, and V' represents a column of a plurality of values obtained by performing convolution linear transformation processing Wv on the input signal.
However, Bila discloses:
- and the output signal includes a product A x V', where A represents a column corresponding to a product of a column K of a plurality of values obtained by performing convolution linear transformation processing
W
K
on the input X
In [1, Page 1]:
In this paper, a new QNN accelerator architecture supporting arbitrary low-precision fixed-point formats is introduced. The proposed architecture enables to process the inference pass in large neural networks while implementing an efficient streaming data flow in a flexible pipelined scheme that limits movement of data to off-chip memory
In [II C, Page 3]:
Weights tiles are n × n bits large and binary-only. For the purposes of quantized CNN, they map a subset of n input feature maps to n output feature maps. For RNN and GEMM, they are simply an n × n tile of the matrix product being implemented.
In [II, Page 2]:
A QNN accelerator design is therefore called to dedicate most of its resources to linear operations, while balancing them with non-linear activation throughput. This linear operation is most commonly the BLAS Level 3 operation GEMM (GEneral Matrix-Matrix product), since all linear operations can be expressed in terms of matrix multiplications.
In [II A, Page 2]: Matrix-Vector Unit
The Matrix-Vector Unit (MVU) is at the heart of the design. Each MVU performs one n × n-element by n-element matrix-vector multiplication, where both the matrix and vector are binary (their elements are single bits). The result of such a product is a new n-element vector of ∼ log2 n bits each that is then accumulated into an n-wide vector accumulator register every clock cycle.
PNG
media_image1.png
435
506
media_image1.png
Greyscale
(BRI: the accumulating into n-wide vector provide the MVM result to each column of the matrix and this context, this is the K column operation. The MVM performing the n x n element by n-element matrix-vector multiplication is the convolution linear transformation processing
W
K
on the input X)
- and a column Q of a plurality of values obtained by performing convolution linear transformation processing WQ on the input signal,
In [1, Page 1]:
In this paper, a new QNN accelerator architecture supporting arbitrary low-precision fixed-point formats is introduced. The proposed architecture enables to process the inference pass in large neural networks while implementing an efficient streaming data flow in a flexible pipelined scheme that limits movement of data to off-chip memory
In [II C, Page 3]:
Weights tiles are n × n bits large and binary-only. For the purposes of quantized CNN, they map a subset of n input feature maps to n output feature maps. For RNN and GEMM, they are simply an n × n tile of the matrix product being implemented.
In [II, Page 2]:
A QNN accelerator design is therefore called to dedicate most of its resources to linear operations, while balancing them with non-linear activation throughput. This linear operation is most commonly the BLAS Level 3 operation GEMM (GEneral Matrix-Matrix product), since all linear operations can be expressed in terms of matrix multiplications.
In [II A, Page 2]: Matrix-Vector Unit
The Matrix-Vector Unit (MVU) is at the heart of the design. Each MVU performs one n × n-element by n-element matrix-vector multiplication, where both the matrix and vector are binary (their elements are single bits). The result of such a product is a new n-element vector of ∼ log2 n bits each that is then accumulated into an n-wide vector accumulator register every clock cycle.
PNG
media_image1.png
435
506
media_image1.png
Greyscale
(BRI: the accumulating into n-wide vector provide the MVM result to each column of the matrix and this context, this is the Q column operation. The MVM performing the n x n element by n-element matrix-vector multiplication is the convolution linear transformation processing
W
q
on the input X)
- and V' represents a column of a plurality of values obtained by performing convolution linear transformation processing
W
v
on the input signal.
In [1, Page 1]:
In this paper, a new QNN accelerator architecture supporting arbitrary low-precision fixed-point formats is introduced. The proposed architecture enables to process the inference pass in large neural networks while implementing an efficient streaming data flow in a flexible pipelined scheme that limits movement of data to off-chip memory
In [II C, Page 3]:
Weights tiles are n × n bits large and binary-only. For the purposes of quantized CNN, they map a subset of n input feature maps to n output feature maps. For RNN and GEMM, they are simply an n × n tile of the matrix product being implemented.
In [II, Page 2]:
A QNN accelerator design is therefore called to dedicate most of its resources to linear operations, while balancing them with non-linear activation throughput. This linear operation is most commonly the BLAS Level 3 operation GEMM (GEneral Matrix-Matrix product), since all linear operations can be expressed in terms of matrix multiplications.
In [II A, Page 2]: Matrix-Vector Unit
The Matrix-Vector Unit (MVU) is at the heart of the design. Each MVU performs one n × n-element by n-element matrix-vector multiplication, where both the matrix and vector are binary (their elements are single bits). The result of such a product is a new n-element vector of ∼ log2 n bits each that is then accumulated into an n-wide vector accumulator register every clock cycle.
PNG
media_image1.png
435
506
media_image1.png
Greyscale
(BRI: the accumulating into n-wide vector provide the MVM result to each column of the matrix and this context, this is the V’ column operation. The MVM performing the n x n element by n-element matrix-vector multiplication is the convolution linear transformation processing
W
v
on the input X)
It would have obvious to one of ordinary skill in the art before the effective filing date of the present application to combine AOUDIA , Barsi and Bila.
The examiner interprets the invention as “ using neural network to learn to extend the quantization and provide a high accuracy to reflect original signal in which the learning is performed by computing and inferring the loss function”
AOUDIA teaches a method for learning, and learning device, representation of low and high signals and loss function.
Barsi teaches low-bit and high-bit quantization.
Bila teaches the matrix-vector multiplication.
Within the context of the core of the invention, the prior art combinations teaches the invention making the case for “motivation to combine”.
Within the context of the core of the invention, the prior art combinations teaches the invention making the case for “motivation to combine”.
One of ordinary skill would have motivation to combine AOUDIA, Barsi and Bila that can provide an improved hardware performance of neural network using low precision (Bila [ 1, Page 1])
In regard to claim 12: (Currently Amended)
AOUDIA discloses:
- wherein the neural network comprises [[a]] the multilayer structure including a layer that determines the output signal based on the input signal,
in [0035]:
multilayer perceptron network is a basic form a feedforward neural network and typically consists of an input layer, one or more hidden layers and an output layer. The network uses forward passes and backpropagation to learn the weights and bias. Forward passes (from input to output) calculate the outputs, while backpropagation calculates the necessary updates for the weights and biases based on the error at the output layer.
AOUDIA and Barsi do not explicitly disclose:
- and the output signal is determined based at least on a product of a first column of a plurality of values obtained by performing a first convolution linear transformation processing on the input signal and a second column of a plurality of values obtained by performing a second convolution linear transformation processing on the input signal based on a value.
However, Bila discloses:
- and the output signal is determined based at least on a product of a first column of a plurality of values obtained by performing a first convolution linear transformation processing on the input signal
In [1, Page 1]:
In this paper, a new QNN accelerator architecture supporting arbitrary low-precision fixed-point formats is introduced. The proposed architecture enables to process the inference pass in large neural networks while implementing an efficient streaming data flow in a flexible pipelined scheme that limits movement of data to off-chip memory
In [II C, Page 3]:
Weights tiles are n × n bits large and binary-only. For the purposes of quantized CNN, they map a subset of n input feature maps to n output feature maps. For RNN and GEMM, they are simply an n × n tile of the matrix product being implemented.
In [II, Page 2]:
A QNN accelerator design is therefore called to dedicate most of its resources to linear operations, while balancing them with non-linear activation throughput. This linear operation is most commonly the BLAS Level 3 operation GEMM (GEneral Matrix-Matrix product), since all linear operations can be expressed in terms of matrix multiplications.
In [II, Page 2]:
GEMM is not universally suitable as a primitive.
In [II, Page 2]:
Conceding that GEMM is not always ideal, we will instead adopt the BLAS Level 2 operation GEMV (GEneral Matrix-Vector product) as our basic linear operation.
(BRI: using a matrix-vector product as a basic operation is the definition and implementation of a linear transformation in which every matrix multiplication of a transformation matrix A by a vector v produces a new vector w which the result of a linear transformation)
In [II, Page 2]:
we will perform GEMV products with multibit operands bit-serially, yet the GEMV operation as a whole is parallelized using bit-slicing. Multiple independent GEMV units can be instantiated, and can provide extra, inter, or intra-layer parallelism; We will call these independent units Matrix-Vector Units. These MVUs communicate over an interconnect, sending messages containing the data vector they’re operating upon
In [II A, Page 2]: Matrix-Vector Unit
The matrix-vector product primitive suffices to implement almost all common linear operations in a neural network:
In [III, Page 3]: A. Linear operations
The use of matrix-vector products and our data layout allows us to implement all common varieties of convolution, as well as classic GEMM, by tiling them into their constituent matrix-vector products. Convolutions of any width or height, subsampled and/or dilated (a-trous)
In [II C Page 3]: Data and Weights Layout
Data vectors are 2n bits large, allowing for n ternary or binary elements. For the purposes of quantized CNN and RNN, element i of the data vector belongs to feature map i (mod n) of the convolutional or fully-connected layer. All elements also share the same spatial coordinates within the tensor
In [II A, Page 2]: Matrix-Vector Unit
The Matrix-Vector Unit (MVU) is at the heart of the design. Each MVU performs one n × n-element by n-element matrix-vector multiplication, where both the matrix and vector are binary (their elements are single bits). The result of such a product is a new n-element vector of ∼ log2 n bits each that is then accumulated into an n-wide vector accumulator register every clock cycle.
PNG
media_image1.png
435
506
media_image1.png
Greyscale
(BRI: the accumulating into n-wide vector provide the MVM result to each column of the matrix and this context, this is the first column operation)
(BRI: the context of highly optimized, extremely quantized CNNs, data vectors are often constructed by packing multiple low-precision elements together as described in the structural mapping above)
- and a second column of a plurality of values obtained by performing a second convolution linear transformation processing on the input signal based on a value.
In [1, Page 1]:
In this paper, a new QNN accelerator architecture supporting arbitrary low-precision fixed-point formats is introduced. The proposed architecture enables to process the inference pass in large neural networks while implementing an efficient streaming data flow in a flexible pipelined scheme that limits movement of data to off-chip memory
In [II C, Page 3]:
Weights tiles are n × n bits large and binary-only. For the purposes of quantized CNN, they map a subset of n input feature maps to n output feature maps. For RNN and GEMM, they are simply an n × n tile of the matrix product being implemented.
In [II, Page 2]:
A QNN accelerator design is therefore called to dedicate most of its resources to linear operations, while balancing them with non-linear activation throughput. This linear operation is most commonly the BLAS Level 3 operation GEMM (GEneral Matrix-Matrix product), since all linear operations can be expressed in terms of matrix multiplications.
In [II, Page 2]:
GEMM is not universally suitable as a primitive.
In [II, Page 2]:
Conceding that GEMM is not always ideal, we will instead adopt the BLAS Level 2 operation GEMV (GEneral Matrix-Vector product) as our basic linear operation.
In [II, Page 2]:
Conceding that GEMM is not always ideal, we will instead adopt the BLAS Level 2 operation GEMV (GEneral Matrix-Vector product) as our basic linear operation.
(BRI: using a matrix-vector product as a basic operation is the definition and implementation of a linear transformation in which every matrix multiplication of a transformation matrix A by a vector v produces a new vector w which the result of a linear transformation)
In [II, Page 2]:
we will perform GEMV products with multibit operands bit-serially, yet the GEMV operation as a whole is parallelized using bit-slicing. Multiple independent GEMV units can be instantiated, and can provide extra, inter, or intra-layer parallelism; We will call these independent units Matrix-Vector Units. These MVUs communicate over an interconnect, sending messages containing the data vector they’re operating upon
In [II A, Page 2]: Matrix-Vector Unit
The matrix-vector product primitive suffices to implement almost all common linear operations in a neural network:
In [III, Page 3]: A. Linear operations
The use of matrix-vector products and our data layout allows us to implement all common varieties of convolution, as well as classic GEMM, by tiling them into their constituent matrix-vector products. Convolutions of any width or height, subsampled and/or dilated (a-trous)
In [II C Page 3]: Data and Weights Layout
Data vectors are 2n bits large, allowing for n ternary or binary elements. For the purposes of quantized CNN and RNN, element i of the data vector belongs to feature map i (mod n) of the convolutional or fully-connected layer. All elements also share the same spatial coordinates within the tensor
In [II A, Page 2]: Matrix-Vector Unit
The Matrix-Vector Unit (MVU) is at the heart of the design. Each MVU performs one n × n-element by n-element matrix-vector multiplication, where both the matrix and vector are binary (their elements are single bits). The result of such a product is a new n-element vector of ∼ log2 n bits each that is then accumulated into an n-wide vector accumulator register every clock cycle.
PNG
media_image1.png
435
506
media_image1.png
Greyscale
(BRI: the accumulating into n-wide vector provide the MVM result to each column of the matrix and this context, this is the second column operation)
(BRI: the context of highly optimized, extremely quantized CNNs, data vectors are often constructed by packing multiple low-precision elements together as described in the structural mapping above)
It would have obvious to one of ordinary skill in the art before the effective filing date of the present application to combine AOUDIA , Barsi and Bila.
The examiner interprets the invention as “ using neural network to learn to extend the quantization and provide a high accuracy to reflect original signal in which the learning is performed by computing and inferring the loss function”
AOUDIA teaches a method for learning, and learning device, representation of low and high signals and loss function.
Barsi teaches low-bit and high-bit quantization.
Bila teaches the output signal performing linear transformation processing on the input signal.
Within the context of the core of the invention, the prior art combinations teaches the invention making the case for “motivation to combine”.
Within the context of the core of the invention, the prior art combinations teaches the invention making the case for “motivation to combine”.
One of ordinary skill would have motivation to combine AOUDIA, Barsi and Bila that can provide an improved hardware performance of neural network using low precision (Bila [ 1, Page 1])
In regard to claim 13: (Currently Amended)
AOUDIA discloses:
- wherein the neural network includes [[a]] the multilayer structure including a layer that determines the output signal based on the input signal
in [0035]:
multilayer perceptron network is a basic form a feedforward neural network and typically consists of an input layer, one or more hidden layers and an output layer. The network uses forward passes and backpropagation to learn the weights and bias. Forward passes (from input to output) calculate the outputs, while backpropagation calculates the necessary updates for the weights and biases based on the error at the output layer.
AOUDIA and Barsi do not explicitly disclose:
- and the output signal includes a product A x V', where A represents a column corresponding to a product of a column K of a plurality of values obtained by performing convolution linear transformation processing
W
K
on the input X and a column Q of a plurality of values obtained by performing convolution linear transformation processing WQ on the input signal, and V' represents a column of a plurality of values obtained by performing convolution linear transformation processing
W
v
on the input signal.
However, Bila discloses:
- and the output signal includes a product A x V', where A represents a column corresponding to a product of a column K of a plurality of values obtained by performing convolution linear transformation processing
W
K
on the input X
In [1, Page 1]:
In this paper, a new QNN accelerator architecture supporting arbitrary low-precision fixed-point formats is introduced. The proposed architecture enables to process the inference pass in large neural networks while implementing an efficient streaming data flow in a flexible pipelined scheme that limits movement of data to off-chip memory
In [II C, Page 3]:
Weights tiles are n × n bits large and binary-only. For the purposes of quantized CNN, they map a subset of n input feature maps to n output feature maps. For RNN and GEMM, they are simply an n × n tile of the matrix product being implemented.
In [II, Page 2]:
A QNN accelerator design is therefore called to dedicate most of its resources to linear operations, while balancing them with non-linear activation throughput. This linear operation is most commonly the BLAS Level 3 operation GEMM (GEneral Matrix-Matrix product), since all linear operations can be expressed in terms of matrix multiplications.
In [II A, Page 2]: Matrix-Vector Unit
The Matrix-Vector Unit (MVU) is at the heart of the design. Each MVU performs one n × n-element by n-element matrix-vector multiplication, where both the matrix and vector are binary (their elements are single bits). The result of such a product is a new n-element vector of ∼ log2 n bits each that is then accumulated into an n-wide vector accumulator register every clock cycle.
PNG
media_image1.png
435
506
media_image1.png
Greyscale
(BRI: the accumulating into n-wide vector provide the MVM result to each column of the matrix and this context, this is the K column operation. The MVM performing the n x n element by n-element matrix-vector multiplication is the convolution linear transformation processing
W
K
on the input X)
- and a column Q of a plurality of values obtained by performing convolution linear transformation processing WQ on the input signal,
In [1, Page 1]:
In this paper, a new QNN accelerator architecture supporting arbitrary low-precision fixed-point formats is introduced. The proposed architecture enables to process the inference pass in large neural networks while implementing an efficient streaming data flow in a flexible pipelined scheme that limits movement of data to off-chip memory
In [II C, Page 3]:
Weights tiles are n × n bits large and binary-only. For the purposes of quantized CNN, they map a subset of n input feature maps to n output feature maps. For RNN and GEMM, they are simply an n × n tile of the matrix product being implemented.
In [II, Page 2]:
A QNN accelerator design is therefore called to dedicate most of its resources to linear operations, while balancing them with non-linear activation throughput. This linear operation is most commonly the BLAS Level 3 operation GEMM (GEneral Matrix-Matrix product), since all linear operations can be expressed in terms of matrix multiplications.
In [II A, Page 2]: Matrix-Vector Unit
The Matrix-Vector Unit (MVU) is at the heart of the design. Each MVU performs one n × n-element by n-element matrix-vector multiplication, where both the matrix and vector are binary (their elements are single bits). The result of such a product is a new n-element vector of ∼ log2 n bits each that is then accumulated into an n-wide vector accumulator register every clock cycle.
PNG
media_image1.png
435
506
media_image1.png
Greyscale
(BRI: the accumulating into n-wide vector provide the MVM result to each column of the matrix and this context, this is the Q column operation. The MVM performing the n x n element by n-element matrix-vector multiplication is the convolution linear transformation processing
W
q
on the input X)
- and V' represents a column of a plurality of values obtained by performing convolution linear transformation processing
W
v
on the input signal.
In [1, Page 1]:
In this paper, a new QNN accelerator architecture supporting arbitrary low-precision fixed-point formats is introduced. The proposed architecture enables to process the inference pass in large neural networks while implementing an efficient streaming data flow in a flexible pipelined scheme that limits movement of data to off-chip memory
In [II C, Page 3]:
Weights tiles are n × n bits large and binary-only. For the purposes of quantized CNN, they map a subset of n input feature maps to n output feature maps. For RNN and GEMM, they are simply an n × n tile of the matrix product being implemented.
In [II, Page 2]:
A QNN accelerator design is therefore called to dedicate most of its resources to linear operations, while balancing them with non-linear activation throughput. This linear operation is most commonly the BLAS Level 3 operation GEMM (GEneral Matrix-Matrix product), since all linear operations can be expressed in terms of matrix multiplications.
In [II A, Page 2]: Matrix-Vector Unit
The Matrix-Vector Unit (MVU) is at the heart of the design. Each MVU performs one n × n-element by n-element matrix-vector multiplication, where both the matrix and vector are binary (their elements are single bits). The result of such a product is a new n-element vector of ∼ log2 n bits each that is then accumulated into an n-wide vector accumulator register every clock cycle.
PNG
media_image1.png
435
506
media_image1.png
Greyscale
(BRI: the accumulating into n-wide vector provide the MVM result to each column of the matrix and this context, this is the V’ column operation. The MVM performing the n x n element by n-element matrix-vector multiplication is the convolution linear transformation processing
W
v
on the input X)
It would have obvious to one of ordinary skill in the art before the effective filing date of the present application to combine AOUDIA , Barsi and Bila.
The examiner interprets the invention as “ using neural network to learn to extend the quantization and provide a high accuracy to reflect original signal in which the learning is performed by computing and inferring the loss function”
AOUDIA teaches a method for learning, and learning device, representation of low and high signals and loss function.
Barsi teaches low-bit and high-bit quantization.
Bila teaches the matrix-vector multiplication.
Within the context of the core of the invention, the prior art combinations teaches the invention making the case for “motivation to combine”.
Within the context of the core of the invention, the prior art combinations teaches the invention making the case for “motivation to combine”.
One of ordinary skill would have motivation to combine AOUDIA, Barsi and Bila that can provide an improved hardware performance of neural network using low precision (Bila [ 1, Page 1])
In regard to claim 19: (Currently Amended)
AOUDIA discloses:
- wherein the neural network includes [[a]] the multilayer structure including a layer that determines the output signal based on the input signal
in [0035]:
multilayer perceptron network is a basic form a feedforward neural network and typically consists of an input layer, one or more hidden layers and an output layer. The network uses forward passes and backpropagation to learn the weights and bias. Forward passes (from input to output) calculate the outputs, while backpropagation calculates the necessary updates for the weights and biases based on the error at the output layer.
AOUDIA and Barsi do not explicitly disclose:
- and the output signal includes a product A x V', where A represents a column corresponding to a product of a column K of a plurality of values obtained by performing convolution linear transformation processing
W
K
on the input X and a column Q of a plurality of values obtained by performing convolution linear transformation processing WQ on the input signal, and V' represents a column of a plurality of values obtained by performing convolution linear transformation processing
W
v
on the input signal.
However, Bila discloses:
- and the output signal includes a product A x V', where A represents a column corresponding to a product of a column K of a plurality of values obtained by performing convolution linear transformation processing
W
K
on the input X
In [1, Page 1]:
In this paper, a new QNN accelerator architecture supporting arbitrary low-precision fixed-point formats is introduced. The proposed architecture enables to process the inference pass in large neural networks while implementing an efficient streaming data flow in a flexible pipelined scheme that limits movement of data to off-chip memory
In [II C, Page 3]:
Weights tiles are n × n bits large and binary-only. For the purposes of quantized CNN, they map a subset of n input feature maps to n output feature maps. For RNN and GEMM, they are simply an n × n tile of the matrix product being implemented.
In [II, Page 2]:
A QNN accelerator design is therefore called to dedicate most of its resources to linear operations, while balancing them with non-linear activation throughput. This linear operation is most commonly the BLAS Level 3 operation GEMM (GEneral Matrix-Matrix product), since all linear operations can be expressed in terms of matrix multiplications.
In [II A, Page 2]: Matrix-Vector Unit
The Matrix-Vector Unit (MVU) is at the heart of the design. Each MVU performs one n × n-element by n-element matrix-vector multiplication, where both the matrix and vector are binary (their elements are single bits). The result of such a product is a new n-element vector of ∼ log2 n bits each that is then accumulated into an n-wide vector accumulator register every clock cycle.
PNG
media_image1.png
435
506
media_image1.png
Greyscale
(BRI: the accumulating into n-wide vector provide the MVM result to each column of the matrix and this context, this is the K column operation. The MVM performing the n x n element by n-element matrix-vector multiplication is the convolution linear transformation processing
W
K
on the input X)
- and a column Q of a plurality of values obtained by performing convolution linear transformation processing WQ on the input signal,
In [1, Page 1]:
In this paper, a new QNN accelerator architecture supporting arbitrary low-precision fixed-point formats is introduced. The proposed architecture enables to process the inference pass in large neural networks while implementing an efficient streaming data flow in a flexible pipelined scheme that limits movement of data to off-chip memory
In [II C, Page 3]:
Weights tiles are n × n bits large and binary-only. For the purposes of quantized CNN, they map a subset of n input feature maps to n output feature maps. For RNN and GEMM, they are simply an n × n tile of the matrix product being implemented.
In [II, Page 2]:
A QNN accelerator design is therefore called to dedicate most of its resources to linear operations, while balancing them with non-linear activation throughput. This linear operation is most commonly the BLAS Level 3 operation GEMM (GEneral Matrix-Matrix product), since all linear operations can be expressed in terms of matrix multiplications.
In [II A, Page 2]: Matrix-Vector Unit
The Matrix-Vector Unit (MVU) is at the heart of the design. Each MVU performs one n × n-element by n-element matrix-vector multiplication, where both the matrix and vector are binary (their elements are single bits). The result of such a product is a new n-element vector of ∼ log2 n bits each that is then accumulated into an n-wide vector accumulator register every clock cycle.
PNG
media_image1.png
435
506
media_image1.png
Greyscale
(BRI: the accumulating into n-wide vector provide the MVM result to each column of the matrix and this context, this is the Q column operation. The MVM performing the n x n element by n-element matrix-vector multiplication is the convolution linear transformation processing
W
q
on the input X)
- and V' represents a column of a plurality of values obtained by performing convolution linear transformation processing
W
v
on the input signal.
In [1, Page 1]:
In this paper, a new QNN accelerator architecture supporting arbitrary low-precision fixed-point formats is introduced. The proposed architecture enables to process the inference pass in large neural networks while implementing an efficient streaming data flow in a flexible pipelined scheme that limits movement of data to off-chip memory
In [II C, Page 3]:
Weights tiles are n × n bits large and binary-only. For the purposes of quantized CNN, they map a subset of n input feature maps to n output feature maps. For RNN and GEMM, they are simply an n × n tile of the matrix product being implemented.
In [II, Page 2]:
A QNN accelerator design is therefore called to dedicate most of its resources to linear operations, while balancing them with non-linear activation throughput. This linear operation is most commonly the BLAS Level 3 operation GEMM (GEneral Matrix-Matrix product), since all linear operations can be expressed in terms of matrix multiplications.
In [II A, Page 2]: Matrix-Vector Unit
The Matrix-Vector Unit (MVU) is at the heart of the design. Each MVU performs one n × n-element by n-element matrix-vector multiplication, where both the matrix and vector are binary (their elements are single bits). The result of such a product is a new n-element vector of ∼ log2 n bits each that is then accumulated into an n-wide vector accumulator register every clock cycle.
PNG
media_image1.png
435
506
media_image1.png
Greyscale
(BRI: the accumulating into n-wide vector provide the MVM result to each column of the matrix and this context, this is the V’ column operation. The MVM performing the n x n element by n-element matrix-vector multiplication is the convolution linear transformation processing
W
v
on the input X)
It would have obvious to one of ordinary skill in the art before the effective filing date of the present application to combine AOUDIA , Barsi and Bila.
The examiner interprets the invention as “ using neural network to learn to extend the quantization and provide a high accuracy to reflect original signal in which the learning is performed by computing and inferring the loss function”
AOUDIA teaches a method for learning, and learning device, representation of low and high signals and loss function.
Barsi teaches low-bit and high-bit quantization.
Bila teaches the matrix-vector multiplication.
Within the context of the core of the invention, the prior art combinations teaches the invention making the case for “motivation to combine”.
Within the context of the core of the invention, the prior art combinations teaches the invention making the case for “motivation to combine”.
One of ordinary skill would have motivation to combine AOUDIA, Barsi and Bila that can provide an improved hardware performance of neural network using low precision (Bila [ 1, Page 1])
Claims 4 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over
in view of AIT AOUDIA et.al. (hereinafter AOUDIA) US 2021/0211163 A1 [Foreign Priority: FI , 20205014, Filed: 2020-01-08],
in view of Ohad Barsimantov (hereinafter Barsi) US 2020/0205771 A1.
further in view of Tal Shaked et.al (hereinafter Shaked) US 10062035 B1,
In regard to claim 4: (Currently Amended)
AOUDIA and Barsi do not explicitly disclose:
inputting another low-bit input signal quantized to the first number of quantization bits to the learnt [[the]] neural network,
and obtaining and outputting another estimated signal to the second number of quantization bits larger than the first number of quantization bits.
However, Shaked discloses:
inputting another low-bit input signal quantized to the first number of quantization bits to the learnt [[the]] neural network,
in [Abstract]:
methods and systems for using variable length representations of machine learning statistics. A method may include storing an n-bit representation of a first statistic at a first n-bit storage cell.
(BRI: An ML statistics collects , analyzes and interpret the data to build models)
In [Col 2, lines 49-55]:
a first mapper may receive example A and example B from a data stream. Both examples may contain features F1, F2, and F3. The mapper may generate a first statistic (e.g., based on a label indicating that a user selected a search result) for F1 based on example A and a second statistic (e.g., based on a label indicating that a user selected a search result) for F1 based on example B
In [Col 9, lines 15-17]:
For ease of illustration and explanation, relatively small values are used for specific examples of low- and high-bit representations
In [Col 9, lines 22-29]:
For example, binary representations such as those defined in the IEEE Standard for Floating-Point Arithmetic (IEEE 754) may be used, such as by storing and/or processing a low-bit representation in binary 32 (single precision), binary 64 (double precision), decimal 32, or decimal 64 format, and a high-bit representation in binary 64, binary 128, decimal 64, or decimal 128 format.
and obtaining and outputting another estimated signal to the second number of quantization bits larger than the first number of quantization bits.
In [Col 2, lines 49-55]:
a first mapper may receive example A and example B from a data stream. Both examples may contain features F1, F2, and F3. The mapper may generate a first statistic (e.g., based on a label indicating that a user selected a search result) for F1 based on example A and a second statistic (e.g., based on a label indicating that a user selected a search result) for F1 based on example B
In [Col 9, lines 15-17]:
For ease of illustration and explanation, relatively small values are used for specific examples of low- and high-bit representations
In [Col 9, lines 22-29]:
For example, binary representations such as those defined in the IEEE Standard for Floating-Point Arithmetic (IEEE 754) may be used, such as by storing and/or processing a low-bit representation in binary 32 (single precision), binary 64 (double precision), decimal 32, or decimal 64 format, and a high-bit representation in binary 64, binary 128, decimal 64, or decimal 128 format.
In [Col 4, lines 17-24]:
the accuracy of predictions made by a machine learning system are based on a model generated using statistics associated with features, it may be very important to store a high precision statistic for a frequently occurring feature.
(BRI: high-precision storage crucial for frequent features. In ML, precise feature stats (mean, variance) train better models where more bits (higher-bit) to reduce error in representing analog signals digitally which are fed into ML)
It would have obvious to one of ordinary skill in the art before the effective filing date of the present application to combine AOUDIA, Barsi, and Shaked.
The examiner interprets the invention as “ using neural network to learn to extend the quantization and provide a high accuracy to reflect original signal in which the learning is performed by computing and inferring the loss function”
AOUDIA teaches a method for learning, and learning device, representation of low and high signals and loss function.
Barsi teaches low-bit and high-bit quantization.
Shaked teaches learning high-bit transformation from low-bit.
Within the context of the core of the invention, the prior art combinations teaches the invention making the case for “motivation to combine”.
One of ordinary skill would have motivation to combine AOUDIA, Barsi and Shaked may improve the quality of ML systems and provide more accurate predictions (Shaked [Col 9, lines 9-14])
In regard to claim 14: (Previously Presented)
AOUDIA and Barsi do not explicitly disclose:
inputting another low-bit input signal quantized to the first number of quantization bits to the learnt [[the]] neural network,
and obtaining and outputting another estimated signal to the second number of quantization bits larger than the first number of quantization bits.
However, Shaked discloses:
inputting another low-bit input signal quantized to the first number of quantization bits to the learnt [[the]] neural network,
in [Abstract]:
methods and systems for using variable length representations of machine learning statistics. A method may include storing an n-bit representation of a first statistic at a first n-bit storage cell.
(BRI: An ML statistics collects , analyzes and interpret the data to build models)
In [Col 2, lines 49-55]:
a first mapper may receive example A and example B from a data stream. Both examples may contain features F1, F2, and F3. The mapper may generate a first statistic (e.g., based on a label indicating that a user selected a search result) for F1 based on example A and a second statistic (e.g., based on a label indicating that a user selected a search result) for F1 based on example B
In [Col 9, lines 15-17]:
For ease of illustration and explanation, relatively small values are used for specific examples of low- and high-bit representations
In [Col 9, lines 22-29]:
For example, binary representations such as those defined in the IEEE Standard for Floating-Point Arithmetic (IEEE 754) may be used, such as by storing and/or processing a low-bit representation in binary 32 (single precision), binary 64 (double precision), decimal 32, or decimal 64 format, and a high-bit representation in binary 64, binary 128, decimal 64, or decimal 128 format.
and obtaining and outputting another estimated signal to the second number of quantization bits larger than the first number of quantization bits.
In [Col 2, lines 49-55]:
a first mapper may receive example A and example B from a data stream. Both examples may contain features F1, F2, and F3. The mapper may generate a first statistic (e.g., based on a label indicating that a user selected a search result) for F1 based on example A and a second statistic (e.g., based on a label indicating that a user selected a search result) for F1 based on example B
In [Col 9, lines 15-17]:
For ease of illustration and explanation, relatively small values are used for specific examples of low- and high-bit representations
In [Col 9, lines 22-29]:
For example, binary representations such as those defined in the IEEE Standard for Floating-Point Arithmetic (IEEE 754) may be used, such as by storing and/or processing a low-bit representation in binary 32 (single precision), binary 64 (double precision), decimal 32, or decimal 64 format, and a high-bit representation in binary 64, binary 128, decimal 64, or decimal 128 format.
In [Col 4, lines 17-24]:
the accuracy of predictions made by a machine learning system are based on a model generated using statistics associated with features, it may be very important to store a high precision statistic for a frequently occurring feature.
(BRI: high-precision storage crucial for frequent features. In ML, precise feature stats (mean, variance) train better models where more bits (higher-bit) to reduce error in representing analog signals digitally which are fed into ML)
It would have obvious to one of ordinary skill in the art before the effective filing date of the present application to combine AOUDIA, Barsi, and Shaked.
The examiner interprets the invention as “ using neural network to learn to extend the quantization and provide a high accuracy to reflect original signal in which the learning is performed by computing and inferring the loss function”
AOUDIA teaches a method for learning, and learning device, representation of low and high signals and loss function.
Barsi teaches low-bit and high-bit quantization.
Shaked teaches learning high-bit transformation from low-bit to high-bit.
Within the context of the core of the invention, the prior art combinations teaches the invention making the case for “motivation to combine”.
One of ordinary skill would have motivation to combine AOUDIA, Barsi and Shaked may improve the quality of ML systems and provide more accurate predictions (Shaked [Col 9, lines 9-14])
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the
examiner should be directed to TIRUMALE KRISHNASWAMY RAMESH whose telephone number is (571)272-4605. The examiner can normally be reached by phone.
Examiner interviews are available via telephone, in-person, and video conferencing
using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Li B
Zhen can be reached on phone (571-272-3768). The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be
obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit:
https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for
information about filing in DOCX format. For additional questions, contact the Electronic
Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO
Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/TIRUMALE K RAMESH/Examiner, Art Unit 2121
/Li B. Zhen/Supervisory Patent Examiner, Art Unit 2121