Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
Claim 19, 32, and 33 are rejected under 35 U.S.C. 103 as being unpatentable over Saito (JP 10154774) in further view of Fujino (PGPub No. 20200083129).
Regarding claim 19, Saito teaches a semiconductor device ((Fig.2 and [0024] point to a semiconductor module) comprising: an insulating substrate (Fig. 4(a) and [0030] point to an insulating substrate 10) on which a semiconductor element is mounted (Id.; see IGBT chip(s) 23); a heat dissipation member (Id.; see Cu base 20) bonded to the insulating substrate by first solder (Id.; see solder layer 22); wherein the insulating substrate has a main surface curved so as to have a shape convex toward the heat dissipation member and extending over a plurality of the semiconductor elements (Fig. 4(d) points to a curved insulating substrate 10), the first solder is thicker at edges than at a center in a plan view (Id.; see solder sheet 22’), and the semiconductor element is bonded to the electrode plate by second solder (Fig. 4(a) and [0030] point to a second solder layer 25), and the semiconductor device further comprising: a frame member disposed so as to surround the insulating substrate at a distance from the insulating substrate (Fig. 3 points to a module case 29 surrounding the insulating substrate 10).
Saito fails to teach an electrode plate disposed above the semiconductor element so as to overlap at least a part of the semiconductor element, wherein the electrode plate is disposed so as to face the insulating substrate in the frame member, and the electrode plate has a main surface curved along the convex shape of the insulating substrate.
Saito in combination with Fujino teaches an electrode plate disposed above the semiconductor element so as to overlap at least a part of the semiconductor element (Fig. 2 and [0035] of Fujino points to a lead frame 611a (electrode plate), positioned above semiconductor elements 21 and 22.), wherein the electrode plate is disposed so as to face the insulating substrate in the frame member (Fig. 2 of Fujino points to opening portions 611b (electrode plate), which is disposed in a casing 51 (frame member) and faces an insulative board 11 (insulating substrate).), and the electrode plate has a main surface curved along the convex shape of the insulating substrate (Fig. 7 of Saito points to a curved upper metallization layer 11 (electrode plate).). Thus, it would have been obvious to a person of ordinary skill in the art (POSITA) prior to the filing date of the claimed invention to modify the teachings of Saito with those of Fujino, such that a lead frame/electrode plate is disposed above the semiconductor element and within the frame member in order to form a high current-density circuit.
Regarding claim 32, Fujino teaches wherein the electrode plate is at a distance from the semiconductor element in a Z direction and the electrode plate has a shape that extends along an XY plane (Figs. 1 and 2 point to the lead frame 611a (electrode plate).). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to modify the teachings of Saito with those of Fujino, such that the lead frame/electrode plate is disposed at a distance from the semiconductor element and extends along the semiconductor device in order to better deal with the elevation in voltage and increase in current of the power module/semiconductor device.
Regarding claim 33, Fujino teaches wherein one main surface of the semiconductor element is bonded to the electrode plate by the second solder (Fig. 2 points to solder-bonding portions 30/31 (second solder).), and an other main surface of the semiconductor element is bonded to the insulating substrate by a conductive member (Id. points to a conductive layer 13 (conductive member).). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to modify the teachings of Saito with those of Fujino, such that the semiconductor element is bonded to the electrode plate via solder and to the insulating substrate via a conductive member in order to enable electrical connection(s) and proper heat dissipation, respectively.
Claim 21 is rejected under 35 U.S.C. 103 as being unpatentable over Saito et al. in further view of Chen (PGPub No. 20050285258).
Saito teaches wherein the heat dissipation member includes a first heat dissipation member portion (Fig. 4(a) and [0030] point to a Cu base 20) bonded to the insulating substrate by the first solder (Id.; see insulating substrate 10 and solder layer 22).
Saito alone fails to teach a second heat dissipation member portion disposed outside the first heat dissipation member portion to surround the first heat dissipation member portion and the first solder in the plan view, the frame member being mounted on the second heat dissipation member portion, and in the heat dissipation member, a depression formed by the first heat dissipation member portion and the second heat dissipation member portion houses the first solder and the insulating substrate.
Saito in combination with Chen teaches a second heat dissipation member portion disposed outside the first heat dissipation member portion to surround the first heat dissipation member portion and the first solder in the plan view, the frame member being mounted on the second heat dissipation member portion, and in the heat dissipation member, a depression formed by the first heat dissipation member portion and the second heat dissipation member portion houses the first solder and the insulating substrate (Fig. 1; [0003]). Specifically, Chen teaches a conventional semiconductor package comprising a heat sink 13 made of copper comprising a horizontal portion (first heat dissipation member portion) and a vertical portion (second heat dissipation member portion) that together create a region (depression) that surrounds the substrate 11 and chip 12 (Id.). Chen is considered analogous to the claimed invention due to 1) both discussing a semiconductor device/package, and 2) sharing at least one CPC classification (US CPC H01L 2224/45015). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to modify the teachings of Saito with those of Chen, such that the shape of the copper heatsink in Chen was rotated and applied to the copper heat sink in Saito (Cu base 20) in order to provide better thermal cooling to the overall device through additional points of contact with the heat dissipation member(s).
Claim 34 and 35 are rejected under 35 U.S.C. 103 as being unpatentable over Saito et al. in further view of Fujino2 (JP 2015133462).
Regarding claim 34, Fujino2 teaches wherein the electrode plate includes a portion extending in a horizontal direction and facing the semiconductor element (Fig. 7 points to a power module 100 comprising a main terminal 6 and an IGBT 1 (semiconductor element).) and a portion bent from the portion extending in the horizontal direction and extending in a Z direction, wherein the portion extending in the Z direction corresponds to the edge of the electrode plate (Id. points to a welding terminal 6b.). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Saito et al. and Fujino2, such that a portion of the electrode plate is bent upwards in order to allow for easier access to the electrode plate and by extension better communication with the underlying semiconductor element.
Regarding claim 35, Fujino2 teaches wherein the electrode plate includes a main terminal-side edge and a semiconductor element-side edge, the main terminal-side edge includes the portion bent from the portion extending in the horizontal direction and extending in the Z direction comprising a first portion extending in the Z direction and exposed outside of the frame member and a second portion embedded in the frame member (Fig. 7 points to the main terminal 6 (semiconductor element-side edge) and the welding terminal 6b (main terminal-side edge) which is fixed to a bridging member 9 via insert molding. Fig. 6 points to an alternative embodiment comprising a screw terminal 6a (main terminal-side edge) that is insert-molded in the case 5 (frame member). It is considered obvious that one of ordinary skill could combine the embodiments such that the welding terminal 6b (main terminal-side edge) is instead embedded into the case 5 (frame member) via insert molding.). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Saito et al. and Fujino2, such that the electrode plate comprises a vertically extending portion that is partially embedded in the case/frame member in order to better protect the electrode plate while still allowing access to the electrode plate and by extension better communication with the underlying semiconductor element.
Response to Arguments
Applicant's arguments filed 01/15/2026 have been fully considered but they are not persuasive. Specifically, Applicant argues 1) that the rejection of claim 19 is improper due to reference Saito failing to teach all elements of the claim, and 2) that the rejection of claim 21 is improper because reference Chen does not remedy the deficiencies of Saito.
Regarding the first argument, Examiner argues that Applicant is providing a piecemeal analysis focusing solely on reference Saito. In response to applicant's arguments against the references individually, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986). As discussed in the previous Office Action as well as the rejection above, claim 19 is rejected over Saito in further view of Fujino (PGPub No. 20200083129). Applicant’s argument initially repeats this (see pgs. 1 and 3 of Remarks), but makes no further mention of Fujino and its relation to Saito in regards to claim 19. Thus, Applicant’s argument is considered unpersuasive and fails to overcome the previous rejection.
Regarding the second argument, Examiner argues that Applicant has not in fact presented an argument, but rather has made conclusory statements in regards to the relationship between references Saito and Chen. Specifically, Applicant only states that Chen relates to semiconductor packages with exposed heat sinks and the heat sinks thereof; no further statements are made and no correlation into how exactly “Chen does not remedy the deficiencies of Saito” is established. Additionally, it should again be noted that Applicant has ignored reference Fujino, as claim 21 was rejected in view of Saito et al. in further view of Chen. Thus, Applicant’s argument is considered unpersuasive and fails to overcome the previous rejection.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/PATRICK CULLEN/Assistant Examiner, Art Unit 2899
/DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899