DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office action is in response to Amendments filed 7/30/2026.
Claim Rejections - 35 USC § 102
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claim(s) 1, 3-5, 11-14, 17-23 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Sasaki et al. (US 10,516,084 B2).
Regarding claim 1, Sasaki discloses a substrate (Fig. 16A, using annotated copy of Fig. 16C below to show details) for manufacturing a display device comprising:
a base part;
assembly electrodes extending in one direction and disposed on the base part at predetermined intervals (the assembly electrodes also including the assembly electrode in the adjacent unit seen in Fig. 16A);
an etch stop layer disposed on at least a portion of the base part (the Examiner notes that actually performing an etch stop function relates to the method in which the device is formed and as long as the layer of Sasaki could be used as an etch stop layer, it qualifies as an etch stop layer; as discussed in the rejection of claim 3, below, the material of the etch stop layer of Sasaki is the same as that claimed (oxide containing indium and tin) and, therefore, could be used as an etch stop layer); and
a barrier wall part (exterior walls of the barrier below) disposed on the etch stop layer while forming a cell on which a semiconductor light emitting device is mounted along an extension direction of the assembly electrodes, wherein the etch stop layer is disposed on at least a first area in which the assembly electrodes are disposed on the base part (see Fig. 16C);
wherein the etch stop layer is further disposed on a second area (area between/outside the two assembly electrodes in the annotated copy of Fig. 16C below, the Examiner notes that there are three portions of the etch stop layer but the “assembly” electrodes are only the two outer electrodes) in which the assembly electrodes are not disposed on the base part, and
wherein the etch stop layer is configured to prevent a short circuit between adjacent assembly electrodes (as there is a gap between the various portions of the etch stop layer such that the portions which touch different assembly electrodes are separated, as seen in the annotated copy of Fig. 16C below, the layer is configured to prevent a short circuit between adjacent assembly electrodes).
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Regarding claim 3, Sasaki further discloses wherein the etch stop layer is an oxide layer comprising Indium and Tin (Col. 6, Line 6).
Regarding claim 4, Sasaki further discloses a first insulating layer disposed on the second area in which the assembly electrodes are not formed on the base part.
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Regarding claim 5, Sasaki further discloses a second insulating layer disposed along an inner surface of the cell and one surface of the barrier wall part (see annotated copy of Fig. 16C, above; the examiner notes that “along” does not require direct contact).
Regarding claim 11, Sasaki further discloses wherein the etch stop layer disposed on a first region (region between the two assembly electrodes shown in Fig. 16C) is thinner than a thickness of the assembly electrodes (as seen in Fig. 16C, the etch stop layer in this region is thinner than the assembly electrodes).
Regarding claim 12, Sasaki further discloses wherein the second insulating layer is disposed to cover the etch stop layer (it covers the sidewall of the etch stop layer).
Regarding claim 13, Sasaki further discloses wherein the etch stop layer is disposed at a same height between the assembly electrodes (as the height of the portion of the etch stop layer that is between the assembly electrodes does not change, the etch stop layer is disposed at a same height between the assembly electrodes).
Regarding claim 14, Sasaki further discloses wherein a side surface of the first insulating layer is in contact (although not direct contact) with the assembly electrodes and the etch stop layer.
Regarding claim 17, Sasaki further discloses wherein the first insulating layer is disposed between the assembly electrodes (it is between the assembly electrodes shown in Fig. 16C and the assembly electrodes in the adjacent region as seen in Fig. 16A).
Regarding claim 20, Sasaki further discloses wherein the first insulating layer is not vertically overlapped with the etch stop layer (see Fig. 16C).
Regarding claim 21, Sasaki further discloses wherein the barrier wall part is spaced apart from the semiconductor light emitting device (separated by the bulk of the barrier, see Fig. 16C).
Regarding claim 22, Sasaki further discloses wherein the lateral width of the etch stop layer (which extends from the leftmost side of the leftmost portion of the etch stop layer to the rightmost side of the rightmost portion of the etch stop layer) is greater than the width of the assembly electrodes (as the widths of the assembly electrodes are individual widths).
Regarding claim 23, Sasaki further discloses wherein semiconductor light emitting device is spaced apart from the assembly electrodes (see Fig. 16C).
Alternatively regarding claim 4, Sasaki further discloses a first insulating layer disposed on a second area in which the assembly electrodes are not formed on the base part.
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Regarding claim 18, Sasaki discloses the substrate according to claim 4 as discussed in the alternative region of claim 4, above. Sasaki further discloses wherein a top surface of the first insulating layer is a height with a top surface of the etch stop layer (see Fig. 16C).
Regarding claim 19, Sasaki discloses the substrate according to claim 4 as discussed in the alternative region of claim 4, above. Sasaki further discloses wherein the first insulating layer is not vertically overlapped with the assembly electrodes (see Fig. 16C; the Examiner notes that the broadest reasonable interpretation of claim 19 only requires as substrate in which the first insulating layer is not vertically overlapped with each of the assembly electrodes, i.e., it includes substrates in which the first insulating layer overlaps one assembly electrode but not the other. As the first insulating layer does not overlap the assembly electrode in the adjacent region, i.e., the other unit in Fig. 16A, the limitation is satisfied).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 24 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sasaki as applied to claim 4 above, and further in view of Tachibana (US 2010/0320482 A1).
Regarding claim 24, Sasaki does not disclose a second insulating layer directly disposed on an inner surface of the cell and one surface of the barrier wall part.
Tachibana, in the same field of endeavor, discloses form an encapsulating insulating material (106 in Fig. 6B) to fill the void space in the device. There was a benefit to forming an encapsulating insulating material as taught by Tachibana in that it adds structural protection to the components of the device. It would have been obvious to one having ordinary skill in the art before the Application's effective filing date to form a second insulating layer formed from an encapsulating material as taught by Tachibana to fill the void spaces in the device of Sasaki (including directly disposed on the inner surface of the cell and one surface of the barrier wall part) for this benefit.
Response to Arguments
Applicant's arguments filed 7/30/2026 have been fully considered but they are not persuasive.
Applicant argues that “the alleged etch stop layer is merely located in areas that also include the alleged assembly electrode”. This argument is not persuasive as the etch stop layer is also in the central portion of 16C and the assembly electrodes are only in the outer regions.
Applicant further argues that “Sasaki merely teaches that all of the alleged etch stop layers are located above all of the alleged assembly electrodes”. This argument is not persuasive as the annotated copy of Fig. 16C used in the present and prior rejections (and copied into the arguments by Applicant) clearly shows through portions of the etch stop layer and only two assembly electrodes. As such, while each of the assembly electrodes are beneath a portion of the etch stop layer, a portion of the etch stop layer is also located between the adjacent assembly electrodes.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRISTOPHER A CULBERT whose telephone number is (571)272-4893. The examiner can normally be reached M-F 9-5.
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/C.A.C/Examiner, Art Unit 2815
/JOSHUA BENITEZ ROSARIO/Supervisory Patent Examiner, Art Unit 2815
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