DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office action is in response to Amendments filed 11/7/2025.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-5, 11-14, and 17-24 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 has been amended to require that the etch stop layer comprise “an electrical insulating material”. It is unclear to one having ordinary skill in the art what Applicant considers to be the metes and bounds of “electrical insulating material” as the only example for such a material presented in Applicant’s specification is ZnO (¶ 0168 of the Specification) which is a semiconducting material (https://www.sciencedirect.com/science/article/pii/S007967271000011X). For the purpose of this Office action, “electrical insulating material” is interpreted as “an electrically insulative material or a semiconducting material”.
Claims 2-5, 11-14, and 17-24 depend from claim 1 and are, therefore, also rejected.
Further regarding claim 24, the claim recites the limitation "the one surface of the barrier wall part" in line 2. There is insufficient antecedent basis for this limitation in the claim.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-5, 11-14, 17-23 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Sasaki et al. (US 10,516,084 B2).
Regarding claim 1, Sasaki discloses a substrate (Fig. 16A, using annotated copy of Fig. 16C below to show details) for manufacturing a display device comprising:
a base part;
assembly electrodes extending in one direction and disposed on the base part at predetermined intervals (the assembly electrodes also including the assembly electrode in the adjacent unit seen in Fig. 16A);
an etch stop layer disposed on at least a portion of the base part (the Examiner notes that actually performing an etch stop function relates to the method in which the device is formed and as long as the layer of Sasaki could be used as an etch stop layer, it qualifies as an etch stop layer; as discussed in the rejection of claim 3, below, the material of the etch stop layer of Sasaki is the same as that claimed and, therefore, could be used as an etch stop layer); and
a barrier wall part (exterior walls of the barrier below) disposed on the etch stop layer while forming a cell on which a semiconductor light emitting device is mounted along an extension direction of the assembly electrodes, wherein the etch stop layer is disposed on at least a first area in which the assembly electrodes are disposed on the base part;
wherein the etch stop layer comprises a semiconducting material (“ITO”, Col. 6, Line 6).
PNG
media_image1.png
477
782
media_image1.png
Greyscale
Regarding claim 2, Sasaki further discloses wherein the etch stop layer is further disposed in a second area (central area in Fig. 16C between the two assembly electrodes shown in Fig. 16C) in which the assembly electrodes are not disposed on the base part.
Regarding claim 3, Sasaki further discloses wherein the etch stop layer is an oxide layer comprising In (Col. 6, Line 6).
Regarding claim 4, Sasaki further discloses a first insulating layer disposed on a second region in which the assembly electrodes are not formed on the base part.
PNG
media_image2.png
495
782
media_image2.png
Greyscale
Regarding claim 5, Sasaki further discloses a second insulating layer disposed along an inner surface of the cell and one surface of the barrier wall part (see annotated copy of Fig. 16C, above; the examiner notes that “along” does not require direct contact).
Regarding claim 11, Sasaki further discloses wherein the etch stop layer disposed on a first region (region between the two assembly electrodes shown in Fig. 16C) is thinner than a thickness of the assembly electrodes (as seen in Fig. 16C, the etch stop layer in this region is thinner than the assembly electrodes).
Regarding claim 12, Sasaki further discloses wherein the second insulating layer is disposed to cover the etch stop layer (it covers the sidewall of the etch stop layer).
Regarding claim 13, Sasaki further discloses wherein the etch stop layer is disposed at a same height between the assembly electrodes (as the height of the portion of the etch stop layer that is between the assembly electrodes does not change, the etch stop layer is disposed at a same height between the assembly electrodes).
Regarding claim 14, Sasaki further discloses wherein a side surface of the first insulating layer is in contact (although not direct contact) with the assembly electrodes and the etch stop layer.
Regarding claim 17, Sasaki further discloses wherein the first insulating layer is disposed between the assembly electrodes (it is between the assembly electrodes shown in Fig. 16C and the assembly electrodes in the adjacent region as seen in Fig. 16A).
Regarding claim 20, Sasaki further discloses wherein the first insulating layer is not vertically overlapped with the etch stop layer (see Fig. 16C).
Regarding claim 21, Sasaki further discloses wherein the barrier wall part is spaced apart from the semiconductor light emitting device (separated by the bulk of the barrier, see Fig. 16C).
Regarding claim 22, Sasaki further discloses wherein the lateral width of the etch stop layer (which extends from the leftmost side of the leftmost portion of the etch stop layer to the rightmost side of the rightmost portion of the etch stop layer) is greater than the width of the assembly electrodes (as the widths of the assembly electrodes are individual widths).
Regarding claim 23, Sasaki further discloses wherein semiconductor light emitting device is spaced apart from the assembly electrodes (see Fig. 16C).
Alternatively regarding claim 4, Sasaki further discloses a first insulating layer disposed on a second region in which the assembly electrodes are not formed on the base part.
PNG
media_image3.png
495
782
media_image3.png
Greyscale
Regarding claim 18, Sasaki discloses the substrate according to claim 4 as discussed in the alternative region of claim 4, above. Sasaki further discloses wherein a top surface of the first insulating layer is a height with a top surface of the etch stop layer (see Fig. 16C).
Regarding claim 19, Sasaki discloses the substrate according to claim 4 as discussed in the alternative region of claim 4, above. Sasaki further discloses wherein the first insulating layer is not vertically overlapped with the assembly electrodes (see Fig. 16C; the Examiner notes that the broadest reasonable interpretation of claim 19 only requires as substrate in which the first insulating layer is not vertically overlapped with each of the assembly electrodes, i.e., it includes substrates in which the first insulating layer overlaps one assembly electrode but not the other. As the first insulating layer does not overlap the assembly electrode in the adjacent region, i.e., the other unit in Fig. 16A, the limitation is satisfied).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 24 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sasaki as applied to claim 4 above, and further in view of Tachibana (US 2010/0320482 A1).
Regarding claim 24, Sasaki does not disclose a second insulating layer directly disposed on the inner surface of the cell and a surface of the barrier wall part.
Tachibana, in the same field of endeavor, discloses form an encapsulating insulating material (106 in Fig. 6B) to fill the void space in the device. There was a benefit to forming an encapsulating insulating material as taught by Tachibana in that it adds structural protection to the components of the device. It would have been obvious to one having ordinary skill in the art before the Application's effective filing date to form a second insulating layer formed from an encapsulating material as taught by Tachibana to fill the void spaces in the device of Sasaki (including directly disposed on the inner surface of the cell and a surface of the barrier wall part) for this benefit.
Response to Arguments
Applicant's arguments filed 11/7/2025 have been fully considered but they are not persuasive.
Applicant argues that Sasaki fails to disclose the newly added limitations to claim 1 as Sasaki discloses using ITO for the etch stop layer. This argument is not persuasive as ITO is a semiconducting material and Applicant’s disclosure of what constitutes an “electrical insulating material” includes semiconducting materials (see 35 USC § 112 rejection of claim 1, above).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRISTOPHER A CULBERT whose telephone number is (571)272-4893. The examiner can normally be reached M-F 9-5.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Joshua Benitez can be reached at (571) 270-1435. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/CHRISTOPHER A CULBERT/ Examiner, Art Unit 2815
Prosecution Insights