DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 2/5/2026 has been entered.
Status of the Application
Acknowledgement is made of the amendment received on 2/5/2026. Claims 11-20 are pending in this application.
Claims 18 and 20 are amended. Claims 11-17 remain withdrawn.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Sasaki et al. (US 2018/0102352; hereinafter ‘Sasaki’) in view of Muranaka et al. (US 2011/0291541; hereinafter ‘Muranaka’) and Chae et al. (US 2019/0189596; hereinafter ‘Chae’).
Regarding claim 18, Sasaki teaches a method for manufacturing a display device (Fig. 4, [0054]), the method comprising:
manufacturing semiconductor light-emitting elements (102) each having recessed portions at a side surface thereof (102 having recessed portions on its sidewalls, Fig. 6A, [0057]);
dispersing the semiconductor light-emitting elements in a fluid accommodated in a fluid chamber (102 is dispersing in 108 within 106, [0048]);
immersing an assembly surface of a substrate in the fluid (400 is immersed in 108);
providing a magnet to move in a direction along one side of the substrate to apply a magnetic force for directing the semiconductor light-emitting elements accommodated in the fluid chamber along the direction (110 moves along one side of 400 to apply a magnetic force that directs 102 within 108 along the same direction); and
applying power to a plurality of electrodes disposed on the assembly surface of the substrate to guide the semiconductor light-emitting elements to preset positions on the substrate (power is applied to electrodes on 904, which corresponds to 400, to guide 102 to target positions, Figs. 15A and 15B, [0077-0078]),
wherein one of the two inner walls for each recessed portion is formed to be an inclined surface and the other of the two inner walls for each recessed portion is formed to be a plane vertical to an upper surface or a lower surface of the semiconductor light-emitting element (the recessed portion having an inclined inner wall facing a straight vertical inter wall, Fig. 6A).
Sasaki does not teach the method comprising: wherein the recessed portions are formed by a plurality of slits continuously arranged.
Muranaka teaches a method (FIGS. 4A-4C, [0037]) comprising: wherein the recessed portions (13, [0039]) are formed by a plurality of slits (15 and 25, [0036]) continuously arranged (15 and 25 are continuously arranged along 17, FIG. 1B, [0039]).
As taught by Muranaka, one of ordinary skill in the art would utilize and modify the above teaching into Sasaki to obtain and achieve the method comprising: wherein the recessed portions are formed by a plurality of slits continuously arranged as claimed, because applying this recessed-slit configuration to achieve a mechanical connection between the LED structure and another element [0021, 0027, 0036].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Muranaka in combination with Sasaki due to above reason.
Sasaki in view of Muranaka does not teach the method comprising: each recessed portion comprises two inner walls facing each other among three inner walls.
Chae teaches a method (FIG. 11, [0094, 0098, 0129]) comprising: each recessed portion comprises two inner walls facing each other among three inner walls (a plurality of recessed portions extending inwardly from outer side surface of the light-emitting structure, each recessed portion being defined by three inner walls, including two inner walls facing each other).
As taught by Chae, one of ordinary skill in the art would utilize and modify the above teaching into Sasaki in view of Muranaka to obtain and achieve the method comprising: each recessed portion comprises two inner walls facing each other among three inner walls as claimed, because providing the recessed portions at outer portions of the light-emitting elements allows various functional configurations [0388] while minimizing interference with the active light-emitting regions.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Chae in combination with Sasaki in view of Muranaka due to above reason.
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Sasaki (US 2018/0102352) in view of Muranaka (US 2011/0291541) and Chae (US 2019/0189596), and further in view of Kim (KR 2009/0087374) and Shin et al. (KR 2008/0069439; hereinafter ‘Shin’).
Regarding claim 19, Sasaki in view of Muranaka and Chae teaches the method of claim 18, wherein the manufacturing of the semiconductor light-emitting elements each having recessed portions at a side surface thereof comprises: forming a conductive semiconductor layer is deposited on a growth substrate (Sasaki: forming GaN LEDs, Fig. 5, [0055]).
Sasaki in view of Muranaka and Chae does not teach the method comprises: forming an epitaxial layer in which a first conductive semiconductor layer, an active layer, and a second conductive semiconductor layer are sequentially deposited on a growth substrate; depositing a photoresist layer in which the plurality of slits are continuously formed on the second conductive semiconductor layer; and irradiating light onto the photoresist layer to form semiconductor light-emitting elements each having the recessed portions at a side surface thereof, and wherein the plurality of slits form recessed portions each comprising the inclined surface.
Kim does teach a method (p3, lines 10-12) comprises:
forming an epitaxial layer in which a first conductive semiconductor layer and a second conductive semiconductor layer are sequentially deposited on a growth substrate (forming 11 in which 11a and 11b are sequentially deposited on 10, Fig. 2a, lines 15, 17, 23);
depositing a photoresist layer in which the plurality of slits are continuously formed on the second conductive semiconductor layer (depositing a patterned photoresist layer on 11b, line 18); and
irradiating light onto the photoresist layer to form semiconductor light-emitting elements each having the recessed portions at a side surface thereof (etching using the patterned photoresist to form on a side surface of 11a, Fig. 2b, line 24-25).
Although Kim does not explicitly teach the method comprising: forming an epitaxial layer includes an active layer between the first conductive semiconductor layer and the second conductive semiconductor layer, and irradiating light onto the photoresist layer.
Kim, however, recognizes that the epitaxial layer form a “cell” which refers to the area where light is emitted from the light emitting diode (p3, line 26). In order for such light emission to occur, the presence of an active layer between the first conductive semiconductor layer (11a) and the second conductive semiconductor layer (11b) is inherently required, even though it is not explicitly disclosed. Furthermore, it is well understood in the art that photoresist materials are commonly patterned or etched through exposure to light.
As taught by Kim, one of ordinary skill in the art would utilize and modify the above teaching into Sasaki in view of Muranaka and Chae to obtain and achieve the method comprising: forming an epitaxial layer includes an active layer between the first conductive semiconductor layer and the second conductive semiconductor layer, and irradiating light onto the photoresist layer as claimed, because it is well-known in the art that an active layer is present between the conductive semiconductor layers to enable light emission, and that photoresist layers are commonly processed by exposure to irradiated light.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Kim in combination with Sasaki in view of Muranaka and Chae due to above reason.
Sasaki in view of Muranaka, Chae, and Kim does not teach the method comprises depositing a photoresist layer in which the plurality of slits, wherein the plurality of slits form recessed portions each comprising the inclined surface.
Shin teaches a method (FIG. 2, [1]) comprises depositing a photoresist layer in which the plurality of slits (200 having 230, p5, lines 20, 24), wherein the plurality of slits form recessed portions each comprising the inclined surface (forming inclined photoresist patterns 112 and 114 using 230, p5, lines 37-38).
As taught by Shin, one of ordinary skill in the art would utilize and modify the above teaching into Sasaki in view of Muranaka, Chae, and Kim to obtain and achieve the method comprises depositing a photoresist layer in which the plurality of slits, wherein the plurality of slits form recessed portions each comprising the inclined surface as claimed, because forming recessed portion with the inclined surface improves structural conformity and enables precise junctions in semiconductor devices. Further, it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended used a matter of obvious design choice. In re Leshin, 125 USPQ 416.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Shin in combination with Sasaki in view of Muranaka, Chae, and Kim due to above reason.
Allowable Subject Matter
Claim 20 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
The applied prior art neither anticipates nor renders the claimed subject matter obvious because it fails to teach the claimed method for manufacturing a display device,
“an angle between each of the plurality of inclined surfaces and one surface of the semiconductor light-emitting element in contact with the substrate increases as a distance from the substrate increases” in combination with all other limitations, as recited in claim 20.
The closest prior arts include Park et al. (US 2022/0399313), Jeon et al. (US 2020/0235077), Choi et al. (US 2018/0351033). These references teach various recessed structures formed in surfaces of light-emitting device assemblies. However, the prior art does not teach or suggest recessed portions having a multi-stage inclined profile in which the inclination angle progressively increases along the thickness direction.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Response to Arguments
Applicant's arguments with respect to claims have been considered but are moot in view of the new ground of rejection. Response to arguments on newly added limitations are responded to in the above rejection.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure. Goshonoo (US 2023/0187429), Kono et al. (US 2023/0335696), Keller et al. (US 2012/0138996), and Yang et al. (US 2013/0020598) as a light emitting device with a semiconductor light emitting element and a device substrate.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JIYOUNG OH whose telephone number is (703)756-5687. The examiner can normally be reached Monday-Friday, 9AM-5PM EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eva Montalvo can be reached on (571) 270-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/JIYOUNG OH/Examiner, Art Unit 2818
/DUY T NGUYEN/Primary Examiner, Art Unit 2818 7/27/26
Prosecution Insights