DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 01/12/2026 has been entered.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 11, 17, and 19 are rejected under 35 U.S.C. 103 as being unpatentable Jeon (U.S. PG Pub No US2018/0102301A1) (of record) in view of Kimura (U.S. PG Pub No US2016/0307817A1) (of record), Tang (KR Pub No CN103531704A), and Jeon-II (U.S. PG Pub No US2016/0126157A1). (See attached translation of Tang for [] citation #’s).
Regarding claim 11, Jeon teaches a method of manufacturing a power module [see title], comprising:
preparing a first substrate (200 base) fig. 3 [0029] comprising a ceramic base [0010, 0013, 0036] and an electrode pattern (610) [0010] brazed to (upon) [0041] at least a first surface of the ceramic base (200), and having an upper surface on which at least one semiconductor chip (310/320) fig. 3 [0010] is mounted;
preparing a spacer (410) fig. 3 [0041] (see fig. 5 for label);
forming a brazing bonding layer (B) fig. 3 [0041] (directly) on the spacer (410);
wherein the forming of the brazing bonding layer (B) includes forming, on the spacer (410),
a brazing bonding layer (B) having a two-layer structure (upper and lower B) in which an (first) layer (upper B) and a (second) layer (lower B) are stacked,
the (first) layer (upper B) being disposed to be in (direct) contact with the electrode pattern (610) disposed on (supported by) the upper surface of the first substrate (200),
and the (second) layer (lower B) being disposed to be in (direct) contact with a lower surface of the spacer (410);
arranging the spacer (410) on (supported by) the pattern (610) of the first substrate (200) to interpose the brazing bonding layer (lower B) between the pattern (610) of the first substrate (200) and a lower surface of the spacer (410) (see also fig. 5);
performing heat treatment [0041-0043] on the brazing bonding layer (B) and brazing and bonding [0041, 0043] the lower surface of the spacer (410) to the pattern (610) of the first substrate (200);
preparing a second substrate (100) fig. 3 [0029] comprising a ceramic base [0010, 0013, 0036] and an (a) pattern (620) fig. 3 [0010] brazed to at least a first surface (bottom) of the ceramic base (100);
forming a bonding layer (upper B layer directly atop 620) [0041] on (collectively supported in structure by) an upper surface of the spacer (410 on left side – see fig. 5 for label);
arranging the second substrate (100) fig. 3 [0029] on the spacer (410 on left side – see fig. 5 for label) to interpose the bonding layer (upper B layer atop 620) (diagonally) between the pattern (620) of the second substrate (100) and the upper surface of the spacer (top of 410); and
bonding the upper surface of the spacer (410) to the pattern of the second substrate (100) by medium of the bonding layer (upper B on 620) (collectively bonded in bonded structure).
However, Jeon does not explicitly disclose a first substrate (200) comprising an electrode pattern and a second substrate comprising an electrode pattern (610/620 not taught as electrode patterns [0010]),
preparing a spacer formed of an electrically-insulating ceramic material (material of “spacer” 410 [0032] not specified);
a brazing bonding layer (B) having a two-layer structure in which an AgCu layer including Ag and Cu and a Ti layer including Ti are stacked,
the AgCu layer being disposed to be in contact with the electrode pattern (610), and
the Ti layer being disposed to be in contact with a lower surface of the spacer (410),
wherein, in the arranging of the spacer (410) on the electrode pattern of the first substrate (200), a plurality of spacers are disposed around an edge of the upper surface of the first substrate (200) at regular intervals such that the plurality of spacers surround the semiconductor chip (310/320) mounted on the upper surface of the first substrate (200) (insufficient diagrammatic information).
Kimura teaches a method of manufacturing a power module [see title, 0010] comprising a first substrate (2) fig. 5 [0039-0041] comprising an electrode pattern (left 10) fig. 5 [0039] and a second substrate (9) fig. 5 [0039-0041] comprising an electrode pattern (right 10) fig. 5 [0039];
preparing a spacer (6) fig. 5 [0030, 0034-0036, 0041] formed of ceramic material [0030, 0036].
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the metal patterns in the power module of Jeon to comprise the metal electrode patterns of Kimura [0039-0041] in order to enable the formation of an “intelligent” power module [0039] with a two-story structure [0040] that optimizes module mounting properties [0041] as well as heat dissipation properties and costs [0041], as taught by Kimura. Further, Kimura teaches that use of a ceramic spacer reduces warpage due to temperature change(s) [0030, 0036 Kimura].
However, Jeon in view of Kimura does not explicitly disclose preparing a spacer formed of an electrically-insulating ceramic material (ceramic material of “spacer” not specified in either Jeon or Kimura),
a brazing bonding layer (B) having a two-layer structure in which an AgCu layer including Ag and Cu and a Ti layer including Ti are stacked,
the AgCu layer being disposed to be in contact with the electrode pattern (610), and
the Ti layer being disposed to be in contact with a lower surface of the spacer (410),
wherein, in the arranging of the spacer (410) on the electrode pattern of the first substrate (200), a plurality of spacers are disposed around an edge of the upper surface of the first substrate (200) at regular intervals such that the plurality of spacers surround the semiconductor chip (310/320) mounted on the upper surface of the first substrate (200) (insufficient diagrammatic information).
Tang teaches a method [see title] comprising preparing a spacer (1) fig. 1 [lines 127-145] formed of an electrically-insulating ceramic material (glass such as aluminosilicate) [lines 127-138],
a brazing bonding layer (2-4) fig. 1 [lines 147-171, lines 564-581] having a two-layer structure in which an AgCu layer (3 with 4) fig. 1 [lines 565, 581] including Ag (AgCu portion 4) [line 581] and Cu (portion 3) [line 565] and a Ti layer (2) fig. 1 [line 565] including Ti are stacked,
the AgCu layer (3 with 4) being disposed to be in contact with the electrode pattern (5) fig. 1 [line 581], and
the Ti layer (2) being disposed to be in contact with a lower surface (lower half) of the spacer (1) fig. 1 [lines 127-145, lines 543-546].
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the brazing bonding layers of Jeon in view of Kimura to comprise the AgCu/Ti stack of Tang [lines 127-145, 564-581] in order to enhance the electrical connection with the electrode [lines 194-211] while improving thermal resistance properties of the package [lines 194-211], as taught by Tang.
However, Jeon in view of Kimura and Tang does not explicitly disclose
wherein, in the arranging of the spacer (410) on the electrode pattern of the first substrate (200), a plurality of spacers are disposed around an edge of the upper surface of the first substrate (200) at regular intervals such that the plurality of spacers surround the semiconductor chip (310/320) mounted on the upper surface of the first substrate (200) (insufficient diagrammatic information).
Jeon-II teaches a method [see title, 0044] wherein, in the arranging of the spacer (comprising 212, 251-1/251-2, 252-1/252-2) fig. 2 [0044-0045] (spacers composed of ceramic material [0014]) on the electrode pattern (comprising 213-3) fig. 2 [0045] of the first substrate (213) fig. 2 [0045], a plurality of spacers (comprising 212, 251-1/251-2, 252-1/252-2) fig. 2 [0044-0045] (spacers composed of ceramic material [0014]) are disposed around (collectively surrounding) an edge of the upper surface of the first substrate (top of 213-2) at regular intervals (equally spaced around the chips) such that the plurality of spacers (comprising 212, 251-1/251-2, 252-1/252-2) (collectively) surround the semiconductor chip (232) fig. 2 [0044] mounted on the upper surface of the first substrate (top of 213-2) [see also fig. 5, 0063].
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the power module of Jeon in view of Kimura and Tang to include the plurality of horizontal and vertical ceramic spacers [0014, 0044] of Jeon-II in order to improve thermal diffusion performance [0009, 0064] of the power module package [0073] so as to improve device reliability [0073] and reduce production costs [0073], as taught by Jeon-II.
Regarding claim 17, Jeon teaches the method [see title] of claim 11. Jeon also teaches wherein, in the brazing and bonding [0043] of the spacer (410) fig. 3 [0041] to the first substrate (200) fig. 3 [0029], heat treatment is performed at a temperature ranging from 780 °C to 900 °C (800 °C [0043]).
Regarding claim 19, Jeon teaches the method [see title] of claim 11. Jeon also teaches wherein, in the forming the bonding layer (B) fig. 3 [0041], solder (comprising Ag) [0043] is applied to one surface of the spacer (410) fig. 3 [0041] (see fig. 5 for label) to form the bonding layer (B).
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable Jeon (U.S. PG Pub No US2018/0102301A1) (of record) in view of Kimura (U.S. PG Pub No US2016/0307817A1) (of record), Tang (KR Pub No CN103531704A), and Jeon-II (U.S. PG Pub No US2016/0126157A1), as applied in claim 11 above, and further in view of Oi (U.S. PG Pub No US2012/0267149A1) (of record).
Regarding claim 13, Jeon teaches the method [see title] of claim 11. However, Jeon does not explicitly disclose wherein, in the preparing of the spacer (410), the spacer (410) formed of one selected from A1203, ZTA, Si3N4, and AlN or a mixture of two or more thereof is prepared (spacer material(s) not specified).
Oi teaches a method [see title] wherein, in the preparing of the spacer (3) fig. 1 [0042], the spacer (3) formed of one selected from Al2O3 and AlN [0042].
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the power module of Jeon such that the spacer layer(s) interposed between the metal layers is composed of a dielectric material such as aluminum oxide or aluminum nitride [0042] because of the material’s art recognized suitability to support, selectively-separate, and bond with [0039-0042] the metal material, as taught by Oi.
Claims 14-15 are rejected under 35 U.S.C. 103 as being unpatentable Jeon (U.S. PG Pub No US2018/0102301A1) (of record) modified by Kimura (U.S. PG Pub No US 20160307817 A1) (of record), Tang (KR Pub No CN103531704A), and Jeon-II (U.S. PG Pub No US2016/0126157A1), as applied in claim 11 above, and further in view of Yuasa (U.S. PG Pub No US2020/0163210A1) (of record).
Regarding claim 14, Jeon teaches the method [see title] of claim 11. However, Jeon does not explicitly disclose wherein the forming of the brazing bonding layer (B) further includes forming an AgCu layer on the first substrate (200) or the spacer (410) by any one among paste printing, foil attachment, and filler attachment.
Yuasa teaches a method [see title] wherein the forming of the brazing bonding layer (7) fig. 2 [0052] further includes forming an AgCu layer [0055-0057] on the first substrate (1) fig. 1 [0052] or the spacer (2) fig. 2 [0052] by paste printing [0041].
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the power module of Jeon such that brazing layer is formed by the printing method [0041] using the brazing bonding layer comprising materials such as silver and copper [0055-0057] disclosed by Yuasa because of the method’s ability to improve thermal cycling resistance [0013] and device reliability [0045], as taught by Yuasa.
Regarding claim 15, Jeon teaches the method [see title] of claim 14. Jeon in view of Yuasa (with reference to Yuasa) also teaches wherein the forming of the brazing bonding layer (7) fig. 2 [0052] further includes forming (providing) a Ti layer [0039, 0059] before the forming of the AgCu layer [0055-0057].
Response to Arguments
Applicant’s arguments, see pages 2-3, filed 01/12/2026, with respect to the rejection(s) of claim(s) 11 under 35 U.S.C. 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Tang (KR Pub No CN103531704A) under 35 U.S.C. 103.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Malhan (U.S. PG Pub No US2008/0054425A1) (of record) teaches an alternative method of forming a power module using a brazing bonding layer. Remaining references on the PTO-892 form (of record) teach other examples of power modules with spacer-pillars.
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/SEAN AYERS WINTERS/Examiner, Art Unit 2892 01/29/2026
/NORMAN D RICHARDS/Supervisory Patent Examiner, Art Unit 2892