Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
The response of the applicant has been read and given careful consideration. Rejection of the previous action, not repeated below are withdrawn based upon the amendment and arguments of the applicant. Responses to the arguments of the applicant appear after the first rejection they are directed to.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-4, 6-13 and 15-21 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
The claims should make it clear that the thin film is a light shielding film as this is the layer with the recited reflectance and thickness range. See the specification at [0043,0046,0094,0108] of the prepub.
In claim 17 , it should be made clear that “its edge” is adjacent the outer peripheral region.
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim 17 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
It is not clear that the specification as filed discloses the patterned mask where the thin film becomes thinner towards its edge. The processing taught uses a hard mask with a 146 nm x 146 mm size [0072] which is less than the size of the light shielding layer and when processing the peripheral region will be etched away.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 8-11 and 18-19 are rejected under 35 U.S.C. 102(a)(1) as anticipated by Nozawa et al. 20180299767 as evidenced by Fukaya et al. 20150010853 or, in the alternative, under 35 U.S.C. 103 as obvious over Nozawa et al. 20180299767 in view of Fukaya et al. 20150010853.
Nozawa et al. 20180299767 teaches with respect to figure 1, a substrate (1) with a chamfer, coated up to the chamfer with a 69 nm MoSiON phase shift layer which was heat treated at 450 degrees C for 1 hour, this was then overcoated with a 36 nm CrOC light shielding film. Which was heat treated at 280 degrees C for 5 minutes. This was then coated with a 12 nm silicon dioxide hard mask. This mask blanks was then patterned to form patterned photomask and then evaluated for pattern transfer with a (simulated) exposure of a resist [0122-0145].
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The embodiments of this invention are explained below. First, the background of this invention is explained. As chromium (Cr)-based materials constructing conventional mask blanks, materials containing nitrogen (N) such as CrON and CrOCN are known. This is because defect quality of a chromium-based material film is enhanced by using nitrogen gas in addition to oxygen-containing gas as a reactive gas when forming a chromium-based material film by sputtering method. Further, by combining nitrogen in a chromium-based material film, etching rate of dry etching by oxygen-containing chlorine-based gas increases. On the other hand, a film-forming method where sputtering is carried out upon forming a film of a Cr-based material is being done in a chromium-based material film. Since this sputtering can enhance defect quality of a chromium-based material film, film-forming without the use of N.sub.2 gas for enhancing defect quality is possible [0057]. Further, the light shielding film 3 should function as an etching mask upon dry etching by fluorine-based gas for forming a transfer pattern (phase shift pattern) on the phase shift film 2. Therefore, the light shielding film 3 should be made from materials having sufficient etching selectivity to the phase shift film 2 upon dry etching by fluorine-based gas. It is required for the light shielding film 3 to precisely form a fine pattern that is to be formed on the phase shift film 2. Film thickness of the light shielding film 3 is preferably 60 nm or less, more preferably 55 nm or less, and further preferably 50 nm or less. When the film thickness of the light shielding film 3 is too thick, the fine pattern to be formed cannot be created at a high precision. On the other hand, it is required for the light shielding film 3 to satisfy the required optical density as given above. Therefore, the film thickness of the light shielding film 3 is desired to be greater than 15 nm, preferably 20 nm or more, and further preferably 25 nm or more [0079].
Fukaya et al. 20150010853 illustrates in figure 4, the chamfered part 11 of the substrate 10 is formed inward from the outer end part at a width (b) of approximately 0.2 mm to 1 mm and the substrate is bare for a width of (a) [0067].
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In example 1, a 50 nm CrON light shielding film is coated on a 6025 substrate [0105-0115]. Phase shift masks are also disclosed [0078].
Nozawa et al. 20180299767 teaches in example 1 with respect to figure 1, a photomask blanks formed on a substrate with chamfered edges which are uncoated by the phase shift or light shielding layer, but does not describe the size/width of the chamfer.
With respect to claims 8-11 and 18-19 , the examiner asserts that the chamfer used in example 1 of Nozawa et al. 20180299767 was 0.2 to 0.5 mm which is within the 0.2-1.0 mm range evidenced by Fukaya et al. 20150010853 as known in the art and therefore the patterned photomasks produced which have a useful area defined by the dimensions of the hard mask (4) which extends to the chamfer and process of its use which does not require the tapered edges in the patterned mask.
If this position is not upheld with respect to claims 8-11 and 18-19 , the examiner holds that it would have been obvious to one skilled in the art to modify example 1 of Nozawa et al. 20180299767 by using a substrate with a chamfer of 0.2 to 0.5 mm which is within the 0.2-1.0 mm range evidenced by Fukaya et al. 20150010853 where the phase shift layer, light shielding layer and/or hard mask layer do not cover the chamfer region as shown in figure 1 with a reasonable expectation of forming a useful patterned mask and useful semiconductor device. As these modifications are congruent with the teachings of Nozawa et al. 20180299767.
In response to the arguments of 10/24/2025 and 9/25/2025, As discussed previously, the patterned mask claims rejection under this heading do not require that the tapered peripheral region be retained in the patterned mask. The examiner notes that the inventive example used a 146 nm x 146 mm silicon dioxide hard mask, which trims the periphery of the mask blank.
Claims 8-11 and 18-19 are rejected under 35 U.S.C. 103 as obvious over Inazuki et al. 20160266485.
Inazuki et al. 20160266485 in example 3 coated a 6025 substrate (152mm square substrate) with a 75 MoSiON phase shift layer using a deposition mask with a 150 mm square opening spaced away from the substrate. Then a 44 mm CrON layer was coated using a deposition mask with a 150 mm square opening spaced away from the substrate. Then a 5 nm SiO hard mask was coated using a deposition mask with a 146 mm square opening spaced away from the substrate [0046-0047]. The phase mask including the side surface, chamfer, front surface/chamfer boundary and backsurface/chamfer boundary were inspected and no deposited materials was observed [0048]. The substrate is typically a chamfered rectangular plate, especially square plate, but not limited thereto. The substrate has a front surface on which an optical functional film or a processing aid film is formed, a back surface (opposed to the front surface), side surfaces (four surfaces in substrate thickness direction), and chamfers between the front or back surface and the side surfaces (four chamfers on each of the front and back surfaces, total eight). Although there are a plurality of side surfaces, chamfers and boundaries, they are herein referred to in singular form for simplicity sake. For example, a 6-inch square substrate (6025 substrate, 152 mm×152 mm×6.35 mm), which is typically used in photomask blanks for LSI fabrication, is provided with a chamfer (also known as C face) of about 0.5 mm wide between the front surface and the side surface or between the back surface and the side surface, at an angle of about 45° relative to the side surface. On the other hand, the optical functional film may be a light-shielding film, a light-shielding film including an antireflective film, or a phase shift film, typically halftone phase shift film. The processing aid film may be a hard mask film (or etching mask film), an etching stop film, or an electrically conductive film [0025]. Figure 1C illustrates the substrate (11) with a chamfer, a phase shift layer (12), a light shielding layer (13) and a hard mask (14) (not to scale) [0034]. Figure 2 shows the deposition mask (2) spaced from the substrate (11) having a chamfer
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(not to scale).
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The mask blank is prepared by depositing the film of a single layer or plural layers by sputtering. A shield member is placed on the substrate, but closely spaced apart therefrom to cover a predetermined region of the substrate so that the film may not be deposited on the predetermined region of the substrate, that is, the side surface, chamfer, front surface-chamfer boundary, and back surface-chamfer boundary of the substrate. Specifically, as shown in FIG. 2, a shield member 2 is placed between a transparent substrate 11 and a sputter target (not shown) and closely spaced apart from the substrate 11 so as to cover a peripheral portion of the front surface of the substrate 11 and extend outward from the front surface-chamfer boundary. With this setup, the target material is sputtered toward the front surface of the substrate 11 to deposit a film thereon. Also illustrated in FIG. 2 are a support member 21 for the shield member 2, a platform 3 on which the substrate 11 is rested, and a wedge or jig 31 for providing point or line support to the substrate 11. If it is desired to alter the region where the film is deposited, the opening of the shield member may be accordingly altered. In an example using a 6-inch square substrate, if a shield member having an opening of 150 mm squares is used, then the region of film deposition is a region of the front surface that extends inward from a line of 1 mm apart from the side surface; if a shield member having an opening of 146 mm squares is used, then the region of film deposition is a region of the front surface that extends inward from a line of 3 mm apart from the side surface [0039]. A process of preparing a mask from the mask blank generally involves the steps of forming a resist film on the mask blank, and patterning the resist film using an EB writing system. For effective operation of the EB writing system, at least one electrically conductive film is included in the mask blank so that the EB projected to the mask blank may not cause any charge-up to the mask blank. For the purpose of preventing the EB projected to the mask blank from causing any charge-up thereto, the EB writing system generally includes a ground pin which comes in contact with the outer periphery of the front surface of the mask blank for grounding the mask blank [0031]. This invention relates to a mask blank which is processed to form a mask (transfer mask) for use in the microfabrication of semiconductor integrated circuits or the like, and a method for preparing the mask blank [0002].
Inazuki et al. 20160266485 forms a mask blank which includes a hard mask used to remove peripheral portions of the phase shift and CrON light shielding layer and a substrate with chamfered edges, but does not exemplify patterning the mask blank or using the resulting pattern mask in a lithographic process.
With respect to claims 8,9 and 18, it would have been obvious to pattern the mask blank of example 3 using the process described at [0031] with a reasonable expectation of forming a useful patterned photomask.
With respect to claims 8-11 and 18-19, it would have been obvious to pattern the mask blank of example 3 using the process described at [0031] with a pattern appropriate to form semiconductor integrated circuits and to use the patterned mask in the formation of integrated circuits as disclosed at [0002] with a reasonable expectation of forming useful semiconductor integrated circuits based upon the disclosure.
Claims 1-4,12,13 and 20-21 are rejected under 35 U.S.C. 103 as being unpatentable over Hamamoto et al. 20150301441 and Shoki et al. 20150079501, in view of Fukaya et al. 20150010853.
Hamamoto et al. 20150301441 in examples 1 teaches a 152.4 x 152.4 x 6.35 substrate coated with a where the ML is coated 149 mm square, the capping layer is coated to 149 mm square, the absorber film is 151.0 mm. The backside was coated with a 20 nm thickness of TaN [0196-2014]. In figure 1, the coverage of the absorber layer and the backside conductive layer appears to be the same in figure 1. In example 3, the conductive film is 151 mm square [0231]. In figures 11 and 12, the backside conductive layer appears to extend to the edge of the chamfer.
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As described earlier, for example, as the multilayer reflective film 2 for EUV light having a wavelength of 13 to 14 nm, use is preferably made of a Mo/Si cycle multilayer film in which Mo films and Si films are alternately laminated by about 40 cycles. Usually, the multilayer reflective film 2 is formed by ion-beam sputtering, magnetron sputtering, or the like. In this embodiment, since the outer peripheral end of the multilayer reflective film 12 should be adjusted to the predetermined relationship with the outer peripheral ends of the other films, it is possible to apply a film forming method provided with a shielding member 30 as shown in FIG. 7. By providing the shielding member 30 so as to be spaced apart from the peripheral edge portion of the substrate 1, sputtered particles are prevented from being deposited on the peripheral edge portion of the substrate 1. Further, by providing the shielding member 30, a film thickness gradient region 21 can be formed in an outer peripheral region of the multilayer reflective film. By adjusting a distance h between the main surface of the substrate 1 and the shielding member 30, a shielding length W by the shielding member 30, and the incident angle of sputtered particles with respect to the normal of the main surface of the substrate 1, the distance L(ML) from the center of the substrate 1 to the outer peripheral end of the multilayer reflective film 2 and the thickness and inclination angle in the film thickness gradient region 21 can be controlled [0131].
Shoki et al. 20150079501 in example 1 teaches a 152.4 x152.4 x 6.35 mm substrate which is coated with a reflective multilayer using a shield which covers 1.3 mm of the edge of the substrate at a height of 0.3 mm which yields a sloped region which is 2.5 mm wide. A protective RuNb layer is then coated, fiducial marks were then formed by focused ion beam etching [0113-0118]. a 20 nm CrN conductive backside layer (12) and an absorber layer (16) and the mask blanks were patterned [0127-0133]. Assuming the 2.5 mm slope is symmetric about the edge of the deposition shield/mask, it extends 0.05 mm from the edge.
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Provided that the size of the substrate 11 is 152 mm.times.152 mm, the slope region 90 is preferably disposed in a region having a width of 5 mm from the sides 72 of the substrate 11, namely, in a region outside the 142 mm.times.142 mm region, thereby ensuring that the slope region does not affect an absorber film pattern 22 of a reflective mask 2. In this case, the width of the slope region illustrated in FIG. 7, Dslope, is 5 mm. Provided that the size of the substrate 11 is 152 mm.times.152 mm similarly to the above, the slope region 90 may be more preferably disposed between the 142 mm.times.142 mm size and the 150 mm.times.150 mm size excluding the region having a width of 1 mm from the sides 72 of the substrate 11, and still more preferably disposed between the 142 mm.times.142 mm size and the 148 mm.times.148 mm size [0065,0067]. The height h between the principal surface 71 of the substrate 11 and the shielding member 68 is preferably 0.1 mm to 1.0 mm, and more preferably 0.2 mm to 0.6 mm. The shielding length L of the shielding member 68 is preferably 0.5 mm to 4.0 mm, and more preferably 1.0 mm to 2.0 mm [0071].
Hamamoto et al. 20150301441 in example 3 teaches the coating of 20 nm TaN as a backside conductive layer where it is 0.7 mm from the side ( {152.4 mm -151 mm}/2 ), which is outside the 0-0.5 mm range claimed and this examples does not describe the use of a chamfered substrate.
With respect to claims 1-4,12,13 and 20-21 , it would have been obvious to one skilled in the art to modify the process of coating the 20 nm TaN backside layer in example 3 of Hamamoto et al. 20150301441 by using a chamfer of 0.2 to 0.5 mm disclosed by Fukaya et al. 20150010853 as being useful chamfer sizes known in the art and chamfered substrates being illustrated in Hamamoto et al. 20150301441 and increasing the spacing of the deposition mask from the surface to increase the width and area of the deposited film as taught by Shoki et al. 20150079501 at [0071] to be within 0.2 to 0.5 mm (the edge of the chamfer transition) of the side of the substrate with a reasonable expectation of forming a useful mask based upon the illustration of the coating of the conductive layer extending to the transition to the chamfered surface in figures 11 and 12 Hamamoto et al. 20150301441. The examiner notes that the instant specification describes the use of TaN as a light shielding film at [0047].
Shoki et al. 20150079501 teaches the coating of a 20 nm CrN layer a s a backside conductive layer, but does not describe size/extent of the coating or a chamfer on the substrate.
With respect to claims 1-4,12,13 and 20-21 , it would have been obvious to one skilled in the art to modify the process of coating the 20 nm CrN backside layer in example 1 of Shoki et al. 20150079501 [0113-0118,0127-0133] by using a chamfer of 0.2 to 0.5 mm disclosed by Fukaya et al. 20150010853 as being useful chamfer sizes known in the art and chamfered substrates being illustrated in figure 5 of Shoki et al. 20150079501 and using a deposition mask with a size and spacing to adjust the size/area of the deposited film as taught by Shoki et al. 20150079501 at [0071] to be within 0.2 to 0.5 mm (the edge of the chamfer transition) of the side of the substrate with a reasonable expectation of forming a useful mask based upon the illustration of the coating of the conductive layer extending to the transition to the chamfered surface in figures 11 and 12 Hamamoto et al. 20150301441. The examiner notes that the instant specification describes the use of Cr with nitrogen as a light shielding film at [0039] and quartz glass substrates and holds that the reflectance of the polished substrate is inherent and that the reflectance of the 9-10 nm thickness of the CrON light shielding layer is also inherent to the coated CrON material.
In the response of 9/25/2025 and 10/24/2025, the applicant argues that the references do not disclose the contrast ratio. The examiner notes that the instant specification describes the use of Cr with nitrogen as a light shielding film at [0039] and quartz glass substrates and holds that the reflectance of the polished substrate is inherent and that the reflectance of the 9-10 nm thickness of the CrON light shielding layer is also inherent to the coated CrON material and therefore the ratio limitation is met for the materials of the prior art which are among those disclosed in the instant specification. The examiner is open to an evidentiary showing by the applicant. The applicant argues that the CrOC is used in the comparative example had a thickness of 24 nm (and seems to use the same 150mm x 150 mm deposition mask for both the deposition of the phase shift layer and the light shielding layer [0081], while the inventive example uses a 146 mm x 146 mm mask for the phase shift deposition and a 150 x 150 mm mask for the light shielding layer). The 9-10 nm thicknesses had a reflectance of 14.85% [0083], which was less than the 23.65% [0070] of the inventive example. The reflectance of the polished substrate was 6.62 to 6.99% [0087]. There may be an issue with the 9-10 nm thickness in the comparative example being a combined thickness of light shielding layer and phase shifting layer to make the 910 nm thickness. The comparative example with a 24 nm thickness of CrOC does not represent a comparison which is equal to a preferable to a direct comparison with the (44 nm) CrON coating of prior art. Also as the inventive example trims the peripheral region outside the hard mask it is not clear what benefit is realized in the patterned mask which is attributable to the tapered edge when the argued tapered thickness has been removed in the inventive examples.
Claims 1-4,6-13,15-16, and 18-20 are rejected under 35 U.S.C. 103 as obvious over Inazuki et al. 20160266485, in view of Hamamoto et al. 20150301441, Shoki et al. 20150079501, Fukaya et al. 20150010853 and Nozawa et al. 20020110741.
Nozawa et al. 20020110741 teaches with respect to figure 2, the masked deposition of the MoSiN halftone phase shifting film where the film is formed 2 mm form the edge of the substrate [0080-0088]. The clearance of the shielding plate from the is moveable/adjustable with a precision of 0.1 mm [0074].
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Inazuki et al. 20160266485 in example 3 does not describe the size of the chamfer or the height of the deposition mask.
With respect to claims 1-4,6-7,12,13,,15-16, and 20-21, it would have been obvious to one skilled in the art to modify the process of example 3 of Inazuki et al. 20160266485 by using a substrate with a chamfer of using a chamfer of 0.2 to 0.5 mm disclosed by Fukaya et al. 20150010853 as being useful chamfer sizes known in the art and chamfered substrates being illustrated in Hamamoto et al. 20150301441 and increasing the spacing of the deposition mask from the surface to increase the width and area of the deposited film as taught by Shoki et al. 20150079501 at [0071] and Nozawa et al. 20020110741 to be within 0.2 to 0.5 mm (the edge of the chamfer transition) of the side of the substrate with a reasonable expectation of forming a useful mask based upon the illustration of the coating of the conductive layer extending to the transition to the chamfered surface in figures 11 and 12 Hamamoto et al. 20150301441 and the disclosure in Inazuki et al. 20160266485 of keeping the deposited materials on the front surface of the mask and not allowing it to be formed on the sides or in the chamfer region at [0048].
With respect to claims 1-4,6-9,12,13,15-18, and 20, it would have been obvious to one skilled in the art to modify the process of example 3 of Inazuki et al. 20160266485 by using a substrate with a chamfer of using a chamfer of 0.2 to 0.5 mm disclosed by Fukaya et al. 20150010853 as being useful chamfer sizes known in the art and chamfered substrates being illustrated in Hamamoto et al. 20150301441 and increasing the spacing of the deposition mask from the surface to increase the width and area of the deposited film as taught by Shoki et al. 20150079501 at [0071] and Nozawa et al. 20020110741 to be within 0.2 to 0.5 mm (the edge of the chamfer transition) of the side of the substrate with a reasonable expectation of forming a useful mask based upon the illustration of the coating of the conductive layer extending to the transition to the chamfered surface in figures 11 and 12 Hamamoto et al. 20150301441 and the disclosure in Inazuki et al. 20160266485 of keeping the deposited materials on the front surface of the mask and not allowing it to be formed on the sides or in the chamfer region at [0048] and to pattern the resulting mask blank using the process described at [0031] of Inazuki et al. 20160266485 with a reasonable expectation of forming a useful patterned photomask.
With respect to claims 1-4,6-13, and 15-20, it would have been obvious to one skilled in the art to modify the process of example 3 of Inazuki et al. 20160266485 by using a substrate with a chamfer of using a chamfer of 0.2 to 0.5 mm disclosed by Fukaya et al. 20150010853 as being useful chamfer sizes known in the art and chamfered substrates being illustrated in Hamamoto et al. 20150301441 and increasing the spacing of the deposition mask from the surface to increase the width and area of the deposited film as taught by Shoki et al. 20150079501 at [0071] and Nozawa et al. 20020110741 to be within 0.2 to 0.5 mm (the edge of the chamfer transition) of the side of the substrate with a reasonable expectation of forming a useful mask based upon the illustration of the coating of the conductive layer extending to the transition to the chamfered surface in figures 11 and 12 Hamamoto et al. 20150301441 and the disclosure in Inazuki et al. 20160266485 of keeping the deposited materials on the front surface of the mask and not allowing it to be formed on the sides or in the chamfer region at [0048] and to pattern the resulting mask blank using the process described at [0031] of Inazuki et al. 20160266485 with a pattern appropriate to form semiconductor integrated circuits and to use the patterned mask in the formation of integrated circuits as disclosed at [0002] of Inazuki et al. 20160266485 with a reasonable expectation of forming useful semiconductor integrated circuits based upon the disclosure.
Claims 1-4,6-13,15-16, and 18-23 are rejected under 35 U.S.C. 103 as obvious over Inazuki et al. 20160266485, in view of Hamamoto et al. 20150301441, Shoki et al. 20150079501, Fukaya et al. 20150010853 and Nozawa et al. 20020110741, further in view of Nozawa et al. 20180299767.
In addition to the basis above, the examiner holds that it would have been obvious to modify the mask blanks, patterned photomask and processes of their use rendered obvious by the combination of Inazuki et al. 20160266485, Hamamoto et al. 20150301441, Shoki et al. 20150079501, Fukaya et al. 20150010853 and Nozawa et al. 20020110741 as discussed above by replacing the CrON light shielding layer with a 36 nm CrOC light shielding layer based upon the teachings of the prior use of CrON light shielding layers at [0057] and 15-60 nm CrOC layers as being preferable to these at [0079].
Claims 1-4,6-13,15-16, and 18-23 are rejected under 35 U.S.C. 103 as obvious over Shishido et al. WO 2022-014248, in view of Umeo et al. 20160266482, Hamamoto et al. 20150301441, Shoki et al. 20150079501, Fukaya et al. 20150010853
Shishido et al. WO 2022014248 (machine translation attached) a substrate which is 152 mm square in example 1, and coated with a 69nm MoSiON phase shift layer using a deposition mask which had a 146 mm square opening. The phase shift layer was then heat treated at 450 degrees C for 1 hour. This was then coated with a 36nm CrOC light shielding film using a deposition mask with 150 nm square opening to form a layer which was 151.2mm (square). This was then heat treated and coated with a 12 nm SiO2 first hard mask using146 nm square mask and a 3 nm CrOCN second hard mask using a 148 nm square mask. This was then patterned using a Cl2/O2 etch for the second mask, a CF4 etch for the first hard mask, a Cl2/O2 etch for the light shielding layer and a SF6 etch for the phase shift layer. The transfer of the pattern into a resist was simulated and verified.
Umeo et al. 20160266482 disclosed that the outer peripheral part of the surface of a glass substrate for mask blanks, surfaces to be chamfered are provided for the reason of preventing cracking or chipping [0010].
With respect to claims 1-4,6-7,12,13,,15-16, and 20-23, it would have been obvious to one skilled in the art to modify the process of example 1 of Shishido et al. WO 2022-014248 by using a substrate with a chamfer of using a chamfer of 0.2 to 0.5 mm disclosed by Fukaya et al. 20150010853 as being useful chamfer sizes known in the art and chamfered substrates being illustrated in Hamamoto et al. 20150301441 and increasing the spacing of the deposition mask from the surface to increase the width and area of the deposited film as taught by Shoki et al. 20150079501 at [0071] and Nozawa et al. 20020110741 to be within 0.2 to 0.5 mm (the edge of the chamfer transition) of the side of the substrate with a reasonable expectation of forming a useful mask based upon the illustration of the coating of the conductive layer extending to the transition to the chamfered surface in figures 11 and 12 Hamamoto et al. 20150301441 and the disclosure in figure 2 of Shishido et al. WO 2022-014248 of keeping the deposited materials on the front surface of the mask and not allowing it to be formed on the sides or in the chamfer region as supported by the illustration.
With respect to claims 1-4,6-9,12,13,15-18, and 20, it would have been obvious to one skilled in the art to modify the process of example 3 of Inazuki et al. 20160266485 by using a substrate with a chamfer of using a chamfer of 0.2 to 0.5 mm disclosed by Fukaya et al. 20150010853 as being useful chamfer sizes known in the art and chamfered substrates being illustrated in Hamamoto et al. 20150301441 and increasing the spacing of the deposition mask from the surface to increase the width and area of the deposited film as taught by Shoki et al. 20150079501 at [0071] and Nozawa et al. 20020110741 to be within 0.2 to 0.5 mm (the edge of the chamfer transition) of the side of the substrate with a reasonable expectation of forming a useful mask based upon the illustration of the coating of the conductive layer extending to the transition to the chamfered surface in figures 11 and 12 Hamamoto et al. 20150301441 and the disclosure in figure 2 of Shishido et al. WO 2022-014248 of keeping the deposited materials on the front surface of the mask and not allowing it to be formed on the sides or in the chamfer region as supported by the illustration and to pattern the resulting mask blank using the process described in example 1 with a reasonable expectation of forming a useful patterned photomask.
With respect to claims 1-4,6-13, and 15-20, it would have been obvious to one skilled in the art to modify the process of example 3 of Inazuki et al. 20160266485 by using a substrate with a chamfer of using a chamfer of 0.2 to 0.5 mm disclosed by Fukaya et al. 20150010853 as being useful chamfer sizes known in the art and chamfered substrates being illustrated in Hamamoto et al. 20150301441 and increasing the spacing of the deposition mask from the surface to increase the width and area of the deposited film as taught by Shoki et al. 20150079501 at [0071] and Nozawa et al. 20020110741 to be within 0.2 to 0.5 mm (the edge of the chamfer transition) of the side of the substrate with a reasonable expectation of forming a useful mask based upon the illustration of the coating of the conductive layer extending to the transition to the chamfered surface in figures 11 and 12 Hamamoto et al. 20150301441 and the disclosure in figure 2 of Shishido et al. WO 2022-014248 of keeping the deposited materials on the front surface of the mask and not allowing it to be formed on the sides or in the chamfer region as supported by the illustration and to pattern the resulting mask blank using the process in example 1 with a pattern appropriate to form semiconductor integrated circuits and to use the patterned mask in the formation of integrated circuits as discussed in example 1 with a reasonable expectation of forming useful semiconductor integrated circuits based upon the disclosure.
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
JP 60-39047U (machine translation enclosed) describes a photomask where the light shielding film (2) in not applied along the edges, which reduces the exfoliation of the light shielding film. The light shielding film can be chromium metal, chromium oxide, silicon oxide, silicon-germanium, germanium dioxide or iron oxide and can be a monolayer or a double layer. The width of the (peripheral) area where the light shielding film is not formed is less than 1 cm and can be 1-3 mm (paragraphs bridging pages 2 and 3, spot oral translation).
Shishido et al. 12468217 is related to Shishido et al. WO 2022-014248 but does not claim the limited area coating of the layers.
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MARTIN J. ANGEBRANNDT
Primary Examiner
Art Unit 1737
/MARTIN J ANGEBRANNDT/Primary Examiner, Art Unit 1737 November 17, 2025