DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Terminal Disclaimer
The Terminal Disclaimer filed 9/25/2025 was disapproved for the following reasons:
1.) The applicant’s name is not the same as it is on the ADS. No additional fee is required with the resubmission.
The terminal disclaimer identifies a party who is not the applicant (only for applications filed on or after September 16, 2012; See FP 14.26.10):
For cases filed on/after 9/16/12, 37 CFR 1.321 specifies that the applicant can disclaim, and the terminal disclaimer must specify the extent of the applicant's ownership.
A request under 37 CFR 1.46(c) to change the applicant needs to be filed, which is (1) a request, signed by a 1.33(b) party, (2) a corrected ADS (37 CFR 1.76(c)) that identifies the "new" applicant in the applicant information, and is underlined since it is new, and (3) a 3.73(c) statement showing chain of title to the new applicant. Along with the § 1.46(c) request we need a POA that gives power to the attorney who is signing the TD, along with another copy of the TD, unless they file a TD that is signed by the applicant.
2.) The incorrect TD form was submitted. Please resubmit on PTO/AIA /25 (04-13) for pending reference and PTO/AIA /26 (04-14) for prior patent.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 1-11 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1 and 5 of U.S. Patent No. 12,136,661. Although the conflicting claims are not identical, they are not patentably distinct from each other because the currently recited broader claims are fully covered by the already patent claims.
US Patent No. 12,136,661
Current Application
1. A compact CMOS structure comprising a region of material in a semiconductor substrate which forms rectifying junctions with both field induced N and P-type semiconductor, said compact CMOS structure further comprising at least two channels projecting from electrical contact with said region of material in a semiconductor substrate which forms rectifying junctions with both field induced N and P-type semiconductor, said channels being substantially parallel and adjacent to one another; said compact CMOS structure further comprising a gate structure offset with respect to said channels by insulating material; said compact CMOS structure further comprising substantially non-rectifying junctions to said region of material which forms rectifying junctions with both field induced N and P-type semiconductor, and to distal ends of said at least two channels; said substrate, at least in the regions of said channels being characterized by a selection from the group consisting of: it is substantially or per se. intrinsic; it is substantially or per se. compensated; it contains both N and P-type dopants in unequal concentrations;
such that in use a voltage is applied between the substantially non-rectifying junctions at the distal ends of said at least two channels and a voltage is applied to said gate which, when switched between the voltages applied to the substantially non-rectifying distal ends of said at least two channels, causes a voltage to appear at the substantially non-rectifying junction to said region of material which forms rectifying junctions with both field induced N and P-type semiconductor which is inverted, in that when the higher of said voltages applied to the substantially non-rectifying junctions to said distal ends of said at least two channels is applied to said gate, the voltage at the substantially non-rectifying junction to said region of material which forms rectifying junctions with both field induced N and P-type semiconductor is low, and vice-versa.
1. A CMOS structure comprising a region of material in a wide bandgap substrate which forms rectifying junctions with both field induced N and P-type regions therein, said CMOS structure further comprising at least two channels projecting from electrical contact with said region of material in a said wide bandgap substrate which forms rectifying junctions with both field induced N and P-type regions therein;
said CMOS structure further comprising gate structures offset with respect to. said channels by insulating material; said CMOS structure further comprising substantially non- rectifying junctions to said material which forms rectifying junctions with both field induced N and P-type wide bandgap semiconductor, at distal ends of said at least two channels; said wide bandgap semiconductor substrate,
at least in the regions of said channels being characterized by a selection from the group consisting of: it is substantially or per se. intrinsic; it is substantially or per se. metallurigically compensated; it contains both metallurgical N and P-type dopants in unequal concentrations; it is metallurgically doped to provide at least one area of P-type material and at least one separate area of N-type material in each channel region; such that in use a voltage is applied between the substantially non-rectifying junctions at the distal ends of said at least two channels and a voltage is applied to said gate which, when switched between the .voltages applied to the substantially non- rectifying distal ends of said at least two channels, causes a voltage to appear at the substantially non-rectifying junction to said region of material which forms rectifying junctions with both field induced N and P-type wide bandgap semiconductor which is inverted, in that when the higher of said voltages applied to the substantially non-rectifying junctions to said distal ends of said at least two channels is applied to said gate, the voltage at the substantially non-rectifying junction to said region of material which forms rectifying junctions with both field induced N and P-type silicon carbide is low, and vice- versa.
1. A compact CMOS structure comprising a region of material in a semiconductor substrate which forms rectifying junctions with both field induced N and P-type semiconductor, said compact CMOS structure further comprising at least two channels projecting from electrical contact with said region of material in a semiconductor substrate which forms rectifying junctions with both field induced N and P-type semiconductor, said channels being substantially parallel and adjacent to one another; said compact CMOS structure further comprising a gate structure offset with respect to said channels by insulating material; said compact CMOS structure further comprising substantially non-rectifying junctions to said region of material which forms rectifying junctions with both field induced N and P-type semiconductor, and to distal ends of said at least two channels; said substrate, at least in the regions of said channels being characterized by a selection from the group consisting of: it is substantially or per se. intrinsic; it is substantially or per se. compensated; it contains both N and P-type dopants in unequal concentrations;
such that in use a voltage is applied between the substantially non-rectifying junctions at the distal ends of said at least two channels and a voltage is applied to said gate which, when switched between the voltages applied to the substantially non-rectifying distal ends of said at least two channels, causes a voltage to appear at the substantially non-rectifying junction to said region of material which forms rectifying junctions with both field induced N and P-type semiconductor which is inverted, in that when the higher of said voltages applied to the substantially non-rectifying junctions to said distal ends of said at least two channels is applied to said gate, the voltage at the substantially non-rectifying junction to said region of material which forms rectifying junctions with both field induced N and P-type semiconductor is low, and vice-versa.
3. A CMOS structure comprising a region of material in a silicon carbide substrate which forms rectifying junctions with both field induced N and P-type silicon carbide, said CMOS structure further comprising at least two channels projecting from electrical contact with said region of material in a silicon carbide substrate which forms rectifying junctions with both field induced N and P-type silicon carbide; said CMOS structure further comprising gate structures offset with respect to said channels by insulating material; said CMOS structure further comprising substantially non- rectifying junctions to said material which forms rectifying junctions with both field induced N and P-type silicon carbide, and to distal ends of said at least two channels; said silicon carbide substrate, at least in the regions of said channels being characterized by a selection from the group consisting of: it is substantially or per se. intrinsic; it is substantially or per se. metallurigically compensated; it contains both metallurgical N and P-type dopants in unequal concentrations; it is metallurgically doped to provide at least one area of P-type material and at least one separate area of N-type material in each channel region; such that in use a voltage is applied between the substantially non-rectifying junctions at the distal ends of said at least two channels and a voltage is applied to said gate which, when switched between the voltages applied to the substantially non- rectifying distal ends of said at least two channels, causes a voltage to appear at the substantially non-rectifying junction to said region of material which forms rectifying junctions with both field induced N and P-type silicon carbide which is inverted, in that when the higher of said voltages applied to the substantially non-rectifying junctions to said distal ends of said at least two channels is applied to said gate, the voltage at the substantially non-rectifying junction to said region of material which forms rectifying junctions with both field induced N and P-type silicon carbide is low, and vice- versa.
5. A compact FINFET CMOS structure comprising a region of material in a semiconductor substrate which forms rectifying junctions with both field induced N and P-type semiconductor, said compact CMOS structure further comprising at least two FIN channels projecting from electrical contact with said region of material in a semiconductor substrate which forms rectifying junctions with both field induced N and P-type semiconductor, said FIN channels being substantially parallel and adjacent to one another; said compact FINFET CMOS structure further comprising a gate structure offset with respect to said FIN channels by insulating material; said compact FINFET CMOS structure further comprising substantially non-rectifying junctions to said region of material which forms rectifying junctions with both field induced N and P-type semiconductor, and to distal ends of said at least two FIN channels; said substrate, at least in the regions of said FINFETs being characterized by a selection from the group consisting of: it is substantially or per se. intrinsic; it is substantially or per se. compensated; it contains both N and P-type dopants in unequal concentrations; such that in use a voltage is applied between the substantially non-rectifying junctions at the distal ends of said at least two FIN channels and a voltage is applied to said gate which, when switched between the voltages applied to the substantially non-rectifying distal ends of said at least two FIN channels, causes a voltage to appear at the substantially non-rectifying junction to said region of material which forms rectifying junctions with both field induced N and P-type semiconductor which is inverted, in that when the higher of said voltages applied to the substantially non-rectifying junctions to said distal ends of said at least two FIN channels is applied to said gate, the voltage at the substantially non-rectifying junction to said region of material which forms rectifying junctions with both field induced N and P-type semiconductor is low, and vice-versa.
6. A compact CMOS structure comprising a region of material in a silicon carbide substrate which forms rectifying junctions with both field induced N and P-type silicon carbide, said compact CMOS structure further comprising at least two channels projecting from electrical contact with said region of material in a silicon carbide substrate which forms rectifying junctions with both field induced N and P-type silicon carbide, said channels being substantially parallel and adjacent to one another; said compact CMOS structure further comprising a gate structure offset with respect to said channels by insulating material; said compact CMOS structure further comprising substantially non-rectifying junctions to said material which forms rectifying junctions with both field induced N and P-type silicon carbide, and to distal ends of said at least two channels; said silicon carbide substrate, at least in the regions of said channels being characterized by a selection from the group consisting of: it is substantially or per se. intrinsic; it is substantially or per se. metallurigically compensated; it contains both metallurgical N and P-type dopants in unequal concentrations; it is metallurgically doped to provide at least one area of P-type material and at least one separate area of N-type material in each channel region; such that in use a voltage is applied between the substantially non-rectifying junctions at the distal ends of said at least two channels and a voltage is applied to said gate which, when switched between the voltages applied to the substantially non- rectifying distal ends of said at least two channels, causes a voltage to appear at the substantially non-rectifying junction to said region of material which forms rectifying junctions with both field induced N and P-type silicon carbide which is inverted, in that when the higher of said voltages applied to the substantially non-rectifying junctions to said distal ends of said at least two channels is applied to said gate, the voltage at the substantially non-rectifying junction to said region of material which forms rectifying junctions with both field induced N and P-type silicon carbide is low, and vice- versa.
9. A CMOS structure as in Claim 1, in which said channels are present in FINS which project from a surface of said wide bandgap semiconductor substrate.
10. A CMOS structure as in Claim 3, in which said channels are present in FINS which project from a surface of said wide bandgap semiconductor substrate.
11. A compact CMOS structure as in Claim 6, in which said channels are present in FINS which project from a surface of said wide bandgap semiconductor substrate.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/CHRISTINE A ENAD/Primary Examiner, Art Unit 2811