DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claims 1, 8-10 are objected to because of the following informalities:
Regarding claim 1, the limitation “cinfuguring” in line 8 is misspelled. Appropriate correction is required.
Regarding claims 8-10, the limitations “A compact CMOS structure as in Claim 7” in claim 8 and “A compact CMOS structure as in Claim 6” are not appropriate since claim 6 and 7 are method claims.
Double Patenting
A rejection based on double patenting of the “same invention” type finds its support in the language of 35 U.S.C. 101 which states that “whoever invents or discovers any new and useful process... may obtain a patent therefor...” (Emphasis added). Thus, the term “same invention,” in this context, means an invention drawn to identical subject matter. See Miller v. Eagle Mfg. Co., 151 U.S. 186 (1894); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Ockert, 245 F.2d 467, 114 USPQ 330 (CCPA 1957).
A statutory type (35 U.S.C. 101) double patenting rejection can be overcome by canceling or amending the claims that are directed to the same invention so they are no longer coextensive in scope. The filing of a terminal disclaimer cannot overcome a double patenting rejection based upon 35 U.S.C. 101.
Claim 1 is rejected under 35 U.S.C. 101 as claiming the same invention as that of claim 6 of prior U.S. Patent No. 11,798,946. This is a statutory double patenting rejection.
Current Application
US Patent No. 11,798,946
1. A compact CMOS structure formed in a semiconductor substrate by a method comprising: a) selecting a semiconductor substrate, identifying insulating material, and identifying material that forms rectifying junctions with both N and P-type field induced doping in said selected semiconductor substrate when present in said semiconductor substrate; b) cinfuguring said semiconductor substrate, said insulating material and said material that forms rectifying junctions with both N and P-type field induced doping when said material is present in said semiconductor substrate, to comprise said compact CMOS structure; said compact CMOS structure being characterized by two channels projecting from electrical contact with said region of material that forms rectifying junctions with both N and P-type field induced doping in said semiconductor substrate, wherein said channels are substantially parallel and adjacent to one another; said compact CMOS structure further comprising a gate structure offset with respect to said channels by said insulating material; and said compact CMOS structure further comprising substantially non-rectifying junctions to said material which forms rectifying junctions with both field induced N and P-type semiconductor, and to distal ends of said two channels; such that in use a voltage is applied between the substantially non-rectifying junctions at- the distal ends of said two channels and a voltage is applied to said gate which, when switched between the voltages applied to the substantially non-rectifying distal ends of said two channels, causes a voltage to appear at the substantially non-rectifying junction to said region of material which forms rectifying junctions with both field induced N and P-type semiconductor which is inverted, in that when the higher of said voltages applied to the substantially non-rectifying junctions to said distal ends of said two channels is applied to said gate, the voltage at the substantially non-rectifying junction to said region of material which forms rectifying junctions with both field induced N and P-type semiconductor is low, and vice-versa.
6. A compact CMOS structure formed in a semiconductor substrate by:
a) selecting a semiconductor substrate, identifying insulating material, and identifying material that forms rectifying junctions with both N and P-type field induced doping in said semiconductor substrate when present in said semiconductor substrate; b) fashioning said semiconductor substrate, said insulating material and said material that forms rectifying junctions with both N and P-type field induced doping when said material is present in said semiconductor substrate, to comprise said compact CMOS structure; said compact CMOS structure being characterized by further comprising two channels projecting from electrical contact with said region of material that forms rectifying junctions with both N and P-type field induced doping in said semiconductor substrate, wherein said channels are substantially parallel and adjacent to one another; said compact CMOS structure further comprising a gate structure offset with respect to said channels by said insulating material; and said compact CMOS structure further comprising substantially non-rectifying junctions to said material which forms rectifying junctions with both field induced N and P-type semiconductor, and to distal ends of said two channels; such that in use a voltage is applied between the substantially non-rectifying junctions at the distal ends of said two channels and a voltage is applied to said gate which, when switched between the voltages applied to the substantially non-rectifying distal ends of said two channels, causes a voltage to appear at the substantially non-rectifying junction to said region of material which forms rectifying junctions with both field induced N and P-type semiconductor which is inverted, in that when the higher of said voltages applied to the substantially non-rectifying junctions to said distal ends of said two channels is applied to said gate, the voltage at the substantially non-rectifying junction to said region of material which forms rectifying junctions with both field induced N and P-type semiconductor is low, and vice-versa.
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 5 of U.S. Patent No. 12,136,661 and claims 1, 4-6 of US Patent No. 11,798,946. Although the claims at issue are not identical, they are not patentably distinct from each other because the currently recited broader claims are fully covered by the already patent claims.
Current Application
US Patent No. 12,136,661
US Patent No. 11,798,946
1. A compact CMOS structure formed in a semiconductor substrate by a method comprising: a) selecting a semiconductor substrate, identifying insulating material, and identifying material that forms rectifying junctions with both N and P-type field induced doping in said selected semiconductor substrate when present in saie semiconductor substrate; b) cinfuguring said semiconductor substrate, said insulating material and said material that forms rectifying junctions with both N and P-type field induced doping when said material is present in said semiconductor substrate, to comprise said compact CMOS structure; said compact CMOS structure being characterized by two channels projecting from electrical contact with said region of material that forms rectifying junctions with both N and P-type field induced doping in said semiconductor substrate, wherein said channels are substantially parallel and adjacent to one another; said compact CMOS structure further comprising a gate structure offset with respect to said channels by said insulating material; and said compact CMOS structure further comprising substantially non-rectifying junctions to said material which forms rectifying junctions with both field induced N and P-type semiconductor, and to distal ends of said two channels; such that in use a voltage is applied between the substantially non-rectifying junctions at- the distal ends of said two channels and a voltage is applied to said gate which, when switched between the voltages applied to the substantially non-rectifying distal ends of said two channels, causes a voltage to appear at the substantially non-rectifying junction to said region of material which forms rectifying junctions with both field induced N and P-type semiconductor which is inverted, in that when the higher of said voltages applied to the substantially non-rectifying junctions to said distal ends of said two channels is applied to said gate, the voltage at the substantially non-rectifying junction to said region of material which forms rectifying junctions with both field induced N and P-type semiconductor is low, and vice-versa.
1. A compact CMOS structure comprising a region of material in a semiconductor substrate which forms rectifying junctions with both field induced N and P-type semiconductor, said compact CMOS structure further comprising at least two channels projecting from electrical contact with said region of material in a semiconductor substrate which forms rectifying junctions with both field induced N and P-type semiconductor, said channels being substantially parallel and adjacent to one another; said compact CMOS structure further comprising a gate structure offset with respect to said channels by insulating material; said compact CMOS structure further comprising substantially non-rectifying junctions to said region of material which forms rectifying junctions with both field induced N and P-type semiconductor, and to distal ends of said at least two channels; said substrate, at least in the regions of said channels being characterized by a selection from the group consisting of: it is substantially or per se. intrinsic; it is substantially or per se. compensated; it contains both N and P-type dopants in unequal concentrations; such that in use a voltage is applied between the substantially non-rectifying junctions at the distal ends of said at least two channels and a voltage is applied to said gate which, when switched between the voltages applied to the substantially non-rectifying distal ends of said at least two channels, causes a voltage to appear at the substantially non-rectifying junction to said region of material which forms rectifying junctions with both field induced N and P-type semiconductor which is inverted, in that when the higher of said voltages applied to the substantially non-rectifying junctions to said distal ends of said at least two channels is applied to said gate, the voltage at the substantially non-rectifying junction to said region of material which forms rectifying junctions with both field induced N and P-type semiconductor is low, and vice-versa.
6. A compact CMOS structure formed in a semiconductor substrate by: a) selecting a semiconductor substrate, identifying insulating material, and identifying material that forms rectifying junctions with both N and P-type field induced doping in said semiconductor substrate when present in said semiconductor substrate; b) fashioning said semiconductor substrate, said insulating material and said material that forms rectifying junctions with both N and P-type field induced doping when said material is present in said semiconductor substrate, to comprise said compact CMOS structure; said compact CMOS structure being characterized by further comprising two channels projecting from electrical contact with said region of material that forms rectifying junctions with both N and P-type field induced doping in said semiconductor substrate, wherein said channels are substantially parallel and adjacent to one another; said compact CMOS structure further comprising a gate structure offset with respect to said channels by said insulating material; and said compact CMOS structure further comprising substantially non-rectifying junctions to said material which forms rectifying junctions with both field induced N and P-type semiconductor, and to distal ends of said two channels; such that in use a voltage is applied between the substantially non-rectifying junctions at the distal ends of said two channels and a voltage is applied to said gate which, when switched between the voltages applied to the substantially non-rectifying distal ends of said two channels, causes a voltage to appear at the substantially non-rectifying junction to said region of material which forms rectifying junctions with both field induced N and P-type semiconductor which is inverted, in that when the higher of said voltages applied to the substantially non-rectifying junctions to said distal ends of said two channels is applied to said gate, the voltage at the substantially non-rectifying junction to said region of material which forms rectifying junctions with both field induced N and P-type semiconductor is low, and vice-versa.
4. A compact CMOS structure as in Claim 1, in which the semiconductor substrate, at least in the regions of said channels, is characterized by.a selection from the group consisting of: it is substantially or per se. intrinsic; it is substantially or per se. metallurgically compensated; it contains both metallurgical N and P-type dopants in unequal concentrations; it is metallurgically doped to provide at least one area of P-type material and at least one separate area of N-type material in each channel region.
(Part of Claim 1)
5. A compact CMOS structure as in Claim 1, in which said channels are present in FINS which project from surface of said semiconductor substrate. (with independent claim 1)
5.A compact FINFET CMOS structure comprising a region of material in a semiconductor substrate which forms rectifying junctions with both field induced N and P-type semiconductor, said compact CMOS structure further comprising at least two FIN channels projecting from electrical contact with said region of material in a semiconductor substrate which forms rectifying junctions with both field induced N and P-type semiconductor, said FIN channels being substantially parallel and adjacent to one another; said compact FINFET CMOS structure further comprising a gate structure offset with respect to said FIN channels by insulating material; said compact FINFET CMOS structure further comprising substantially non-rectifying junctions to said region of material which forms rectifying junctions with both field induced N and P-type semiconductor, and to distal ends of said at least two FIN channels; said substrate, at least in the regions of said FINFETs being characterized by a selection from the group consisting of: it is substantially or per se. intrinsic; it is substantially or per se. compensated; it contains both N and P-type dopants in unequal concentrations; such that in use a voltage is applied between the substantially non-rectifying junctions at the distal ends of said at least two FIN channels and a voltage is applied to said gate which, when switched between the voltages applied to the substantially non-rectifying distal ends of said at least two FIN channels, causes a voltage to appear at the substantially non-rectifying junction to said region of material which forms rectifying junctions with both field induced N and P-type semiconductor which is inverted, in that when the higher of said voltages applied to the substantially non-rectifying junctions to said distal ends of said at least two FIN channels is applied to said gate, the voltage at the substantially non-rectifying junction to said region of material which forms rectifying junctions with both field induced N and P-type semiconductor is low, and vice-versa.
6. A method of fabricating a compact CMOS structure formed in a semiconductor substrate comprising: a) selecting a semiconductor substrate, identifying insulating material, and identifying material that forms rectifying junctions with both N and P-type field induced doping in said selected semiconductor substrate when present in said semiconductor substrate; b) configuring said semiconductor substrate, said insulating material and said material that forms rectifying junctions with both N and P-type field induced doping when said material is present in said semiconductor substrate, to comprise said compact CMOS structure; said compact CMOS structure being characterized by two channels projecting from electrical contact with said region of material that forms rectifying junctions with both N and P-type field induced doping in said semiconductor substrate, wherein said channels are substantially parallel and adjacent to one another; said compact CMOS structure further comprising a gate structure offset with respect to said channels by said insulating material; and said compact CMOS structure further comprising substantially non-rectifying junctions to said material which forms rectifying junctions with both field induced N and P-type semiconductor, and to distal ends of said two channels;such that in use a voltage is applied between the substantially non-rectifying junctions at the distal ends of said two channels and a voltage is applied to said gate which, when switched between the voltages applied to the substantially non-rectifying distal ends of said two channels, causes a voltage to appear at the substantially non-rectifying junction to said region of material which forms rectifying junctions with both field induced N and P-type semiconductor which is inverted, in that when the higher of said voltages applied to the substantially non-rectifying junctions to said distal ends of said two channels is applied to said gate, the voltage at the substantially non-rectifying junction to said region of material which forms rectifying junctions with both field induced N and P-type semiconductor is low, and vice-versa.
1. A compact CMOS structure comprising a region of material in a semiconductor substrate which forms rectifying junctions with both field induced N and P-type semiconductor, said compact CMOS structure further comprising at least two channels projecting from electrical contact with said region of material in a semiconductor substrate which forms rectifying junctions with both field induced N and P-type semiconductor, said channels being substantially parallel and adjacent to one another; said compact CMOS structure further comprising a gate structure offset with respect to said channels by insulating material; said compact CMOS structure further comprising substantially non-rectifying junctions to said region of material which forms rectifying junctions with both field induced N and P-type semiconductor, and to distal ends of said at least two channels; said substrate, at least in the regions of said channels being characterized by a selection from the group consisting of: it is substantially or per se. intrinsic; it is substantially or per se. compensated; it contains both N and P-type dopants in unequal concentrations; such that in use a voltage is applied between the substantially non-rectifying junctions at the distal ends of said at least two channels and a voltage is applied to said gate which, when switched between the voltages applied to the substantially non-rectifying distal ends of said at least two channels, causes a voltage to appear at the substantially non-rectifying junction to said region of material which forms rectifying junctions with both field induced N and P-type semiconductor which is inverted, in that when the higher of said voltages applied to the substantially non-rectifying junctions to said distal ends of said at least two channels is applied to said gate, the voltage at the substantially non-rectifying junction to said region of material which forms rectifying junctions with both field induced N and P-type semiconductor is low, and vice-versa.
6. A compact CMOS structure formed in a semiconductor substrate by: a) selecting a semiconductor substrate, identifying insulating material, and identifying material that forms rectifying junctions with both N and P-type field induced doping in said semiconductor substrate when present in said semiconductor substrate; b) fashioning said semiconductor substrate, said insulating material and said material that forms rectifying junctions with both N and P-type field induced doping when said material is present in said semiconductor substrate, to comprise said compact CMOS structure; said compact CMOS structure being characterized by further comprising two channels projecting from electrical contact with said region of material that forms rectifying junctions with both N and P-type field induced doping in said semiconductor substrate, wherein said channels are substantially parallel and adjacent to one another; said compact CMOS structure further comprising a gate structure offset with respect to said channels by said insulating material; and said compact CMOS structure further comprising substantially non-rectifying junctions to said material which forms rectifying junctions with both field induced N and P-type semiconductor, and to distal ends of said two channels; such that in use a voltage is applied between the substantially non-rectifying junctions at the distal ends of said two channels and a voltage is applied to said gate which, when switched between the voltages applied to the substantially non-rectifying distal ends of said two channels, causes a voltage to appear at the substantially non-rectifying junction to said region of material which forms rectifying junctions with both field induced N and P-type semiconductor which is inverted, in that when the higher of said voltages applied to the substantially non-rectifying junctions to said distal ends of said two channels is applied to said gate, the voltage at the substantially non-rectifying junction to said region of material which forms rectifying junctions with both field induced N and P-type semiconductor is low, and vice-versa.
11. A compact CMOS structure formed in a semiconductor substrate by a method comprising: a) selecting a semiconductor substrate, identifying insulating material, and identifying material that forms rectifying junctions with both N and P-type field induced doping in said selected semiconductor substrate when present in said semiconductor substrate; b) configuring said semiconductor substrate, said insulating material and said material that forms rectifying junctions with both N and P-type field induced doping when said material is present in said semiconductor substrate, to comprise said compact CMOS structure; said compact CMOS structure being characterized by two channels projecting from electrical contact with said region of material that forms rectifying junctions with both N and P-type field induced doping in said semiconductor substrate, said compact CMOS structure further comprising a gate structure offset with respect to said channels by said insulating material; and said compact CMOS structure further comprising substantially non-rectifying junctions to said material which forms rectifying junctions with both field induced N and P-type semiconductor, and to distal ends of said two channels; such that in use a voltage is applied between the substantially non-rectifying junctions at the distal ends of said two channels and a voltage is applied to said gate which, when switched between the voltages applied to the substantially non-rectifying distal ends of said two channels, causes a voltage to appear at the substantially non-rectifying junction to said region of material which forms rectifying junctions with both field induced N and P-type semiconductor which is inverted, in that when the higher of said voltages applied to the substantially non-rectifying junctions to said distal ends of said two channels is applied to said gate, the voltage at the substantially non-rectifying junction to said region of material which forms rectifying junctions with both field induced N and P-type semiconductor is low, and vice-versa.
1. A compact CMOS structure comprising a region of material in a semiconductor substrate which forms rectifying junctions with both field induced N and P-type semiconductor, said compact CMOS structure further comprising at least two channels projecting from electrical contact with said region of material in a semiconductor substrate which forms rectifying junctions with both field induced N and P-type semiconductor, said channels being substantially parallel and adjacent to one another; said compact CMOS structure further comprising a gate structure offset with respect to said channels by insulating material; said compact CMOS structure further comprising substantially non-rectifying junctions to said region of material which forms rectifying junctions with both field induced N and P-type semiconductor, and to distal ends of said at least two channels; said substrate, at least in the regions of said channels being characterized by a selection from the group consisting of: it is substantially or per se. intrinsic; it is substantially or per se. compensated; it contains both N and P-type dopants in unequal concentrations; such that in use a voltage is applied between the substantially non-rectifying junctions at the distal ends of said at least two channels and a voltage is applied to said gate which, when switched between the voltages applied to the substantially non-rectifying distal ends of said at least two channels, causes a voltage to appear at the substantially non-rectifying junction to said region of material which forms rectifying junctions with both field induced N and P-type semiconductor which is inverted, in that when the higher of said voltages applied to the substantially non-rectifying junctions to said distal ends of said at least two channels is applied to said gate, the voltage at the substantially non-rectifying junction to said region of material which forms rectifying junctions with both field induced N and P-type semiconductor is low, and vice-versa.
6. A compact CMOS structure formed in a semiconductor substrate by: a) selecting a semiconductor substrate, identifying insulating material, and identifying material that forms rectifying junctions with both N and P-type field induced doping in said semiconductor substrate when present in said semiconductor substrate; b) fashioning said semiconductor substrate, said insulating material and said material that forms rectifying junctions with both N and P-type field induced doping when said material is present in said semiconductor substrate, to comprise said compact CMOS structure; said compact CMOS structure being characterized by further comprising two channels projecting from electrical contact with said region of material that forms rectifying junctions with both N and P-type field induced doping in said semiconductor substrate, wherein said channels are substantially parallel and adjacent to one another; said compact CMOS structure further comprising a gate structure offset with respect to said channels by said insulating material; and said compact CMOS structure further comprising substantially non-rectifying junctions to said material which forms rectifying junctions with both field induced N and P-type semiconductor, and to distal ends of said two channels; such that in use a voltage is applied between the substantially non-rectifying junctions at the distal ends of said two channels and a voltage is applied to said gate which, when switched between the voltages applied to the substantially non-rectifying distal ends of said two channels, causes a voltage to appear at the substantially non-rectifying junction to said region of material which forms rectifying junctions with both field induced N and P-type semiconductor which is inverted, in that when the higher of said voltages applied to the substantially non-rectifying junctions to said distal ends of said two channels is applied to said gate, the voltage at the substantially non-rectifying junction to said region of material which forms rectifying junctions with both field induced N and P-type semiconductor is low, and vice-versa.
14. A compact CMOS structure as in Claim 11, in which the semiconductor substrate, at least in the regions of said channels, is characterized by a selection from the group consisting of: it is substantially or per se. intrinsic; it is substantially or per se. metallurgically compensated; it contains both metallurgical N and P-type dopants in unequal concentrations; it is metallurgically doped to provide at least one area of P-type material and at least one separate area of N-type material in each channel region.
(Part of Claim 1)
15. A compact CMOS structure as in Claim 12, in which said channels are present in FINS which project from surface of said semiconductor substrate. (with independent claim 1)
5.A compact FINFET CMOS structure comprising a region of material in a semiconductor substrate which forms rectifying junctions with both field induced N and P-type semiconductor, said compact CMOS structure further comprising at least two FIN channels projecting from electrical contact with said region of material in a semiconductor substrate which forms rectifying junctions with both field induced N and P-type semiconductor, said FIN channels being substantially parallel and adjacent to one another; said compact FINFET CMOS structure further comprising a gate structure offset with respect to said FIN channels by insulating material; said compact FINFET CMOS structure further comprising substantially non-rectifying junctions to said region of material which forms rectifying junctions with both field induced N and P-type semiconductor, and to distal ends of said at least two FIN channels; said substrate, at least in the regions of said FINFETs being characterized by a selection from the group consisting of: it is substantially or per se. intrinsic; it is substantially or per se. compensated; it contains both N and P-type dopants in unequal concentrations; such that in use a voltage is applied between the substantially non-rectifying junctions at the distal ends of said at least two FIN channels and a voltage is applied to said gate which, when switched between the voltages applied to the substantially non-rectifying distal ends of said at least two FIN channels, causes a voltage to appear at the substantially non-rectifying junction to said region of material which forms rectifying junctions with both field induced N and P-type semiconductor which is inverted, in that when the higher of said voltages applied to the substantially non-rectifying junctions to said distal ends of said at least two FIN channels is applied to said gate, the voltage at the substantially non-rectifying junction to said region of material which forms rectifying junctions with both field induced N and P-type semiconductor is low, and vice-versa.
Conclusion
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/CHRISTINE A ENAD/Primary Examiner, Art Unit 2811