Prosecution Insights
Last updated: July 17, 2026
Application No. 17/804,928

Dual Side Intelligent Power Device Integration

Non-Final OA §102§103
Filed
Jun 01, 2022
Priority
Apr 26, 2022 — provisional 63/363,590
Examiner
BOATMAN, CASEY PAUL
Art Unit
2893
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Taiwan Semiconductor Manufacturing Company, Ltd.
OA Round
4 (Non-Final)
82%
Grant Probability
Favorable
4-5
OA Rounds
0m
Est. Remaining
94%
With Interview

Examiner Intelligence

Grants 82% — above average
82%
Career Allowance Rate
61 granted / 74 resolved
+14.4% vs TC avg
Moderate +12% lift
Without
With
+11.6%
Interview Lift
resolved cases with interview
Typical timeline
3y 6m
Avg Prosecution
23 currently pending
Career history
96
Total Applications
across all art units

Statute-Specific Performance

§103
79.3%
+39.3% vs TC avg
§102
13.6%
-26.4% vs TC avg
§112
6.8%
-33.2% vs TC avg
Black line = Tech Center average estimate • Based on career data from 74 resolved cases

Office Action

§102 §103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Response to Amendment Amendments to claims 17 and 18 submitted on March 16, 2026 are acknowledged and have since been entered. Claims 1-13, 16, 19, 20 and 25-25 have been canceled. New Claims 36-47 are further acknowledged. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 37- 40, 42, and 43 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Farooq (US 20210175174 A1). Regarding Claim 37, Farooq teaches a method (see Figs. 11-15) comprising: forming a first package component (1502, shown Fig. 15) comprising an interposer (504a-512a, shown Fig. 11), wherein the interposer is electrically connected to a first die (500a) that is encapsulated in an encapsulant (see [0081] which describes the entire structure being encased in an underfill encapsulant), and wherein the interposer comprises a plurality of protruding metal posts (524a); bonding a second die (300a) to a second side of the interposer (shown Fig. 15), wherein the second die comprises: a substrate (302); and a through-via penetrating through the substrate (see [0082] which describes chips 300a being bridge chips, wherein it is understood that at least some metal interconnect extends through the die substrate); and bonding a second package component (1202) underlying the first package component through a plurality of solder regions (1004, shown Fig. 11, see also [0082]), wherein the plurality of solder regions comprise portions lower than a top surface of the second package component (shown Figs. 12-15, wherein the solder regions would be entirely below the surface in which chip 300a is disposed on the second package component). Regarding Claim 38, Farooq teaches the method of claim 37 further comprising: etching the second package component to form a plurality of recesses (1206, see [0084]), wherein the plurality of solder regions extend into the plurality of recesses (see [0082] and Fig. 15). Regarding Claim 39, Farooq teaches the method of claim 37, wherein the plurality of solder regions join the plurality of plurality of protruding metal posts to the second package component (see [0082] and Figs. 11 and 15). Regarding Claim 40, Farooq teaches the method of claim 37 further comprising dispensing an underfill (see [0081] which describes the entire package being encased in an underfill encapsulant) between the interposer and the second package component, wherein the underfill extends into the second package component (as shown in Fig. 15, the underfill would fill any gap between the interposer and the second package component and within recesses 1206). Regarding Claim 42, Farooq teaches the method of claim 37, wherein the second die is a bridge die (see [0082]). Regarding Claim 43, Farooq teaches the method of claim 37, wherein the first package component further comprises a third die (700a, shown Fig. 15) bonding to the interposer, wherein the second die electrically connects the first die to the third die (see [0082]). Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. Claim 41 is rejected under 35 U.S.C. 103 as being unpatentable over Farooq (US 20210175174 A1) in further view of Hsu (US 20190006315 A1) Regarding Claim 41, Farooq teaches the method of claim 37, wherein the second die is a bridge die, but does not explicitly teach that the bridge die may contain active components of an exemplary intelligent power device die. Hsu teaches a method of forming a package structure (see Fig. 4) comprising a first and second die (200a and 200b) bridged by an intelligent power device die (130, see also [0034] which describes die 130 comprising active components). It would be obvious to one of ordinary skill in the art prior to the effective filing date of the instant application to implement active components in the bridge die of Farooq as this would increase integration versatility within IC packaging. Specifically, this modification would teach that the second die of Farooq is an intelligent power device die. Allowable Subject Matter Claims 14-15, 17, 18, 21-24, 36, and 44-47 are allowed. The following is a statement of reasons for the indication of allowable subject matter: Regarding Claim 14, Wu (US 20210098421 A1) being the most relevant prior art of record teaches: A package (shown Fig. 7) comprising: an interposer (350 and metal pillars 120, as defined in the instant application), wherein the interposer comprises a plurality of protruding metal posts (120); a first device die (200A) over and bonding to the interposer; a die (530) underlying and bonding to the interposer, wherein the die comprises: a semiconductor substrate (532, see [0075] and Fig. 6A); and through-vias (534, see [0077]) penetrating through the semiconductor substrate; a package substrate (110) underlying the die and the interposer (shown Fig. 7); a first plurality of connection regions (112t, see also Fig. 1A, [0025-0026] which describes 112t being distributed on a “die-attaching region”); and a second plurality of connection regions 112t’, see Fig. 6A) bonding the die to the package substrate (shown Fig. 6A), wherein the second plurality of connection regions comprise portions over the top surface of the package substrate, and wherein the through-vias and the second plurality of connection regions electrically connect the interposer to the package substrate (shown Fig. 7). Seo (US 20160133613 A1) further teaches a package-on-package structure analogous to that of Wu wherein a first solder pad 165, interpreted as a first solder region, is disposed in the same manner as component 112t of Wu), bonding the interposer to the package substrate (shown Fig. 7) with a subsequent solder material and wherein the first solder regions are lower than a top surface of the package substrate (shown Fig. 7). Farooq (US 20210175174 A1) teaches a package structure (shown Fig. 15) wherein a plurality of protruding metal posts protrude toward a package substrate and join the package substrate via a plurality of solder regions wherein at least some portion of the solder region is lower than a top surface of the substrate. However, Farooq teaches away from a second plurality of solder regions joining a die, which underlies the interposer, to the package substrate over the top surface of the package substrate. The prior art does not explicitly teach or suggest in any combination the plurality of protruding metal posts protruding toward the package substrate and joining the package substrate via a plurality of solder regions wherein at least some portion of the solder region is lower than a top surface of the package substrate as shown in Fig. 15 of the instant application. Thus, claim 14 is deemed patentable over the prior art. Claims 17, 21-22, 24 and 44-45 are further deemed patentable due to their dependence on claim 14. Regarding Claim 18, Jeng (us 20210193637 A1) being the most relevant prior art of record teaches a package (see Fig. 7) comprising: an interposer (20’); a first device die (50A) and a second device die (50B) over and bonding to the interposer (shown Fig. 7); a die (78) underlying and bonding to the interposer, wherein the die comprises: a component (described [0040]) selected from the group consisting of an intelligent power device, a passive device (see [0034], and combinations thereof, wherein the component comprises: a semiconductor substrate (80); and a through-via (90) penetrating through the semiconductor substrate (shown Fig. 13); and a package component (102) underlying and bonding to both of the die and the interposer (shown Fig. 7), wherein the interposer is electrically connected to the package component through the die (see Fig. 13). Jeng further teaches an underfill (108) between the die and the interposer (shown Fig. 7) and further between the interposer and the package component. Jeng does not explicitly describe the underfill being a first underfill and a second underfill which have a “distinguishable interface therebetween”. Tsai (US 20200105663 A1) teaches an integrated circuit package comprising a die (224, see Fig. 20), a first underfill (230) formed between a package component (208) and the die and around solder regions 228, and a second underfill (232) to encapsulate the die and the first underfill. Farooq (US 20210175174 A1) teaches a package structure (shown Fig. 15) wherein a plurality of protruding metal posts protrude toward a package substrate and join the package substrate via a plurality of solder regions wherein at least some portion of the solder region is lower than a top surface of the substrate. However, Farooq teaches away from a second plurality of solder regions joining a die, which underlies the interposer, to the package substrate over the top surface of the package substrate. The prior art does not explicitly teach or suggest in any combination the plurality of protruding metal posts protruding toward the package substrate and joining the package substrate via a plurality of solder regions wherein at least some portion of the solder region is lower than a top surface of the package substrate and the package component being electrically connected to the interposer through the die as shown in Fig. 15 of the instant application. Thus, claim 18 is deemed patentable over the prior art. Claims 23, 36 and 46-47 are further deemed patentable due to their dependence on claim 18. As allowable subject matter has been indicated, applicant's reply must either comply with all formal requirements or specifically traverse each requirement not complied with. See 37 CFR 1.111(b) and MPEP § 707.07(a). Response to Arguments Applicant’s arguments with respect to newly added claims have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Conclusion THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to CASEY PAUL BOATMAN whose telephone number is (703)756-4778. The examiner can normally be reached M-F 7:30 AM - 5:30 PM ET. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt Hanley can be reached on (571)270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /C.P.B./Examiner, Art Unit 2893 /SUE A PURVIS/Supervisory Patent Examiner, Art Unit 2893
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Prosecution Timeline

Show 7 earlier events
Jul 21, 2025
Request for Continued Examination
Jul 22, 2025
Response after Non-Final Action
Dec 18, 2025
Non-Final Rejection mailed — §102, §103
Mar 16, 2026
Response Filed
Apr 09, 2026
Final Rejection mailed — §102, §103
Jun 02, 2026
Response after Non-Final Action
Jun 23, 2026
Examiner Interview Summary
Jun 23, 2026
Applicant Interview (Telephonic)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

4-5
Expected OA Rounds
82%
Grant Probability
94%
With Interview (+11.6%)
3y 6m (~0m remaining)
Median Time to Grant
High
PTA Risk
Based on 74 resolved cases by this examiner. Grant probability derived from career allowance rate.

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