Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The previous objection to the drawings is withdrawn.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 3-6, 8-10, 12 and 13 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Pinos (US PgPub 20220302344).
With regard to claim 1, Pinos teaches in figures 1-3, a method of fabricating a semiconductor device comprising: providing a substrate (10, 21 and 22), the substrate comprising a base layer 10 and two or more planar heteroepitaxial layers (21 and 22) deposited on the base layer, the two or more heteroepitaxial layers comprising a first epitaxial layer 21 having a first lattice constant and a second epitaxial layer having a second lattice constant different than the first lattice constant (paragraph [0080]); etching the substrate to form one or more mesas (figure 2), each of the one or more mesas having a width from 10 µm to 100 µm (paragraph [0058] teaches surface less than 100 µm x 100 µm); and depositing one or more non-planar overgrowth layers (30, paragraph [0106]) on the etched substrate.
With regard to claim 3, the base layer of Pinos comprises a silicon substrate (paragraph [0075]).
With regard to claim 4, the two or more heteroepitaxial layers comprise III-V materials (paragraph [0077 – 0080]).
With regard to claim 5, the two or more heteroepitaxial layers comprise GaN (paragraph [0077] and [0082]).
With regard to claim 6, Pinos teach providing the base layer and epitaxially growing the two or more planar heteroepitaxial layers on the base layer (figure 1).
With regard to claim 8, Pinos teach the mesa surface being less than approx. 100 µm x 100 µm. Taking this end point, the length to width ratio would be about 1:1 as thus reads on the claimed range of ratios.
With regard to claim 9, depositing the one of more non-planar overgrowth layers decreases a tensile strain on the two of more heteroepitaxial layers (note that the different compositions of III-V materials used for the overgrowth layers and the heteroepitaxial layers and the teachings of strain relaxing are understood that the overgrowth layers on the sidewalls will contribute to some decrease (relaxing) of the tensile strain in the layers).
With regard to claim 10, the one or more non-planar overgrowth layers are epitaxially (MBE, paragraph [9192]).
With regard to claim 12, the non-planar overgrowth layer has the formula AlxGa1-xN (when x=0) or AlxInyGa1-x-yN (when x=0) (paragraph [0103-0104]).
With regard to claim 13, Pinos discloses wherein the one or more non-planar overgrowth layers (50) [0117] (40) [0113] comprise a first overgrowth layer (50) comprising a first alloy (AlGaN) [0117] and a second overgrowth layer (40) comprising a second alloy (InGaN) [0113].
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 7 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Pinos (US PgPub 20220302344) as applied to claim 1 above, in view of Official Notice.
With regard to claim 7, Pinos teach the etching to form mesas comprises: depositing a mask over the substrate, patterning the mask to remove portions of the mask, and etching the non-masked portions of the substrate to form the one or more mesas (paragraph [0090]). While Pinos is silent as to using photolithography, Official Notice it taken that it is well known in the art before the effective filing date of the invention to us photolithography in patterning masks. These techniques are routinely used throughout the semiconductor industry and thus provide the benefit of using well known, understood and readily available techniques.
With regard to claim 11, Pinos teaches the one or more overgrowth layer (30 and 40) are alternating layers (paragraph [0113] – active layer 40 is alternating layers) and that layer 40 may be multiple quantum wells. While not explicitly taught, Official Notice is taken that is well known to incorporate superlattices into LEDs. It is well known that superlattices provide control over the bandgaps and emission wavelength of the LED. Thus it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate superlattices into the LED of Pinos.
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Pinos (US PgPub 20220302344) as applied to claim 1 above, and further in view of Hudait et al. (US Patent 7851780) (hereinafter Hudait).
Regarding claim 2, Pinos discloses the method of claim 1, but does not disclose wherein the base layer of the substrate has a nominal offcut angle of between about 0.0 and ±4.0 degrees. Note that Pinos does not specify offcut angle in any capacity.
However, Hudait discloses a method of fabricating a semiconductor device, comprising: providing a substrate in figure 5, the substrate comprising a base layer (510) (Col. 13, lines 1-5) and two or more planar heteroepitaxial layers (585 and 581) (Col. 12, lines 5-28) deposited on the base layer; etching the substrate to form one or more mesas (Col. 13, lines 1-8); wherein the base layer (510) of the substrate has a nominal offcut angle of between about 0.0 and ±4.0 degrees (Col. 9, lines 58-63).
Therefore, it would have been obvious to a person of ordinary skill in the art (POSITA) before the effective filing date of the invention to modify the device of Pinos in light of the disclosure of Hudait to have a nominal offcut angle between about 0.0 and ±4.0 degrees in order to decrease the number of terrace levels and the necessary thickness of the nucleation layer as taught by Hudait (Col. 8, lines 43-48).
Response to Arguments
Applicant’s arguments with respect to claims 1-13 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/NORMAN D RICHARDS/ Supervisory Patent Examiner, Art Unit 2892
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