Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after allowance or after an Office action under Ex Parte Quayle, 25 USPQ 74, 453 O.G. 213 (Comm'r Pat. 1935). Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, prosecution in this application has been reopened pursuant to 37 CFR 1.114. Applicant's submission filed on 10/27/2025 has been entered.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over US 10,192,867 B1 to Frougier et al. (hereinafter Frougier) in view of US 11,502,167 B2 (US 2022/0109046 A1) to Hong et al. (hereinafter Hong) and Huang et al. (US 2021/0336012 A1).
Regarding independent claim 1: Frougier teaches a semiconductor device comprising:
a bottom field effect transistor (FET) (820, Fig. 7, Col. 7, Ins. 53-55);
a top FET (1330, Fig. 12, Col. 8, In. 64 - Col. 9, In. 1) stacked over the bottom FET;
a bottom gate (G1, Fig. 7, Col. 7, Ins. 55-58) formed in contact with the bottom FET;
a top gate (G2, Fig. 12, Col. 9, Ins. 1-3) formed in contact with the top FET; and a bottom contact (1820 and 1830, Fig. 17, Col. 9, In. 62 - Col. 10, In. 1) formed adjacent to the top gate, wherein an inner spacer (1110, Fig. 17, Col. 8, Ins. 24-27) is formed between the bottom contact and the top gate.
Frougier does not teach where the top FET has a smaller active area than the bottom FET;
a gate spacer surrounding a portion of the high-k metal gate layer in the top FET; and a hardmask layer in contact with the gate spacer, wherein the gate spacer, the hardmask layer, the inner spacers and the dielectric isolation layer are all formed between the bottom contact and the high-k metal gate of the top FET.
Hong teaches (e.g., Fig. 3C) a semiconductor device, wherein the top FET (302, Fig. 3C) has a smaller active area than the bottom FET (301, Fig. 3C, Col. 8, Ins. 1-3, the length of the bottom nanosheet layer is greater than the length of the top nanosheet layers).
The advantage of this structure is that it provides a stepped structure that reduces the footprint of the FET.
Frougier and Hong teach stacked FET devices comprised of layers of nanosheets.
Hong teaches a stacked FET wherein the bottom FET is larger than the top FET.
It would have been obvious to one of ordinary skill in the art at the time the claims were effectively filed to apply the stepped structure of Hong to the FET of Frougier to overcome the limitation of the prior art where the stacked FETs are the same size and instead provide a stepped structure that reduces the footprint of the FET.
Huang teaches (e.g., Figs. 1A-22E) a semiconductor device comprising:
a gate spacer ([00385]: 606) surrounding a portion of a high-k metal gate layer ([0028], [0035] and [0039]: MG; 706) in a top FET (upper portion transistor): and
a hardmask layer ([0041]: 708; see [0031]: corresponding to Hard Mask 508) in contact with the gate spacer (606).
wherein the gate spacer (606), the hardmask layer (708), the inner spacers ([0038] and [0040]: 606A) and a dielectric isolation layer ([0020]: 204) are all formed between the bottom contact (1202) and the high-k metal gate (702) of the top FET.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to include in the device of Frougier as modified by Hong, the gate spacer surrounding a portion of the high-k metal gate layer in the top FET; and a hardmask layer in contact with the gate spacer, wherein the gate spacer, the hardmask layer, the inner spacers and the dielectric isolation layer are all formed between the bottom contact and the high-k metal gate of the top FET, as taught by Huang, for the benefits of shielding the gate metal from surrounding conductive structure thus avoiding short-circuit, and at the same time allowing signal ommunication between the stacked transistors.
Regarding claim 2, Frougier as modified by Hong further teaches the semiconductor device of claim 1, wherein the bottom FET includes alternating layers of active semiconductor layers (312, Fig. 12) and high-k metal gate layers (Fig. 12, 1310) (Col. 8, Ins. 36-52 dummy gate 340 and SiGe layer 311 are removed, leaving Si layer 312 and HKMG 1310).
Regarding claim 3, Frougier as modified by Hong further teaches the semiconductor device according to claim 2, further comprising a gate spacer (Fig. 12, 370, Col. 6, Ins. 21-25 dummy gate 340 replaced with HKMG layer 1310 in subsequent step) surrounding the high-k metal gate layers.
Regarding claim 4, Frougier as modified by Hong further teaches the semiconductor device of claim 3, wherein for the top FET, the gate spacer is formed in contact with the inner spacer (Fig. 10 and Col. 8, Ins. 24-27, dielectric layer 1110 is formed over gate spacers 370).
Regarding claim 5, Frougier as modified by Hong further teaches the semiconductor device of claim 3, wherein the gate spacer and the inner spacer are dielectric layers (Col. 6, Ins. 25-29, material of gate spacer 370 is any one or more of a variety of insulative materials and Col. 8, Ins. 23-24 forming dielectric layer 1110).
Regarding claim 6: Frougier as modified by Hong further teaches the semiconductor device according to claim 1, wherein the top FET includes a top epitaxial layer (1010, 1020, Fig. 9, Col. 8, Ins. 9-14 epitaxial growth of Si layer 1010 and SiGe layer 1020).
Regarding claim 7: Frougier as modified by Hong further teaches the semiconductor device according to claim 6, wherein at least a portion of the inner spacer is formed between the bottom contact and the top epitaxial layer (1110 between 1820 and 1610, Fig. 17, Col. 9, Ins. 43-50 conformal silicide layer 1610 formed from silicidation process of Si layer 1010, Col. 9, In. 62-Col. 10, In. 1 first vertical conductive metal region 1820 forms wrap-around contact for first (i.e., bottom) FET 820).
Regarding claim 8: Frougier does not teach the semiconductor device according to claim 1, wherein an active region of the top FET is laterally offset from an active region of the bottom FET to form a staircase configuration.
Hong teaches the semiconductor device according to claim 1, wherein an active region of the top FET is laterally offset from an active region of the bottom FET to form a staircase configuration (Figs. 3A-3E, Col. 8, Ins, 1-3 the length of the bottom nanosheet layers are greater than the length of the top nanosheet layers). The advantage of this structure is that it provides a stepped structure that reduces the footprint of the FET
Frougier and Hong teach stacked FET devices comprised of layers of nanosheets. Hong teaches a stacked FET wherein the bottom FET is larger than the top FET.
It would have been obvious to one of ordinary skill in the art at the time the claims were effectively filed to apply the stepped structure of Hong to the FET of Frougier to overcome the limitation of the prior art where the stacked FETs are the same size and instead provide a stepped structure that reduces the footprint of the FET.
Regarding claim 9: Frougier as modified by Hong further teaches the semiconductor device according to claim 1, further comprising a hardmask layer (Fig. 12, 1320, Col. 8, Ins. 59-60 forming a cap 1320 in contact with HKMG 1310) in contact with the top gate.
Regarding claim 10, Frougier as modified by Hong further teaches the semiconductor device according to claim 9, wherein the hardmask is comprised of a different material than the inner spacer (Col. 8, Ins. 62-63 the cap 1320 may be formed of different material than the gate spacers 370).
Regarding claim 11, Frougier teaches a semiconductor device comprising: a bottom field effect transistor (FET) (820, Fig. 7, Col. 7, Ins. 53-55); a top FET (1330, Fig. 12, Col. 8, In. 64 - Col. 9, In. 1) stacked over the bottom FET;
a bottom gate (G1, Fig. 7, Col. 7, Ins. 55-58) formed in contact with the bottom FET;
a top gate (G2, Fig. 12, Col. 9, Ins. 1-3) formed in contact with the top FET; and a bottom contact (1820 and 1830, Fig. 17, Col. 9, In. 62 - Col. 10, In. 1) formed adjacent to the top gate, wherein an inner spacer (1110, Fig. 17, Col. 8, Ins. 24-27) is formed between the bottom contact and the top gate.
Frougier does not teach where the top FET has a smaller active area than the bottom FET;
a gate spacer surrounding a portion of the high-k metal gate layer in the top FET; and a hardmask layer in contact with the gate spacer, wherein the gate spacer, the hardmask layer, the inner spacers and the dielectric isolation layer are all formed between the bottom contact and the high-k metal gate of the top FET.
Hong teaches where the top FET (302, Fig. 3C) has a smaller active area than the bottom FET (301, Fig. 3C, Col. 8, Ins. 1-3, the length of the bottom nanosheet layers is greater than the length of the top nanosheet layers). The advantage of this structure is that it provides a stepped structure that reduces the footprint of the FET
Frougier and Hong teach stacked FET devices comprised of layers of nanosheets. Hong teaches a stacked FET wherein the bottom FET is larger than the top FET.
It would have been obvious to one of ordinary skill in the art at the time the claims were effectively filed to apply the stepped structure of Hong to the FET of Frougier to overcome the limitation of the prior art where the stacked FETs are the same size and instead provide a stepped structure that reduces the footprint of the FET.
Huang teaches (e.g., Figs. 1A-22E) a semiconductor device comprising:
a gate spacer ([00385]: 606) surrounding a portion of a high-k metal gate layer ([0028], [0035] and [0039]: MG; 706) in a top FET (upper portion transistor): and
a hardmask layer ([0041]: 708; see [0031]: corresponding to Hard Mask 508) in contact with the gate spacer (606).
wherein the gate spacer (606), the hardmask layer (708), the inner spacers ([0038] and [0040]: 606A) and a dielectric isolation layer ([0020]: 204) are all formed between the bottom contact (1202) and the high-k metal gate (702) of the top FET.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to include in the device of Frougier as modified by Hong, the gate spacer surrounding a portion of the high-k metal gate layer in the top FET; and a hardmask layer in contact with the gate spacer, wherein the gate spacer, the hardmask layer, the inner spacers and the dielectric isolation layer are all formed between the bottom contact and the high-k metal gate of the top FET, as taught by Huang, for the benefits of shielding the gate metal from surrounding conductive structure thus avoiding short-circuit, and at the same time allowing signal ommunication between the stacked transistors.
Regarding claim 12: Frougier as modified by Hong further teaches the semiconductor device of claim 11, wherein the bottom FET includes alternating layers of active semiconductor layers (312, Fig. 12) and high-k metal gate layers (Fig. 12, 1310) (Col. 8, Ins. 36-52 dummy gate 340 and SiGe layer 311 are removed, leaving Si layer 312 and HKMG 1310).
Regarding claim 13, Frougier as modified by Hong further teaches the semiconductor device according to claim 12, further comprising a gate spacer (Fig. 12, 370, Col. 6, Ins. 21-25 dummy gate 340 replaced with HKMG layer 1310 in subsequent step) surrounding the high-k metal gate layers.
Regarding claim 14, Frougier as modified by Hong further teaches the semiconductor device of claim 13, wherein for the top FET, the gate spacer is formed in contact with the inner spacer (Fig. 10 and Col. 8, Ins. 24-27, dielectric layer 1110 is formed over gate spacers 370).
Regarding claim 15, Frougier as modified by Hong further teaches the semiconductor device of claim 13, wherein the gate spacer and the inner spacer are
dielectric layers (Col. 6, Ins. 25-29, material of gate spacer 370 is any one or more of a variety of insulative materials and Col. 8, Ins. 23-24 forming dielectric layer 1110).
Regarding claim 16, Frougier as modified by Hong further teaches the semiconductor device according to claim 11, wherein the top FET includes a top epitaxial layer (1010, 1020, Fig. 9, Col. 8, Ins. 9-14 epitaxial growth of Si layer 1010 and SiGe layer 1020).
Regarding claim 17, Frougier as modified by Hong further teaches the semiconductor device according to claim 16, wherein at least a portion of the inner spacer is formed between the bottom contact and the top epitaxial layer (1110 between 1820 and 1610, Fig. 17, Col. 9, Ins. 43-50 conformal silicide layer 1610 formed from silicidation process of Si layer 1010, Col. 9, In. 62-Col. 10, In. 1 first vertical conductive metal region 1820 forms wrap-around contact for first (i.e., bottom) FET 820).
Regarding claim 18, Frougier does not teach the semiconductor device according to claim 11, wherein an active region of the top FET is laterally offset from an active region of the bottom FET to form a staircase configuration.
Hong teaches the semiconductor device according to claim 11, wherein an active region of the top FET is laterally offset from an active region of the bottom FET to form a staircase configuration (Figs. 3A-3E, Col. 8, Ins, 1-3 the length of the bottom nanosheet layers are greater than the length of the top nanosheet layers).
The advantage of this structure is that it provides a stepped structure that reduces the footprint of the FET; Frougier and Hong teach stacked FET devices comprised of layers of nanosheets. Hong teaches a stacked FET wherein the bottom FET is larger than the top FET. It would have been obvious to one of ordinary skill in the art at the time the claims were effectively filed to apply the stepped structure of Hong to the FET of Frougier to overcome the limitation of the prior art where the stacked FETs are the same size and instead provide a stepped structure that reduces the footprint of the FET.
Regarding claim 19, Frougier as modified by Hong further teaches the semiconductor device according to claim 11, further comprising a hardmask layer (Fig. 12, 1320, Col. 8, Ins. 59-60 forming a cap 1320 in contact with HKMG 1310) in contact with the top gate.
Regarding claim 20, Frougier as modified by Hong further teaches the semiconductor device according to claim 19, wherein the hardmask is comprised of a different material than the inner spacer (Col. 8, Ins. 62-63 the cap 1320 may be formed of different material than the gate spacers 370).
Conclusion
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/HERVE-LOUIS Y ASSOUMAN/ Examiner, Art Unit 2812
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