Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Applicant’s arguments with respect to claims 1-2, 5-15 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
DETAILED ACTION
This action is responsive to application No. 17806514 filed on 06/13/2022.
Information Disclosure Statement
Acknowledgment is made of Applicant’s Information Disclosure Statement (IDS) form PTO-1449. These IDS has been considered.
Election/Restrictions
Applicant’s election without traverse of claims 1-16 in the reply filed on 7/31/2025 is acknowledged.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 5-7, 10-15 are rejected under 35 U.S.C. 103 as being unpatentable over Chung (US 2021/0375861) in view of Huang et al. (US 2023/0268344).
Regarding Independent claim 1, Chung et al. teach a semiconductor structure, comprising:
a via (Fig. 31B, element 36) in a semiconductor material (Fig. 31B, element 50); and
a dielectric liner (Fig. 31B, element 34) surrounding vertical sides of the via.
Chung et al. do not explicitly disclose a rectangular-shaped via; wherein the rectangular shaped via directly contacts (i) a source/drain and (ii) a power rail; and the rectangular-shaped via tapers such that a first surface contacting the source/drain has smaller surface area than a second surface contacting the power rail; and wherein a surface of the dielectric line directly contacts the power rail and the surface of the dielectric liner is coplanar with the second surface.
Huang et al. teach a semiconductor device comprising a rectangular-shaped via (Fig. 20C, elements 350 & 360); wherein the rectangular shaped via directly contacts (i) a source/drain (Fig. 20C, element 240) and (ii) a power rail (Figs. 20B & 20C, elements 370, 372 & 374); and the rectangular-shaped via tapers such that a first surface contacting the source/drain has smaller surface area than a second surface contacting the power rail (Fig. 20C); and wherein a surface of the dielectric liner (Fig. 20C, element 340) directly contacts the power rail and the surface of the dielectric liner is coplanar with the second surface (Fig. 20C).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to modify the teachings of Chung et al. according to the teachings of Huang et al. with the motivation to increasing production efficiency and lowering associated costs (paragraph 0002).
Regarding claim 2, Chung et al. modified by Huang et al. teach wherein the rectangular-shaped via contacts a rectangular-shaped portion of the source/drain and a rectangular-shaped portion of the power rail (Fig. 20C of Huang).
Regarding claim 5, Chung et al. modified by Huang et al. teach wherein the power rail is a backside power rail (Figs. 20B & 20C, elements 370, 372 & 374 of Huang are metal lines and interlayer dielectric structurally analogous to the instant application).
Regarding claim 6, Chung et al. modified by Huang et al. teach wherein the source/drain is on a selection from the group consisting of: a backside of a semiconductor device and a frontside of the semiconductor device (Figs. 20A-20D, paragraph 0063 of Huang).
Regarding Independent claim 7, Chung et al. teach a semiconductor structure comprising:
a contact via (Fig. 31B, element 36) in a semiconductor material (Fig. 31B, element 50) of a semiconductor device (paragraph 0101 discloses nanowire or nanosheet device);
Chuang et al. do not explicitly disclose a square-shaped contact via; a first semiconductor device element under the square-shaped contact via; and a second semiconductor device element above the square-shaped contact via, wherein the square shaped contact via tapers such that a first surface contacting the first semiconductor device element has a smaller surface area than a second surface contacting the second semiconductor device element.
Huang et al. teach a semiconductor device comprising a square-shaped contact via (Fig. 20C, elements 350 & 360); a first semiconductor device element (Fig. 20C, element 240) under the square-shaped contact via; and a second semiconductor device element (Figs. 20B & 20C, elements 370, 372 & 374) above the square-shaped contact via, wherein the square shaped contact via tapers such that a first surface contacting the first semiconductor device element has a smaller surface area than a second surface contacting the second semiconductor device element (Fig. 20C).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to modify the teachings of Chung et al. according to the teachings of Huang et al. with the motivation to increasing production efficiency and lowering associated costs (paragraph 0002).
Regarding claim 10, Chung et al. modified by Huang et al. teach wherein the first semiconductor device element is a source/drain (Fig. 20C, element 240, paragraph 0035) of the semiconductor device.
Regarding claim 11, Chung et al. modified by Huang et al. teach wherein the second semiconductor device element is a selection from the group consisting of: a power rail (Figs. 20B & 20C, elements 370, 372 & 374 of Huang are metal lines and interlayer dielectric structurally analogous to the instant application), a backside power rail, and a pad in an interconnect wiring layer.
Regarding claim 12, Chung et al. modified by Huang et al. teach wherein the semiconductor device is selected from the group consisting of a logic device (paragraph 0024 of Chuang), a memory device, and a photovoltaic device.
Regarding claim 13, Chung et al. modified by Huang et al. teach wherein the semiconductor device is a nanosheet transistor (paragraph 0101 of Huang).
Regarding claim 14, Chung et al. modified by Huang et al. teach wherein the source/drain is on a backside of a nanosheet transistor (paragraph 0101 of Huang discloses nanosheet paragraph 0057 of Huang discloses backside via).
Regarding claim 15, Chung et al. modified by Huang et al. teach wherein the source/drain is on a backside of the nanosheet transistor and connects to a backside power rail by the square-shaped contact via (Fig. 20C of Huang, Fig. 31B of Chung), further comprising: a dielectric layer with at least one via (Fig. 31B, element 136, paragraph 0095 of Chung) over the backside power rail; and a back end of line interconnect wiring layer connecting, by the at least one via, to the backside power rail (Fig. 31B, paragraph 0096-0098 of Chung).
Claims 8-9 are rejected under 35 U.S.C. 103 as being unpatentable over US 2021/0375861) in view of Huang et al. (US 2023/0268344) and further in view of Ren et al. (US 2023/0260825).
Regarding claim 8, Chung et al. modified by Huang et al. teach all of the limitations as discussed above.
Chung et al. modified by Huang et al. do not explicitly disclose wherein the square-shaped via in the semiconductor material has straight edges that are parallel to one or more (110) crystal planes of the semiconductor material.
Ren et al. teach a semiconductor device comprising wherein the via in the semiconductor material has straight edges that are parallel to one or more (110) crystal planes of the semiconductor material (paragraph 0006).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to modify the teachings of Chung et al. and Huang et al. according to the teachings of Ren et al. with the motivation to backside power via for a transistor structure (paragraph 0006).
Regarding claim 9, Chung et al. modified by Huang et al. teach all of the limitations as discussed above.
Chung et al. modified by Huang et al. do not explicitly disclose wherein the square-shaped contact via in the semiconductor material has corners pointing in a direction orthogonal to one or more of (100) crystal planes of the semiconductor material.
Ren et al. teach a semiconductor device comprising wherein the contact via in the semiconductor material has corners pointing in a direction orthogonal to one or more of (100) crystal planes of the semiconductor material (paragraph 0006).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to modify the teachings of Chung et al. and Huang et al. according to the teachings of Ren et al. with the motivation to backside power via for a transistor structure (paragraph 0006).
Conclusion
THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHAHED AHMED whose telephone number is (571)272-3477. The examiner can normally be reached M-F 9-5.
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/SHAHED AHMED/Primary Examiner, Art Unit 2813