Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on February 3, 2026 has been entered.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3, 14-15, 18 and 27 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yilmaz (US 2006/0076629).
Regarding claim 1, Yilmaz discloses a semiconductor device comprising:
a buried layer (508/515) of a first conductivity type (N+) on a semiconductor substrate (40) [Figs. 5A-5B];
a trench capacitor (506/514) extending into the buried layer (508/515) and laterally surrounding a transistor (54/58) [Figs. 5A-5B], the trench capacitor 1comprising:
a conductive region (310,506/514) within a trench (308) extending and touching into the buried layer (508/515) [Figs. 3A-3F and 5A-5B];
a dielectric (306) disposed around the conductive region (310,506/514) [Figs. 3A-3F and 5A-5B]; and
a doped region (507/511) disposed around the dielectric (306) and extending into and touching the buried layer (508/515) [Figs. 3A-3F and 5A-5B].
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Regarding claim 2, Yilmaz discloses wherein the dielectric (306) extends between the conductive region (310) and the buried layer (508/515) [Figs. 3A-3F and 5A-5B].
Regarding claim 3, Yilmaz discloses a semiconductor layer (52) disposed on the buried layer (508/515), wherein the trench capacitor (506/514) extends through the semiconductor layer (52) [Figs. 5A-5B].
Regarding claim 14, Yilmaz discloses conductive features (314/C) disposed in a metallization structure (312) disposed over the trench capacitor (310/306), the conductive features (314/C) conductively connected to the trench capacitor (310/306) [Figs. 3H and 5A].
Regarding claim 15, Yilmaz discloses wherein the conductive features (506) comprises a first contact (C) coupled to the conductive region of the trench capacitor (506) [Figs. 5A]; and a second contact (B) coupled to the doped region (507) of the trench capacitor [Fig. 5A].
Regarding claim 18, Yilmaz discloses a method for manufacturing a semiconductor device, the method comprising:
forming a buried layer (300,507,511) on a semiconductor substrate (40), the buried layer having a first conductivity type (N) [Figs. 3A, 5A and 5B, and paragraph 0019];
forming a semiconductor layer (302/52) on the buried layer [Figs. 3A, 5A and 5B, and paragraph 0019];
forming a transistor (54/58) on or over the semiconductor layer [Figs. 5A and 5B, and paragraphs 0036-0040]; and
forming a trench capacitor (506/514) adjacent to the transistor, the trench capacitor (506/514) comprising a deep trench (308) laterally surrounding the transistor (54/58) [Figs. 3B, 5A and 5B], the deep trench (308) filled with a conductive material (310,506,514) [Figs. 3E, 5A and 5B], a dielectric region (306) around the conductive material [Fig. 3F and 5A-5B], and a doped region (507/511) around the dielectric region [Figs. 5A-5B], the conductive material (310,506,514) and the doped region (507) extending down from a first surface of the semiconductor layer (300/52) and into and touching the buried layer (508) [Figs. 3H and 5A].
Regarding claim 27, Yilmaz discloses wherein the conductive region (310/506/514) comprises doped polysilicon [Figs. 3E and 5A-5B and paragraphs 0024 and 0073].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 4-5, 7-12, 17 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Yilmaz (US 2006/0076629).
Regarding claims 4-5, Yilmaz discloses an example in which an inner width of the trench capacitor (308) is about 1 µm when the thickness of the P layer 302 is 10 µm [paragraph 0021]. Thus, it would have been obvious to one of ordinary skill in the art to include a thicker P layer (i.e. greater than 10 µm thick) such that the inner width of the trench capacitor is in the range of greater than about 1.2 µm, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Huang, 40 USPQ2d 1685,1688(Fed. Cir. 1996) citing In re Aller, 105 USPQ 233., 235 (CCPA 1955).
Regarding claim 7, Yilmaz discloses wherein an inner width of the trench capacitor is between 0.01 times a depth of the trench capacitor and 0.1 times the depth of the trench capacitor [Figure 3B shows that the depth of the trench 308 is equal to the thickness of the layer 302, and paragraph 0021 discloses that the thickness of layer 302 is, for example, 10 µm. In addition, Yilmaz discloses a width of about 1 µm which is equivalent to 0.1 times the depth of the trench capacitor (e.g. 10 µm). See paragraph 0021]. Please note that the court has held that in the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists. In re Wertheim, 541F.2d 257,191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990).
Regarding claim 8, Yilmaz discloses an embodiment in which at least a portion of the trench capacitor (802) comprises a cylindrical (circular) capacitor [See Fig. 8B].
Regarding claims 9-10, Yilmaz does not disclose a trench capacitor having an hexagonal cylindrical or conical shape. However, it is considered that the claimed device is not patentably distinct from the prior art device since the configuration of the trench is a matter of choice which a person of ordinary skill in the art would have found obvious absent persuasive evidence that the particular configuration of the claimed trench is significant. See In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966). Also, In Gardner v. TEC Syst., Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984), the Federal Circuit held that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device.
Regarding claims 11-12, it is noted that using phosphorous as an n-type implant is well-established in the art. For example, Yilmaz discloses a buried layer (508) and a doped region (507) comprising n-type dopants [Fig. 5A]. In addition, Yilmaz discloses that n-type dopant include phosphorus, which can be heavily implanted (N+) at a concentration of 1018-1019 atoms-cm3 [paragraphs 0024, 0037, and 0042]. Hence, it is within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use. See In re Leshin, 125 USPQ 416.
Regarding claim 17, Yilmaz discloses wherein a width of the dielectric (306) is between 0.1 µm and 1 µm [Fig. 3C and paragraph 0022]. Please note that the court has held that in the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists. In re Wertheim, 541F.2d 257,191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990).
Regarding claim 20, Yilmaz discloses:
forming a trench of an isolation deep trench (535/305) simultaneously as forming the deep trench of the trench capacitor (506) [Figs. 3B and 5A, and paragraph 0018];
forming the dielectric region (306, 506/514) and a dielectric liner (306, 535) of the isolation deep trench simultaneously as forming the dielectric region of the trench capacitor [Figs. 3C and 5A, and paragraphs 0018 and 0037-0040]; and
forming polysilicon region (310) of the isolation deep trench (535) simultaneously as forming the polysilicon region (310) of the trench capacitor (506/514) [Figs. 3C and 5E, and paragraphs 0018 and 0037-0040].
In regards to the claimed order of performing process steps, the court has held that selection of any order of performing process steps is prima facie obvious in the absence of new or unexpected results. In re Burhans, 154 F.2d 690, 69 USPQ 330 (CCPA 1946).
Claims 13 and 21-24 are rejected under 35 U.S.C. 103 as being unpatentable over Yilmaz (US 2006/0076629) in view of Shimada et al. (US 2008/0023787).
Regarding claim 13, Yilmaz does not disclose a dielectric having a higher dielectric constant than silicon oxide.
Shimada suggests that the dielectric (6a/6b) may be an insulation film other than silicon oxide [paragraphs 0034-0035: “[a]n insulation film 6b (e.g. silicon oxidation film)…” ].
Therefore, one of ordinary skill in the art, before the effective filing date of the claimed invention, would have been motivated to modify Yilmaz by including an insulation film having a higher dielectric constant as taught by Shimada because it helps to insulate between the trench and the epitaxial layer [paragraph 0034]. In addition, the court has held that it is within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416 (CCPA 1960); Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945).Regarding claims 21-22, Yilmaz does not disclose a width of the deep trench of the deep trench capacitor that is less than a width of the trench of the isolation deep trench, and a depth of the deep trench of the trench capacitor that is less than a depth of the trench of the isolation deep trench.
Regarding claims 21-22, Yilmaz does not disclose a width of the deep trench of the deep trench capacitor that is less than a width of the trench of the isolation deep trench, and a depth of the deep trench of the trench capacitor that is less than a depth of the trench of the isolation deep trench.
In regards to claim 21, Shimada teaches wherein a width (W1) of the deep trench (7) touching the buried layer (3) is less than a width (W) of the trench of the isolation deep trench (5) [Fig. 9 and paragraph 0047].
In regards to claim 22, Shimada teaches wherein a depth of the deep trench (7) touching the buried layer (3) is less than a depth of the trench of the isolation deep trench (5) [Fig. 9 and paragraph 0047].
Therefore, one of ordinary skill in the art, before the effective filing date of the claimed invention, would have been motivated to modify Yilmaz by including the isolation deep trench as taught by Shimada because it helps to prevent leakage current [paragraph 0060].
Regarding claim 23, Yilmaz discloses a semiconductor structure, comprising:
a buried layer (300,508,515) disposed on a semiconductor substrate (40), the buried layer (300,505,515) having a first conductivity type (N) Figs. 3A, 5A and 5B, and paragraph 0019];
a semiconductor layer (302/52) disposed on the buried layer [Figs. 3A, 5A and 5B, and paragraph 0019];
a transistor (54/58) disposed on or over the semiconductor layer [Figs. 5A and 5B, and paragraphs 0036-0040]; and
a capacitor (506/514) extending through the semiconductor layer (52) and into the buried layer (508,515), the capacitator disposed core, the doped region and the conductive core extending into and touching the buried layer [Figs. 3A, 5A and 5B].
However, Yilmaz does not disclose an isolation deep trench extending through the semiconductor layer and into the semiconductor substrate.
Shimada teaches an isolation deep trench (5,6a,8a) extending through the semiconductor layer (2) and into the semiconductor substrate (1) and laterally surrounding a trench structure that is extended through the semiconductor layer (2) and into the buried layer (3) [Figs. 9-11].
Therefore, one of ordinary skill in the art, before the effective filing date of the claimed invention, would have been motivated to modify Yilmaz by including an isolation deep trench such that the capacitator is disposed between the transistor and the isolation deep trench as taught by Shimada because it helps to prevent leakage current [paragraph 0060].
Regarding claim 24, Yilmaz discloses wherein the capacitor is a first capacitor (506/514 - right side), and further comprising a second capacitor (506/514 - left side) extending through the semiconductor layer and into the buried layer and terminating in the buried layer (508/515), the second capacitor (506) adjacent to the transistor (54/58) [Figs. 5A-5B].
Allowable Subject Matter
Claim 26 is allowed.
Claims 16, 19, and 25 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Response to Arguments
Applicant’s arguments with respect to claims 1-5, 7-1517-18, 20-24 and 27 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOSE R DIAZ whose telephone number is (571)272-1727. The examiner can normally be reached Monday-Friday.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Joshua Benitez can be reached at 571-270-1435. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Jose R Diaz/Primary Examiner, Art Unit 2815
1 The term “trench capacitor” is considered to be just a label used to identify a structure comprising: a trench, a conductive region, a dielectric and a doped region, as defined in claim 1.