DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 01/26/2026 has been entered.
Response to Arguments
Applicant's arguments filed 01/26/2026 have been fully considered and overcome the previous drawings objection and written description rejections but they are moot in view of the new grounds of rejection as detailed below in light of Applicant’s claim amendments.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1,3,5,11,27-29 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by U.S. Patent Application Publication Number 2020/0219871 A1 to Moens et al., “Moens”.
Regarding claim 1, Moens discloses a semiconductor device (FIG. 3, alternately FIG. 5), comprising:
a silicon substrate layer (102, ¶ [0031]);
a first semiconductor layer (206, ¶ [0036]) comprising a gallium nitride layer, the first semiconductor layer (206) disposed over the silicon substrate layer (102);
a second semiconductor layer (208, ¶ [0036],[0039]) disposed on the first semiconductor layer (206), the second semiconductor layer (208) comprising an aluminum gallium nitride layer (¶ [0039]), wherein a 2DEG channel (200, ¶ [0036],[0042]) is formed at an interface between the gallium nitride layer (206) and the aluminum gallium nitride layer (208); and
a first drain contact (322 and 108 together, ¶ [0043],[0044]) extending through the second semiconductor layer (208) and extending into the first semiconductor layer (206), the first drain including a first portion (322) extending into the first semiconductor layer (206) and a second portion (108, ¶ [0043]-[0045]) extending laterally in the gallium nitride layer (206).
Regarding claim 3, Moens discloses the semiconductor device of claim 1, and Moens further discloses (FIG. 3) a dielectric layer (300, ¶ [0043]) disposed on the second semiconductor layer (208), the dielectric layer (300) having at least one metallization layer (324, ¶ [0044]) embedded therein.
Regarding claim 5, Moens discloses the semiconductor device of claim 1, and Moens further discloses (FIG. 5) a source contact (526 and 518, ¶ [0052]) extending through the second semiconductor layer (208) and into the first semiconductor layer (206).
Regarding claim 11, Moens discloses the semiconductor device of claim 1, and Moens further discloses (FIG. 3) a shallow source contact (326, ¶ [0043]).
Regarding claim 27, Moens discloses the semiconductor device of claim 1, and Moens further discloses wherein the second portion (108) of the first drain contact includes a doped semiconductor layer (¶ [0034]).
Regarding claim 28, Moens discloses the semiconductor device of claim 1, and Moens further discloses wherein the second portion (108) of the first drain contact includes a conductive channel with electrons or holes (holes since p-type ¶ [0034]).
Regarding claim 29, Moens discloses the semiconductor device of claim 1, and Moens further discloses wherein the second portion (108) of the first drain contact extends laterally in the gallium nitride layer (206) at an angle that is perpendicular with respect to the first portion of the first drain contact (right angle between 322 and 108 as pictured).
Claims 1,8-10,31 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by U.S. Patent Application Publication Number 2022/0376084 A1 to Hao et al., “Hao `084”.
Regarding claim 1, Hao `084 discloses a semiconductor device (FIG. 9A), comprising:
a silicon substrate layer (102, ¶ [0048]);
a first semiconductor layer (104 and 110 together) comprising a gallium nitride layer (¶ [0049],[0053]), the first semiconductor layer (104) disposed over the silicon substrate layer (102);
a second semiconductor layer (112) disposed on the first semiconductor layer (104), the second semiconductor layer (112) comprising an aluminum gallium nitride layer (¶ [0053]), wherein a 2DEG channel (¶ [0054]) is formed at an interface between the gallium nitride layer (110) and the aluminum gallium nitride layer; and
a first drain contact (160A) extending through the second semiconductor layer (112) and extending into the first semiconductor layer (into 110 and 104), the first drain including a first portion (e.g. vertical portion in 110) extending into the first semiconductor layer and a second portion (lower portion in 108, see Examiner-annotated figure below) extending laterally in the gallium nitride layer (108 is part of 104).
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Examiner’s Note: the language of “extends laterally” is interpreted under the doctrine of broadest reasonable interpretation (BRI, MPEP 2111) as including lateral extension but not necessarily requiring the second portion extending laterally beyond the first portion.
Regarding claim 8, Hao `084 discloses the semiconductor device of claim 1, and Hao `084 further discloses wherein the gallium nitride layer comprises an undoped gallium nitride layer (110, undoped since not described as doped as would have been conveyed to one having ordinary skill in the art) disposed over a carbon doped gallium nitride layer (108, ¶ [0051]).
Regarding claim 9, Hao `084 discloses the semiconductor device of claim 8, and Hao `084 further discloses wherein the first drain contact (160A) extends through the undoped gallium nitride layer (110) and into the carbon doped gallium nitride layer (108).
Regarding claim 10, Hao `084 discloses the semiconductor device of claim 1, and Hao `084 further discloses wherein the first drain contact (160) comprises a singular elongated drain contact (modification of FIG. 1 elongated singular drain contact 130, ¶ [0046]).
Regarding claim 31, Hao `084 discloses the semiconductor device of claim 1, and Hao `084 further discloses wherein the first and second portions of the first drain contact (160A) have a same material composition (single layer as pictured).
Claims 1,22-23,25-26,32,36 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by U.S. Patent Application Publication Number 2021/0202730 A1 to Hao et al., “Hao `730”.
Regarding claim 1, Hao `730 discloses a semiconductor device (FIG. 1A), comprising:
a silicon substrate layer (101, ¶ [0019]);
a first semiconductor layer (103, ¶ [0023]) comprising a gallium nitride layer, the first semiconductor layer disposed over the silicon substrate layer (102);
a second semiconductor layer (104, ¶ [0027]) disposed on the first semiconductor layer, the second semiconductor layer comprising an aluminum gallium nitride layer, wherein a 2DEG channel (¶ [0035]) is formed at an interface between the gallium nitride layer (103) and the aluminum gallium nitride layer (104); and
a first drain contact (107 and 103’ together) extending through the second semiconductor layer and extending into the first semiconductor layer, the first drain including a first portion (107, ¶ [0018]) extending into (“the conductive structure 107 may extend into the doped semiconductor structure 103′ ” ¶ [0087]) the first semiconductor layer (103) and a second portion (103’) extending laterally in the gallium nitride layer (103).
Regarding claim 22, Hao `730 discloses a structure (FIG. 1A), comprising:
a gallium nitride layer (103, ¶ [0023]) disposed on a silicon substrate (101, ¶ [0019]);
an aluminum gallium nitride layer (104, ¶ [0027]) disposed on the gallium nitride layer, wherein a 2DEG channel (¶ [0035]) is formed at an interface between the gallium nitride layer and the aluminum gallium nitride layer;
a silicon nitride layer (105, ¶ [0036]) disposed on the aluminum gallium nitride layer;
at least one metallization layers disposed in the silicon nitride layer, the at least one metallization layers forming a drain electrode (e.g. upper portion of 107, similar to Applicant’s use of the term e.g. Applicant’s ¶ [0031]), a gate electrode (106), and a source electrode (e.g. upper portion of 108, similar to Applicant’s use of the term e.g. Applicant’s ¶ [0031]); and at least one drain terminal (107 and 103’ together, ¶ [0018],[0024]) coupled to the drain electrode, the at least one drain terminal (i.e. structure connected to drain) including a first portion (107) extended through the silicon nitride layer (105) and aluminum gallium nitride layer (104) and into the gallium nitride layer (103) and a second portion (103’, ¶ [0024]) extended laterally in the gallium nitride layer (103).
Regarding claim 23, Hao `730 discloses the structure of claim 22, and Hao `730 further discloses a source terminal (108) extending through the silicon nitride layer (105) and through the aluminum gallium nitride layer (104), the source terminal coupled to the source electrode (108, inherent since 108 is the source and must be biased to source terminal, identical to Applicant’s use of “S” for source terminal).
Regarding claim 25, Hao `730 discloses the structure of claim 22, and Hao `730 further discloses wherein the second portion (103’) of the at least one drain terminal includes a doped semiconductor layer (¶ [0024]).
Regarding claim 26, Hao `730 discloses the structure of claim 22, and Hao `730 further discloses wherein the second portion (103’) of the at least one drain terminal includes a conductive channel with electrons or holes (electrons since n-type ¶ [0024]).
Regarding claim 32, Hao `730 discloses the semiconductor device of claim 1, and Hao `730 further discloses a first source contact (108) extending through the aluminum gallium nitride layer (104) to a first depth; and wherein the second portion (103’) of the first drain contact extends to a second depth that is greater than the first depth (as pictured).
Regarding claim 36, Hao `730 discloses the structure of claim 22, and Hao `730 further discloses a gate structure (106, ¶ [0040]-[0041]) disposed over the aluminum gallium nitride layer (104); and wherein the second portion (103’) of the at least one drain terminal extends laterally within the gallium nitride layer (103) toward the gate structure (106) without extending under the gate structure (as pictured).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Application Publication Number 2020/0219871 A1 to Moens et al., “Moens”.
Regarding claim 2, although Moens anticipates the semiconductor device of claim 1, Moens fails to clearly state in sufficient specificity for anticipation (MPEP 2131.03) wherein the first portion of the first drain contact (322) extends between about 0.1 µm and about 10 µm into the first semiconductor layer (206).
However, Moens teaches wherein the first portion of the drain contact (322) extends through a substantial portion of the first semiconductor layer (206) and wherein the first semiconductor layer has a thickness in a range of 0.02 μm to 4 μm (20 nm to 4000 nm ¶ [0038]) which overlaps with the claimed range.
It would have been obvious before the effective filing date of the claimed invention to one having ordinary skill in the art to have formed the device of Moens with the depth of the first drain contact within the claimed range as suggested by the overlapping range of Moens since it has been held that in the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990), MPEP 2144.05, or since it has been held that “where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation.” In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955), In re Hoeschele, 406 F.2d 1403, 160 USPQ 809 (CCPA 1969), wherein in the instant case the depth of the contact is determined by the thickness of the channel layer which determines the electrical characteristics such as the operating voltages of the transistor making it a result effective variable, In re Antonie, 559 F.2d 618, 195 USPQ 6 (CCPA 1977), and MPEP 2144.05 Obviousness of Ranges II. OPTIMIZATION OF RANGES A. Optimization Within Prior Art Conditions or Through Routine Experimentation B. Only Result-Effective Variables Can Be Optimized.
Claims 22 and 33 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Application Publication Number 2020/0219871 A1 to Moens et al., “Moens”, in view of U.S. Patent Application Publication Number 2021/0202730 A1 to Hao et al., “Hao `730”.
Regarding claim 22, Moens discloses a structure (FIG. 3, alternately FIG. 5), comprising:
a gallium nitride layer (206, ¶ [0036]) disposed on a silicon substrate (102, ¶ [0031]);
an aluminum gallium nitride layer (208, ¶ [0036],[0039]) disposed on the gallium nitride layer (206), wherein a 2DEG channel (200, ¶ [0036],[0042]) is formed at an interface between the gallium nitride layer (206) and the aluminum gallium nitride layer (208);
an interlayer dielectric layer (300, ¶ [0043]) disposed on the aluminum gallium nitride layer (208);
at least one metallization layers disposed in the silicon nitride layer, the at least one metallization layers forming a drain electrode (322), a gate electrode (210, ¶ [0040]), and a source electrode (326); and at least one drain terminal coupled to the drain electrode (inherent, similar to Applicant’s use of “D” as a drain terminal), the at least one drain terminal including a first portion (322) extended through the interlayer dielectric layer (300) and aluminum gallium nitride layer (208) and into the gallium nitride layer (206) and a second portion (108) extended laterally in the gallium nitride layer (206).
Moens fails to clearly teach wherein the interlayer dielectric layer (300) is silicon nitride.
Hao `730 teaches wherein an interlayer dielectric layer (105) is silicon nitride (¶ [0036]).
It would have been obvious before the effective filing date of the claimed invention to one having ordinary skill in the art to have formed the device of Moens with the interlayer dielectric formed of silicon nitride as taught by Hao `730 in order to select a material to inhibit current collapse and prevent water vapor in the environment from eroding the device (Hao `730 ¶ [0037]).
Regarding claim 33, Moens in view of Hao `730 yields the structure of claim 22, and Moens further comprising (e.g. FIG. 5-7): a source terminal (inherent, biased to source, similar to Applicant’s “S”) coupled to the source electrode, the source terminal including a third portion (526) extended through the silicon nitride layer (300, silicon nitride when applying teachings of Hao `730 discussed above) and aluminum gallium nitride layer (208) and into the gallium nitride layer (206) and a fourth portion (e.g. 518, ¶ [0051]-[0052], including FIG. 6-7 n-type region 618, ¶ [0052]-[0054]) extended laterally in the gallium nitride layer.
Claim 30 is rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Application Publication Number 2020/0219871 A1 to Moens et al., “Moens”, in view of U.S. Patent Application Publication Number 6,329,677 B1 to Oguri et al., “Oguri”.
Regarding claim 30, although Moens discloses the semiconductor device of claim 1, Moens fails to clearly teach in sufficient detail wherein the first portion of the first drain contact (322) has a first side and an opposing second side, the second portion (108) of the first drain contact is disposed on the first side of the first portion of the first drain contact (322) without being disposed on the second side of the first portion of the first drain contact (322).
Oguri teaches wherein a first portion (“DR”, column 4 lines 10-13) of a drain contact has a first side and an opposing second side, and a second portion (“DM”, column 4 lines 24-37) of the first drain contact is disposed on the first side of the first portion of the first drain contact without being disposed on the second side of the first portion of the drain contact (as pictured).
It would have been obvious before the effective filing date of the claimed invention to one having ordinary skill in the art to have formed the device of Moens with the second portion of the drain contact only extending in towards and under the transistor’s channel as exemplified by Oguri since the second portion of the drain contact (Moens buried region 108) functions to inject holes into the channel and improve the on-state resistance (Moens ¶ [0049]) and the 2DEG channel exists on the first side of the drain contact without being disposed on the second side of the drain contact (i.e. the channel spans from the drain to the source contact). Alternately it would have been obvious before the effective filing date of the claimed invention to one having ordinary skill in the art to have formed the device of Moens with the second portion of the drain contact only extending in towards and under the transistor’s channel as taught by Oguri in order to selectively enhance the channel performance and improve the breakdown voltage (Oguri column 3 lines 7-20, column 4 lines 30-37).
Claims 34 and 35 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Application Publicatio Number 2020/0219871 A1 to Moens et al., “Moens”, in view of U.S. Patent Application Publication Number 2021/0202730 A1 to Hao et al., “Hao `730”, further in view of U.S. Patent Application Publication Number 6,329,677 B1 to Oguri et al., “Oguri”.
Regarding claim 34, although Moens in view of Hao `730 yields the structure of claim 33, Moens fails to clearly teach in sufficient detail in FIG. 5 wherein the third portion (526) of the source terminal has a first side and an opposing second side and the fourth portion (518) of the source terminal is disposed on the first side without being disposed on the second side of the third portion of the source terminal.
Oguri teaches wherein the third portion (“SR”) of the source terminal has a first side and an opposing second side and the fourth portion (“SM”) of the source terminal is disposed on the first side without being disposed on the second side of the third portion of the source terminal.
It would have been obvious before the effective filing date of the claimed invention to one having ordinary skill in the art to have formed the device of Moens with the second portion of the source contact only extending in towards and under the transistor’s channel as exemplified by Oguri since the second portion of the source contact (Moens buried region 108) functions to inject holes into the channel and improve the on-state resistance (Moens ¶ [0049]) and the 2DEG channel exists on the first side of the drain contact without being disposed on the second side of the drain contact (i.e. the channel spans from the drain to the source contact). Alternately it would have been obvious before the effective filing date of the claimed invention to one having ordinary skill in the art to have formed the device of Moens with the second portion of the drain contact only extending in towards and under the transistor’s channel as taught by Oguri in order to selectively enhance the channel performance and improve the breakdown voltage (Oguri column 3 lines 7-20, column 4 lines 30-37).
Regarding claim 35, Moens in view of Hao `730 and Oguri yields the structure of claim 34, and Moens further teaches wherein the fourth portion (e.g. region 618) of the source terminal is a doped region (¶ [0054]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
U.S. Patent Application Publication Number 2024/0097016 A1 to Fiorenza et al. teaches (e.g. Figure 2) wherein a drain electrode (226) includes a portion (236, ¶ [0046]) extending laterally into the channel layer (206);
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIC A WARD whose telephone number is (571)270-3406. The examiner can normally be reached M-F 10-6 ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Landau can be reached at (571)272-1731. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Eric A. Ward/ Primary Examiner, Art Unit 2891