DETAILED ACTION
This Office Action is in response to Applicant’s Remarks filed on 12/05/2025.
Currently, claims 1, 3-10, 16, 18-22, and 24-28 are pending in the application.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendments
Applicant' s arguments with respect to claim(s) 1, 3-10, 16, 18-22, and 24-28 have been considered but are moot because the new ground of rejection does not rely on the same combination of references applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Drawings
The drawings received on 12/05/2025 accepted.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
Claim 10 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. Claim 10 recites that the contiguous replacement gate structure comprises a polysilicon (PO) structure. ¶ [0024] of Applicant’s specification states that the disclosed subject matter may be applied to CPO (cut-dummy-poly) and CMG (cut-metal-gate) processes. The claimed “replacement gate structure” appears to refer to the CMG process rather than the CPO process because the CPO process occurs to dummy/hybrid gate structures (see ¶ [0024] of Applicant’s specification), which are formed before replacement gates. Therefore, there is insufficient support in Applicant’s written description for the claimed replacement gate structure to also be polysilicon. For the purpose of examination, this limitation will not be considered.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claim 26 and 27 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 26 and 27 recite the limitations “the dielectric structure extends into the hybrid fin…” It is unclear what these limitations mean as the dielectric structure of independent claim 1 is formed above and around the replacement gate structure before the partial etching operations that expose the top of the hybrid fin. Therefore, the claims have an indefinite scope. For the purpose of examination, these limitations will not be considered.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3, 4, 6, 8, 10, 26, and 27 are rejected under 35 U.S.C. 103 as being obvious over HUNG et al. (US Pub. No. 2020/0105613) in view of TSAI et al. (US Pub. No. 2021/0125875) and further in view of YANG et al. (US Pub. No. 2020/0135574) and further in view of JEON et al. (US Pub. No. 2019/0378903).
Regarding independent claim 1, Hung teaches a method (Figs. 1-15) comprising:
forming a substrate (Fig. 12B, 50, ¶ [0022]) containing a plurality of fins (Fig. 12B, 64B, ¶ [0056]) and a hybrid fin (Fig. 12B, 64E, ¶ [0038]) that extend vertically above the substrate, a contiguous replacement gate structure (Fig. 12B, 98, ¶ [0049]) on three sides of each of the plurality of fins and the hybrid fin, and shallow trench isolation (STI) material (Fig. 12B, 62, ¶ [0031]) disposed between the plurality of fins and the hybrid fin;
forming a dielectric structure (Fig. 12B, 124, ¶ [0063]) above and around the contiguous replacement gate structure;
forming a first opening (Fig. 12B, 137, ¶ [0064]) in the dielectric structure above the hybrid fin; and
etching a portion of the contiguous replacement gate structure underneath the first opening and above the hybrid fin to form a second opening (Fig. 13B, 141, ¶ [0066]) in the contiguous replacement gate structure with a bottom of the second opening resting on a top of the hybrid fin (¶ [0066]), the second opening having a middle critical dimension (MCD) (Fig. 13B, D2, ¶ [0066]) and a bottom critical dimension (BCD) on a top of the hybrid fin (Fig. 13B, width of opening 141 above dummy fin 64E), the second opening separating the contiguous replacement gate structure into a first replacement gate section (Fig. 13B, left portion of 98) and a second replacement gate section (Fig. 13B, right portion of 98), the etching comprising:
performing partial etching operations (¶ [0068] teaches multiple etching cycles) using a gas source comprising an etch gas (¶ [0070] teaches using an etching gas such as boron trichloride for a plasma etching process) and a dilute gas (¶ [0070] teaches using a carrier gas such as argon and helium for the plasma etching process) to cut the second opening in the contiguous replacement gate structure, wherein a polymer layer (¶ [0071] teaches a polymer byproduct is formed on sidewalls of the metal gate) forms on sidewalls of the second opening;
repeating the partial etching operations and subsequent polymer layer (¶¶ [0068]-[0071]) formation to form the second opening with the bottom of the second opening resting on the top of the hybrid fin and the MCD of the second opening being greater than the BCD on the top of the hybrid fin;
However, Hung does not explicitly teach using a gas source comprising a passivation gas.
and removing the polymer layer formed in the second opening;
wherein the second opening between the first replacement gate section and the second replacement gate section has a bottom profile with the MCD of the second opening between the first replacement gate section and the second replacement gate section at least 1.2 times the BCD on the top of the hybrid fin.
However, Tsai is a pertinent art that teaches using a gas source comprising a passivation gas (¶¶ [0042] & [0045] teaches selecting a polymer gas for Tsai’s plasma etching process. The Examiner notes that Tsai’s plasma etching process can also include the same or similar gases as Hung’s plasma etching process).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Hung’s plasma etching process to further include a polymer forming gas according to the teaching of Tsai (¶ [0045]) in order to have greater control of the shape of a gate isolation opening by influencing the rate of polymer formation (Tsai ¶¶ [0045]-[0046]).
However, Hung modified by Tsai does not explicitly teach removing the polymer layer formed in the second opening;
wherein the second opening between the first replacement gate section and the second replacement gate section has a bottom profile with the MCD of the second opening between the first replacement gate section and the second replacement gate section at least 1.2 times the BCD on the top of the hybrid fin.
However, Yang is a pertinent art that teaches removing the polymer layer (Figs. 7-8, 703, ¶¶ [0062]-[0063] teaches removing residual byproduct polymer material) formed in the second opening (Fig. 7, opening between 109a and 109b, ¶ [0057]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Hung modified by Tsai’s method to further comprise removing polymer byproduct material according to the teaching of Yang (Figs. 7-8) in order to ensure a clean surface for further processing (Yang Abstract & ¶ [0064]).
However, Hung modified by Tsai modified by Yang does not explicitly teach that the second opening between the first replacement gate section and the second replacement gate section has a bottom profile with the MCD of the second opening between the first replacement gate section and the second replacement gate section at least 1.2 times the BCD on the top of the hybrid fin.
However, Jeon is a pertinent art that recognizes that the critical dimensions of an opening impacts the volume of gate isolation that can be filled in it, which in turn impacts the insulation performance and reduces capacitance (Jeon ¶¶ [0036]-[0037] & [0089], also see Jeon Figs. 2 & 26). Jeon further recognizes the need to reduce capacitance associated with gate isolation (Jeon ¶¶ [0002] & [0036]-[0037]). Therefore, the critical dimensions of an opening filled with gate isolation is an art recognized variable. One of ordinary skill in the art would have had a reasonable expectation of success to arrive within the range of the claim 1 limitations, in order to achieve the desired balance between the impact of the volume of gate isolation on the insulation performance as well as the reduction in capacitance as taught by Jeon. MPEP 2144.05. Furthermore, the applicant has not presented persuasive evidence that the claimed widths are for a particular purpose that is critical to the overall claimed invention (i.e., that the invention would not work without the specific claimed dimensions and/or the claimed range achieves unexpected results relative to the prior art).
Regarding claim 3, Hung modified by Tsai modified by Yang modified by Jeon teaches the method of claim 1, and Hung teaches that the repeating partial etching operations comprises etching away a gate dielectric layer (Fig. 13B, 96, ¶ [0067] teaches removing portions of gate dielectric layer 96 over 64E) disposed above the hybrid fin (Fig. 12B, 64E, ¶ [0038]).
Regarding claim 4, Hung modified by Tsai modified by Yang modified by Jeon teaches the method of claim 1, and Hung teaches that the repeating partial etching operations comprises etching away a portion of a height of the hybrid fin (see Figs. 12B & 13B, at least a topmost portion of 64E is etched away).
Regarding claim 6, Hung modified by Tsai modified by Yang modified by Jeon the method of claim 1, and Hung teaches that etching the contiguous gate structure (Fig. 13B) comprises cutting two parallel contiguous gate structures (Fig. 9, ¶ [0056] teaches parallel gate structures 97B and 97C are each cut into two separate metal gates during later processing) during the etching and the second opening separates each of the two parallel contiguous gate structures into two separate portions.
Regarding claim 8, Hung modified by Tsai modified by Yang modified by Jeon teaches the method of claim 1, and Hung teaches that etching the contiguous replacement gate structure comprises cutting more than two parallel contiguous replacement gate structures (Fig. 9, ¶ [0058] teaches that more than two metal gates can be cut in later processing) during the etching and the second opening comprises a trench (Fig. 9, 55, ¶ [0058]) that separates each of the more than two parallel contiguous replacement gate structures into two separate portions.
Regarding claim 10, Hung modified by Tsai modified by Yang modified by Jeon teaches the method of claim 1 (see 112(a) rejection above).
Regarding claim 26, Hung modified by Tsai modified by Yang modified by Jeon teaches the method of claim 1 (see 112(b) rejection above).
Regarding claim 27, Hung modified by Tsai modified by Yang modified by Jeon teaches the method of claim 1 (see 112(b) rejection above).
Claims 7 and 9 are rejected under 35 U.S.C. 103 as being obvious over HUNG et al. (US Pub. No. 2020/0105613) in view of TSAI et al. (US Pub. No. 2021/0125875) and further in view of YANG et al. (US Pub. No. 2020/0135574) and further in view of JEON et al. (US Pub. No. 2019/0378903) and further in view of REZNICEK et al. (US Pub. No. 2019/0181090).
Regarding claim 7, Hung modified by Tsai modified by Yang modified by Jeon teaches the method of claim 6, and Hung teaches that each of the two parallel contiguous replacement gate structures provides a gate (Fig. 9, ¶ [0056] teaches parallel gate structures 97B and 97C) for at least two parallel fins (Fig. 9, 64B + 64C, ¶ [0056]).
However, Hung modified by Tsai modified by Yang modified by Jeon does not explicitly teach that the at least two parallel fins have a pitch between them of about 10 to 50 nm.
However, Reznicek is a pertinent art that teaches the at least two parallel fins have a pitch between them of about 10 to 50 nm (Fig. 1, 12, ¶ [0038] teaches fins with a pitch of 20nm-100nm. The range taught by Reznicek overlaps with the range claimed. “In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists. MPEP 2144.05).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Hung modified by Tsai modified by Yang modified by Jeon’s fin pitch according to the teaching of Reznicek (Fig. 1) in order to not take up too much space (Reznicek ¶ [0003]).
Regarding claim 9, Hung modified by Tsai modified by Yang modified by Jeon teaches the method of claim 8.
However, Hung modified by Tsai modified by Yang modified by Jeon does not explicitly teach that each of the more than two parallel contiguous replacement gate structures provides a gate for a fin having a fin pitch between a parallel fin of about 50 to 100 nm.
However, Reznicek is a pertinent art that teaches a fin having a fin pitch between a parallel fin of about 50 to 100 nm (Fig. 1, 12, ¶ [0038] teaches fins with a pitch of 20nm-100nm. The range taught by Reznicek overlaps with the range claimed. “In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists. MPEP 2144.05).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Hung modified by Tsai modified by Yang modified by Jeon’s fin pitch according to the teaching of Reznicek (Fig. 1) in order to not take up too much space (Reznicek ¶ [0003]).
Claim 5 is rejected under 35 U.S.C. 103 as being obvious over HUNG et al. (US Pub. No. 2020/0105613) in view of TSAI et al. (US Pub. No. 2021/0125875) and further in view of YANG et al. (US Pub. No. 2020/0135574) and further in view of JEON et al. (US Pub. No. 2019/0378903) and further in view of LIN et al. (US Pub. No. 2020/0020794).
Regarding claim 5, Hung modified by Tsai modified by Yang modified by Jeon teaches the method of claim 4.
However, Hung modified by Tsai modified by Yang modified by Jeon does not explicitly teach that the portion of the height of the hybrid fin that is etched away is greater than 3 nm.
However, Lin is a pertinent art teaches that the portion of the height of the hybrid fin that is etched away is greater than 3 nm (Fig. 3C, H3, ¶ [0029]-[0030] teaches that height of an exposed dummy fin is 3-10 nm. Fig. 4 is an alternative embodiment of Fig. 3C that teaches etching the exposed portion of the dummy fin. Therefore, the height of the exposed portion of the dummy fin that is etched in Fig. 4 is 3-10 nm. Further, Lin also teaches etching 0-20 nm of an exposed portion of a dummy fin in the embodiment of Fig. 5C (Fig. 5C, 212, ¶ [0031]). The range taught by Lin overlaps with the range claimed. “In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists. MPEP 2144.05.).
Therefore, it would have been obvious to modify Hung modified by Tsai modified by Yang modified by Jeon’s process to etch away more than 3 nm of Hung’s dummy fin according to the teaching of Lin (Figs. 3C & 4) in order to have the bottom surface of an opening be substantially plane (Lin ¶ [0030]), which would make more space available in the opening for further processing.
Claims 16 and 28 are rejected under 35 U.S.C. 103 as being obvious over HUNG et al. (US Pub. No. 2020/0105613) in view of JEON et al. (US Pub. No. 2019/0378903).
Regarding independent claim 16, Hung teaches a method comprising:
forming a semiconductor device comprising: a substrate (Fig. 12B, 50, ¶ [0022]), fin structures (Fig. 12B, 64B, ¶ [0056]) protruding in a Z- direction (see Figs. 1 & 12B) above the substrate, a hybrid fin (Fig. 12B, 64E, ¶ [0038]), shallow trench isolation (STI) material (Fig. 12B, 62, ¶ [0031]) disposed between the fin structures, a replacement gate structure (Fig. 12B, 98, ¶ [0049]) disposed above the fin structures and the STI material, and an interlayer dielectric (ILD) (Fig. 12B, 124, ¶ [0063]) structure disposed above and around the replacement gate structure;
performing lithographic operations to provide a patterned photolithographic structure (Fig. 12B, teaches forming a patterned photoresist mask above 124 and 122 to form the opening 137) above the ILD structure that exposes a region of the ILD structure above the hybrid fin to processing;
forming a first opening (Fig. 12B, 137, ¶ [0064]) in the ILD structure in the exposed region;
forming a second opening (Fig. 13B, 141, ¶ [0066]) in the replacement gate structure to separate the replacement gate structure into a first replacement gate section (Fig. 13B, left portion of 98) and a second replacement gate section (Fig. 13B, right portion of 98), wherein the second opening has a bottom that rests on a top of the hybrid fin (Fig. 13B, ¶ [0066]), wherein the second opening has a bottom critical dimension (BCD) (Fig. 13B, width of opening 141 above dummy fin 64E) that is smaller than a middle critical dimension (MCD) (Fig. 13B, D2, ¶ [0066]) of the second opening; and
forming a dielectric structure (Fig. 14B, 143, ¶ [0075]) between the first replacement gate section and the second replacement gate section by filling the second opening in the replacement gate structure with a dielectric material (¶ [0075]);
wherein the second opening between the first replacement gate section and the second replacement gate section has a bottom profile with the MCD of the second opening between the first replacement gate section and the second replacement gate section at least 1.2 times the BCD of the second opening between the first replacement gate section and the second replacement gate section.
However, Hung does not explicitly teach that the second opening between the first replacement gate section and the second replacement gate section has a bottom profile with the MCD of the second opening between the first replacement gate section and the second replacement gate section at least 1.2 times the BCD of the second opening between the first replacement gate section and the second replacement gate section.
However, Jeon is a pertinent art that recognizes that the critical dimensions of an opening impacts the volume of gate isolation that can be filled in it, which in turn impacts the insulation performance and reduces capacitance (Jeon ¶¶ [0036]-[0037] & [0089], also see Jeon Figs. 2 & 26). Jeon further recognizes the need to reduce capacitance associated with gate isolation (Jeon ¶¶ [0002] & [0036]-[0037]). Therefore, the critical dimensions of an opening filled with gate isolation is an art recognized variable. One of ordinary skill in the art would have had a reasonable expectation of success to arrive within the range of the claim 16 limitations, in order to achieve the desired balance between the impact of the volume of gate isolation on the insulation performance as well as the reduction in capacitance as taught by Jeon. MPEP 2144.05. Furthermore, the applicant has not presented persuasive evidence that the claimed widths are for a particular purpose that is critical to the overall claimed invention (i.e., that the invention would not work without the specific claimed dimensions and/or the claimed range achieves unexpected results relative to the prior art).
Regarding claim 28, Hung modified by Jeon teaches the method of claim 16, and Hung teaches that the hybrid fin (Fig. 12B, 64E, ¶ [0038]) is disposed between at least two fin structures (Fig. 12B, 64E is between 64), and the dielectric structure (Fig. 14B, 143, ¶ [0075]) extends into the hybrid fin at a distance in the Z-direction to a height that is below the height of the at least two fin structures (Fig. 14B, 143 is at least partially below the top of the fins 64).
Claims 18 and 19 are rejected under 35 U.S.C. 103 as being obvious over HUNG et al. (US Pub. No. 2020/0105613) in view of JEON et al. (US Pub. No. 2019/0378903) and further in view of TSAI et al. (US Pub. No. 2021/0125875) and further in view of YANG et al. (US Pub. No. 2020/0135574).
Regarding claim 18, Hung modified by Jeon teaches the method of claim 16, and Hung teaches that forming the second opening (Fig. 13B, 141, ¶ [0066]) in the replacement gate structure (Fig. 12B, 98, ¶ [0049]) comprises:
performing partial etching operations (¶ [0068] teaches multiple etching cycles) using a gas source comprising an etch gas (¶ [0070] teaches using an etching gas such as boron trichloride for a plasma etching process) and a dilute gas (¶ [0070] teaches using a carrier gas such as argon and helium for the plasma etching process) to cut the second opening in the replacement gate structure, wherein a polymer layer (¶ [0071] teaches a polymer byproduct is formed on sidewalls of the metal gate) forms on sidewalls of the second opening;
repeating the partial etching operations and subsequent polymer layer formation (¶¶ [0068]-[0071]) to form the second opening with the bottom of the second opening resting on the top of the hybrid fin and the MCD of the second opening being greater than the BCD of the second opening; and
However, Hung does not explicitly teach selecting a passivation gas for controlling polymer layer formation and a using gas source comprising the passivation gas, and removing the polymer layer formed in the second opening.
However, Tsai is a pertinent art that teaches selecting a passivation gas for controlling polymer layer formation and a using gas source comprising the passivation gas (¶¶ [0042] & [0045] teaches selecting a polymer gas for Tsai’s plasma etching process. The Examiner notes that Tsai’s plasma etching process can also include the same or similar gases as Hung’s plasma etching process).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Hung modified by Jeon’s plasma etching process to further include a polymer forming gas according to the teaching of Tsai (¶ [0045]) in order to have greater control of the shape of a gate isolation opening by influencing the rate of polymer formation (Tsai ¶¶ [0045]-[0046]).
However, Hung modified by Jeon modified by Tsai does not explicitly teach removing the polymer layer formed in the second opening;
However, Yang is a pertinent art that teaches removing the polymer layer (Figs. 7-8, 703, ¶¶ [0062]-[0063] teaches removing residual byproduct polymer material) formed in the second opening (Fig. 7, opening between 109a and 109b, ¶ [0057]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Hung modified by Jeon modified by Tsai’s method to further comprise removing polymer byproduct material according to the teaching of Yang (Figs. 7-8) in order to ensure a clean surface for further processing (Yang Abstract & ¶ [0064]).
Regarding claim 19, Hung modified by Jeon modified by Tsai modified by Yang teaches the method of claim 18, and Hung teaches that repeating the partial etching operations comprises:
etching away a gate dielectric layer (Fig. 13B, 96, ¶ [0067] teaches removing portions of gate dielectric layer 96 over 64E) disposed above the fin structures; and
etching away a portion of a height of the hybrid fin (see Figs. 12B & 13B, at least a topmost portion of 64E is etched away).
Claims 20 is rejected under 35 U.S.C. 103 as being obvious over HUNG et al. (US Pub. No. 2020/0105613) in view of JEON et al. (US Pub. No. 2019/0378903) and further in view of TSAI et al. (US Pub. No. 2021/0125875) and further in view of YANG et al. (US Pub. No. 2020/0135574) and further in view of LIN et al. (US Pub. No. 2020/0020794).
Regarding claim 20, Hung modified by Jeon modified by Tsai modified by Yang teaches the method of claim 19.
However, Hung modified by Jeon modified by Tsai modified by Yang does not explicitly teach that the portion of the height of the hybrid fin that is etched away is greater than 3 nm.
However, Lin is a pertinent art teaches that the portion of the height of the hybrid fin that is etched away is greater than 3 nm (Fig. 3C, H3, ¶ [0029]-[0030] teaches that height of an exposed dummy fin is 3-10 nm. Fig. 4 is an alternative embodiment of Fig. 3C that teaches etching the exposed portion of the dummy fin. Therefore, the height of the exposed portion of the dummy fin that is etched in Fig. 4 is 3-10 nm. Further, Lin also teaches etching 0-20 nm of an exposed portion of a dummy fin in the embodiment of Fig. 5C (Fig. 5C, 212, ¶ [0031]). The range taught by Lin overlaps with the range claimed. “In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists. MPEP 2144.05.).
Therefore, it would have been obvious to modify Hung modified by Tsai modified by Jeon modified by Tsai modified by Yang’s process to etch away more than 3 nm of Hung’s dummy fin according to the teaching of Lin (Figs. 3C & 4) in order to have the bottom surface of an opening be substantially plane (Lin ¶ [0030]), which would make more space available in the opening for further processing.
Claims 21, 24, and 25 are rejected under 35 U.S.C. 103 as being obvious over HUNG et al. (US Pub. No. 2020/0105613) in view of TSAI et al. (US Pub. No. 2021/0125875) and further in view of YANG et al. (US Pub. No. 2020/0135574) and further in view of LIN et al. (US Pub. No. 2020/0020794).
Regarding independent claim 21, Hung teaches a method (Figs. 1-15) comprising:
providing a semiconductor device (Fig. 12B) comprising: a substrate (Fig. 12B, 50, ¶ [0022]), a plurality of fin structures (Fig. 12B, 64B, ¶ [0056]) protruding in a Z-direction (see Figs. 1 & 12B) above the substrate, a hybrid fin (Fig. 12B, 64E, ¶ [0038]) disposed between at least two fin structures of the plurality of fin structures and extending in a Z-direction above the substrate, a replacement gate structure (Fig. 12B, 98, ¶ [0049]) disposed above the plurality of fin structures and the hybrid fin, and a dielectric layer (Fig. 13B, 96, ¶ [0067] teaches removing portions of gate dielectric layer 96 over 64E) disposed above and around the replacement gate structure;
forming a first opening (Fig. 12B, 137, ¶ [0064]) in the dielectric layer above the hybrid fin;
etching a second opening (Fig. 13B, 141, ¶ [0066]) in the replacement gate structure below the first opening that separates the replacement gate structure into a plurality of replacement gate sections (Fig. 13B, left and right portions of 98), wherein the second opening has a bottom that rests on a top of the hybrid fin (Fig. 13B, width of opening 141 above dummy fin 64E), wherein the second opening has a bottom critical dimension (BCD) (Fig. 13B, width of opening 141 above dummy fin 64E) that is smaller than a middle critical dimension (MCD) (Fig. 13B, D2, ¶ [0066]) of the second opening, the etching comprising:
performing partial etching operations (¶ [0068] teaches multiple etching cycles) using a gas source comprising an etch gas (¶ [0070] teaches using an etching gas such as boron trichloride for a plasma etching process) and a dilute gas (¶ [0070] teaches using a carrier gas such as argon and helium for the plasma etching process) to cut the second opening in the replacement gate structure, wherein a polymer layer (¶ [0071] teaches a polymer byproduct is formed on sidewalls of the metal gate) forms on sidewalls of the second opening;
repeating the partial etching operations and subsequent polymer layer formation (¶¶ [0068]-[0071]) to form the second opening with the bottom of the second opening resting on a top of the hybrid fin and the MCD of the second opening being greater than the BCD of the second opening; and
wherein the second opening has a bottom profile resulting from the etching that reduces a leakage risk between the plurality of replacement gate sections (Fig. 13B, Hung’s opening 137 has a bottom dimension that is smaller than the middle dimension in a similar manner to Applicant’s opening. Therefore, it would be obvious that Hung’s opening 137 would be capable of reducing a leakage risk between Hung’s gate sections); and
forming a dielectric structure (Fig. 14B, 143, ¶ [0075]) by filling the first opening and the second opening with a dielectric material, wherein the dielectric structure has an MCD and a BCD (Fig. 14B);
However, Hung does not explicitly teach selecting a passivation gas for controlling polymer layer formation during the etching; and a gas source comprising the passivation gas; removing the polymer layer formed in the second opening;
wherein the dielectric structure extends into the hybrid fin at a distance in the Z-direction to a height that is at least 3 nm below the height of the at least two fin structures.
However Tsai is a pertinent art that teaches selecting a passivation gas for controlling polymer layer formation and a gas source comprising the passivation gas (¶¶ [0042] & [0045] teaches selecting a polymer gas for Tsai’s plasma etching process. The Examiner notes that Tsai’s plasma etching process can also include the same or similar gases as Hung’s plasma etching process).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Hung’s plasma etching process to further include a polymer forming gas according to the teaching of Tsai (¶ [0045]) in order to have greater control of the shape of a gate isolation opening by influencing the rate of polymer formation (Tsai ¶¶ [0045]-[0046]).
However, Hung modified by Tsai does not explicitly teach removing the polymer layer formed in the second opening; and the dielectric structure extends into the hybrid fin at a distance in the Z-direction to a height that is at least 3 nm below the height of the at least two fin structures (the Examiner notes that Hung’s dielectric structure does extend below the height of the other fin structures, see Fig. 15B).
However, Yang is a pertinent art that teaches removing the polymer layer (Figs. 7-8, 703, ¶¶ [0062]-[0063] teaches removing residual byproduct polymer material) formed in the second opening (Fig. 7, opening between 109a and 109b, ¶ [0057]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Hung modified by Tsai’s method to further comprise removing polymer byproduct material according to the teaching of Yang (Figs. 7-8) in order to ensure a clean surface for further processing (Yang Abstract & ¶ [0064]).
However, Lin is a pertinent art that teaches the dielectric structure (Figs. 3C, 4 & 8C, 600, ¶ [0035]) extends into the hybrid fin (Figs. 3C, 4, & 7C, 200, ¶ [0023]) at a distance in the Z-direction to a height that is at least 3 nm below the height of the at least two fin structures (Figs. 2C & 3C, ¶ [0023] teaches a dummy fin that can be the same height as two adjacent fins 110 and 120 (¶ [0024]). Fig. 3C, H3, ¶ [0029]-[0030] teaches that height of an exposed dummy fin is 3-10 nm. Fig. 4 is an alternative embodiment of Fig. 3C that teaches etching the exposed portion of the dummy fin. Therefore, the height of the exposed portion of the dummy fin that is etched in Fig. 4 is 3-10 nm. Further, Lin also teaches etching 0-20 nm of an exposed portion of a dummy fin in the embodiment of Fig. 5C (Fig. 5C, 212, ¶ [0031]). Fig. 8C, ¶ [0035] teaches that an isolation structure can be formed in the opening 314 of Fig. 4. Therefore, isolation structure 600 can extend 3-10 nm of the dummy fin 200, which is also 3-10 nm below the height of the adjacent fins. The range taught by Lin overlaps with the range claimed. “In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists. MPEP 2144.05.).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Hung modified by Tsai modified by Yang’s method to further comprise etching a portion of dummy fin according to the teaching of Lin (Figs. 3C & 4) in order to have the bottom surface of an opening be substantially plane (Lin ¶ [0030]), which would make more space available a higher volume of isolation material during further processing (Lin Fig. 8C, ¶ [0035]).
Regarding claim 24, Hung modified by Tsai modified by Yang modified by Lin teaches the method of claim 21, and Hung teaches that etching the second opening (Fig. 13B, 141, ¶ [0066]) in the replacement gate structure comprises cutting more than two parallel contiguous replacement gate structures (Fig. 9, ¶ [0058] teaches that more than two metal gates can be cut in later processing) during the etching and the second opening comprises a trench (Fig. 9, 55, ¶ [0058]) that separates each of the more than two parallel contiguous replacement gate structures into two separate portions.
Regarding claim 25, Hung modified by Tsai modified by Yang modified by Lin teaches the method of claim 21, and Hung teaches that repeating the partial etching operations (Fig. 13B) comprises etching away a portion of a height of the hybrid fin (see Figs. 12B & 13B, at least a topmost portion of 64E is etched away).
Claims 22 is rejected under 35 U.S.C. 103 as being obvious over HUNG et al. (US Pub. No. 2020/0105613) in view of TSAI et al. (US Pub. No. 2021/0125875) and further in view of YANG et al. (US Pub. No. 2020/0135574) and further in view of LIN et al. (US Pub. No. 2020/0020794) and further in view of JEON et al. (US Pub. No. 2019/0378903).
Regarding claim 22, Hung modified by Tsai modified by Yang modified by Lin teaches the method of claim 21.
However, Hung modified by Tsai modified by Yang modified by Lin does not explicitly teach that the MCD of the dielectric structure is approximately 1.2 times the BCD of the dielectric structure.
However, Jeon is a pertinent art that recognizes that the critical dimensions of an opening impacts the volume of gate isolation that can be filled in it, which in turn impacts the insulation performance and reduces capacitance (Jeon ¶¶ [0036]-[0037] & [0089], also see Jeon Figs. 2 & 26). Jeon further recognizes the need to reduce capacitance associated with gate isolation (Jeon ¶¶ [0002] & [0036]-[0037]). Therefore, the critical dimensions of an opening filled with gate isolation is an art recognized variable. One of ordinary skill in the art would have had a reasonable expectation of success to arrive within the range of the claim 22 limitations, in order to achieve the desired balance between the impact of the volume of gate isolation on the insulation performance as well as the reduction in capacitance as taught by Jeon. MPEP 2144.05. Furthermore, the applicant has not presented persuasive evidence that the claimed widths are for a particular purpose that is critical to the overall claimed invention (i.e., that the invention would not work without the specific claimed dimensions and/or the claimed range achieves unexpected results relative to the prior art).
Cited Prior Art
The Examiner has pointed out particular references contained in the prior art of record within the body of this action for the convenience of the Applicant.
Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
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/R.P.S./
Examiner, Art Unit 2813
/KHAJA AHMAD/Primary Examiner, Art Unit 2813
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