DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The amendment filed 16 April 2026 has been entered. The terminal disclaimers filed have overcome the double patenting rejections. The amendments to the claims have overcome the 35 USC 112(b) rejections. Claims 1-20 remain pending.
Claim Construction
Regarding claim 1, the preamble is given patentable weight. Claim 12 contains the limitation “the device” in the body, which is referring to the limitations as recited in the preamble of claim 1. A skilled person in the art reading the claims would consider the claim in view of the body and preamble, and identify them limited to the technological environment of the device. The body of the claim depends on the preamble for completeness, and gives life, meaning, and vitality to this claim. Therefore, the preamble of claim 1 should be afforded patentable weight.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5, 9-10, 17-20 are rejected under 35 U.S.C. 103 as being unpatentable over US 10872038 B1 Nair et al. (hereinafter “Nair”) in view of US 20190042252 A1 Kaul et al. (hereinafter “Kaul”) in view of US 20230177321 A1 Sanchez et al. (hereinafter “Sanchez”).
Regarding claim 1, Nair teaches a device (Fig. 1 “100” co. 8 ln. 3-6), comprising:
a plurality of matrix-matrix (MM) components (Fig. 1 “101” co. 8 ln. 3-9; Fig. 2 “200” co. 9 ln. 48-53, 67; co. 10 ln. 1-15) that each include:
a plurality of map memory components (Fig. 1 “103” co. 8 ln. 6-9; Fig. 2 “203” co. 9 ln. 50-53) each configured to store (co. 8 ln. 42-46) map data (Fig. 7B “703” co. 21 ln. 42-47; co. 8 ln. 1-2),
a plurality of kernel memory components (Fig. 1 “105” co. 8 ln. 6-9; Fig. 2 “205” co. 9 ln. 50-53) each configured to store (co. 8 ln. 42-46) kernel data (Fig. 7A “701” co. 21 ln. 42-47; co. 8 ln. 1-2), and
a plurality of matrix-vector (MV) components (Fig. 1 “107” co. 8 ln. 9-10; Fig. 2 “201” co. 9 ln. 50-56) that each include a plurality of vector-vector (VV) components (Fig. 1 “111”, “121”, “131”, “141” co. 8 ln. 9-10, 17-21; Fig. 2 “211”, “221” co. 9 ln. 53-58; co. 10 ln. 5-7) that are each configured to generate a VV output (Fig. 1 output of “107” co. 8 ln. 27-30; Fig. 2 output of “201” co. 9 ln. 62-67) based on an input precision mode, an output precision mode, and an accumulation of products that is based on the map data and the kernel data (co. 7 ln. 60-67, co. 8 ln. 1-2; co. 9 ln. 10-18; co. 12, ln. 20-34),
wherein the input precision mode indicates an input word length for data input to a VV component (Fig. 1 inputs of “107” from “103” and “105” co. 8 ln. 39-42; Fig. 2 inputs of “201” from “203” and “205” co. 10 ln. 16-50),
wherein the output precision mode indicates an output word length for data output from the VV component (Fig. 1 output from “107” co. 8 ln. 28-38; Fig. 2 output from “201” co. 9 ln. 58-67), and
wherein each VV component, of the plurality of VV components included in a corresponding MV component (Fig. 1 “111”, “121”, “131”, “141” co. 8 ln. 9-10, 17-21; Fig. 2 “211”, “221” co. 9 ln. 53-58; co. 10 ln. 5-7), is coupled with each map memory component, of the plurality of map memory components (Fig. 1 output of “103” to “107” co. 8 ln. 7-18; Fig. 2 output of “203” to “201” co. 10 ln. 16-24), and is coupled with a single kernel memory component of the plurality of kernel memory components (Fig. 1 output of “105” to “107” co. 8 ln. 39-46; Fig. 2 output of “205” to “201” co. 9 ln. 59-67); and
a data distribution component (Fig. 1 “161” co. 8 ln. 3-6, 46-51) coupled with the plurality of MM components (Fig. 1 output of “161” to “107” through “103” and “105” co. 8 ln. 46-56), wherein the data distribution component comprises a plurality of multiplexers, each multiplexer of the plurality of multiplexers coupled with a respective MM component of the plurality of MM components (Fig. 1 “101” co. 8 ln. 3-9; Fig. 2 “200” co. 9 ln. 48-53, 67; co. 10 ln. 1-15), and wherein each multiplexer of the plurality of multiplexers is configured to selectively load the map data into the plurality of map memory components (co. 8 ln. 46-56) of the respective MM component (Fig. 1 “101” co. 8 ln. 3-9; Fig. 2 “200” co. 9 ln. 48-53, 67; co. 10 ln. 1-15).
Nair discloses the claimed invention except for a plurality of matrix-matrix (MM) components, a plurality of map memory components, a plurality of kernel memory components, and a plurality of matrix-vector (MV) components.
It would have been obvious to one having ordinary skill in the art at the time the invention was made to make a plurality of: matrix-matrix (MM) components, map memory components, kernel memory components, and matrix-vector (MV) components, since it has been held that mere duplication of the essential working parts of a device involves only routine skill in the art. St. Regis Paper Co. v. Bemis Co., 193 USPQ 8.
Nair is silent with disclosing based on an input precision mode, an output precision mode, wherein the input precision mode indicates an input word length, and wherein the output precision mode indicates an output word length. Further, Nair is silent with disclosing a plurality of multiplexers, and wherein each multiplexer of the plurality of multiplexers is configured to selectively.
Kaul discloses based on an input precision mode (Fig. 2A mode1b at “234”, mode4b at “236”, mode8b at “238” [0026]; Fig. 3A mode1b at “334”, mode4b OR mode8b at “336”, “338” [0029], [0032]; Fig. 4A mode1b [0032]), an output precision mode (Fig. 2B mode1b at “244” [0027]; Fig. 3B mode1b mux on lefthand side and mode1b, mode8b at “316” [0030-0031]; Fig. 4B mode [0032]), wherein the input precision mode indicates an input word length ([0024-0025], [0026] 1/2/4/8-bit modes, [0029-0030] as one example with reference to Fig. 3A, [0043]), and wherein the output precision mode indicates an output word length ([0024-0025], [0026] 1/2/4/8-bit modes, [0031] as one example with reference to Fig. 3B, [0043]).
It would have been obvious to one of ordinary skill in the art before the effective
filing date to modify Nair’s artificial intelligence circuitry with Kaul’s input and output precision modes features because they are in the claimed invention’s same field of endeavor of machine learning accelerator architecture ([0001]). Modifying with Kaul’s precision modes would be beneficial as doing so provides greater support for different bit width precisions to be selected and computed ([0029]), ranging from 1-bit, 2-bit, and 4-bit modes. Therefore, it would have been obvious to one of ordinary skill in the art to configure Nair’s artificial intelligence circuitry with Kaul’s precision modes features as making the modification would lead to more configurability of precision modes by operating in the designated mode and utilizing computing components appropriately ([0034]).
Kaul is silent with disclosing a plurality of multiplexers, and wherein each multiplexer of the plurality of multiplexers is configured to selectively.
Nair in view of Kaul is silent with disclosing a plurality of multiplexers, and wherein each multiplexer of the plurality of multiplexers is configured to selectively.
Sanchez discloses a plurality of multiplexers (Fig. 4 “408”, “402” [0123], [0127]), and wherein each multiplexer of the plurality of multiplexers is configured to selectively ([0030], [0123], [0127]).
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Nair in view of Kaul’s modified artificial intelligence circuitry with Sanchez’s multiplexer circuitry because they are in the claimed invention’s same field of endeavor of neural network accelerator architecture ([abstract]). Sanchez discloses that the multiplexers are used to selectively connect input ports to output ports ([0030]). Modifying with Sanchez’s multiplexers would have been obvious to one of ordinary skill in the art as doing so would yield significant improvements in reducing unnecessary computations by simplifying the inputs to the next processing stage ([0127]). Using Sanchez’s multiplexers to provide a predictable result in Nair in view of Kaul’s modified device before the effective filing date would have been obvious since one of ordinary skill in the art would recognize that the modified device was ready for improvement to incorporate the multiplexers and doing so would be beneficial by providing the capability of avoiding unnecessary operation executions in the device.
Regarding claim 2, the teachings addressed in the claim 1 analysis and rejection
are incorporated.
Nair is silent with disclosing an input precision mode port configured to receive a value that indicates the input precision mode; and an output precision mode port configured to receive a value that indicates the output precision mode.
Kaul discloses an input precision mode port (Fig. 2A “234”, “236”, “238” [0026]; Fig. 3A “334”, “336”, “338” [0029], [0032]; Fig. 4A mode1b multiplexer [0032]) configured to receive a value that indicates the input precision mode (Fig. 2A mode1b at “234”, mode4b at “236”, mode8b at “238” [0026]; Fig. 3A mode1b at “334”, mode4b OR mode8b at “336”, “338” [0029], [0032]; Fig. 4A mode1b [0032]); and an output precision mode port (Fig. 2B “244” [0027]; Fig. 3B mode1b mux on lefthand side, “316” [0030-0031]; Fig. 4B multiplexer [0032]) configured to receive a value that indicates the output precision mode (Fig. 2B mode1b at “244” [0027]; Fig. 3B mode1b mux on lefthand side and mode1b, mode8b at “316” [0030-0031]; Fig. 4B mode [0032]).
The motivation to combine provided with respect to claim 1 similarly applies.
Regarding claim 3, the teachings addressed in the claim 2 analysis and rejection
are incorporated.
Nair is silent with disclosing wherein the input precision mode port is a 1-bit port and the output precision mode port is a 1-bit port.
Kaul discloses wherein the input precision mode port is a 1-bit port (multiplexer selection signals of Fig. 2A mode1b at “234”, mode4b at “236”, mode8b at “238” [0026]; Fig. 3A mode1b at “334”, mode4b OR mode8b at “336”, “338” [0029], [0032]; Fig. 4A mode1b [0032]) and the output precision mode port is a 1-bit port (multiplexer selection signals of Fig. 2B mode1b at “244” [0027]; Fig. 3B mode1b mux on lefthand side and mode1b, mode8b at “316” [0030-0031]; Fig. 4B mode [0032]).
The motivation to combine provided with respect to claim 1 similarly applies.
Regarding claim 4, the teachings addressed in the claim 1 analysis and rejection
are incorporated, and Nair teaches the device of claim 1, wherein
each kernel memory component (Fig. 1 “105” co. 8 ln. 6-9; Fig. 2 “205” co. 9 ln. 50-53), of the plurality of kernel memory components, is coupled with a single VV component (Fig. 1 “111”, “121”, “131”, “141” co. 8 ln. 9-10, 17-21; Fig. 2 “211”, “221” co. 9 ln. 53-58; co. 10 ln. 5-7) per each MV component of the plurality of MV components (Fig. 1 “107” co. 8 ln. 9-10; Fig. 2 “201” co. 9 ln. 50-56).
Nair discloses the claimed invention except for a plurality of kernel memory components and a plurality of matrix-vector MV components.
It would have been obvious to one having ordinary skill in the art at the time the invention was made to make a plurality of: kernel memory components and matrix-vector MV components, since it has been held that mere duplication of the essential working parts of a device involves only routine skill in the art. St. Regis Paper Co. v. Bemis Co., 193 USPQ 8.
Regarding claim 5, the teachings addressed in the claim 1 analysis and rejection
are incorporated, and Nair teaches the device of claim 1, further comprising
a plurality of data input ports (Fig. 1 “103” connection to “161”, “105” connection to “161”; co. 8 ln. 39-64; Fig. 2 “203” incoming arrow, “205” incoming arrow; co. 9 ln. 50-67) configured to receive a corresponding plurality of input values (co. 8 ln. 39-64; co. 9 ln. 50-67); and
wherein the data distribution component (Fig. 1 “161” co. 8 ln. 3-6, 46-51) is configured to load a subset of input values, of the corresponding plurality of input values (co. 8 ln. 51-56), into the plurality of map memory components as the map data (Fig. 1 “103” co. 8 ln. 6-9; Fig. 2 “203” co. 9 ln. 50-53).
Regarding claim 9, the teachings addressed in the claim 1 analysis and rejection
are incorporated, and Nair teaches the device of claim 1, further comprising
an output port (Fig. 1 output from “107” to “151” co. 8 ln. 28-38; Fig. 2 output from “201” to “251” co. 9 ln. 62-67) configured to output processed map data to a memory (Fig. 1 “151” co. 8 ln. 28-38; Fig. 2 “251” co. 10 ln. 1-5) that is external to the plurality of MM components (Fig. 1 “101” co. 8 ln. 3-9; Fig. 2 “200” co. 9 ln. 48-53, 67; co. 10 ln. 1-15) and that is separate from the data distribution component (Fig. 1 “151” is included in “101” is not included in “161”; Fig. 2 “251” is included in “200”).
Nair discloses the claimed invention except for the plurality of MM components.
It would have been obvious to one having ordinary skill in the art at the time the invention was made to make a plurality of: MM components, since it has been held that mere duplication of the essential working parts of a device involves only routine skill in the art. St. Regis Paper Co. v. Bemis Co., 193 USPQ 8.
Nair appears to be silent to disclosing a memory that is external to the plurality of MM components.
Kaul discloses a memory that is external to (Fig. 1 “124” [0024]) the plurality of MM components.
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Nair’s artificial intelligence circuitry with Kaul’s load port and external memory features because they are in the claimed invention’s same field of endeavor of machine learning accelerator architecture ([0001]). Modifying with Kaul’s load port and external memory would be beneficial as doing so provides dedicated connectivity to load information and provides the option to retire instructions and write back results ([0024]). Therefore, it would have been obvious to one of ordinary skill in the art to configure Nair’s artificial intelligence circuitry with Kaul’s load port and external memory features as making the modification would lead to more configurability of loading data and effectively disposing instructions.
Regarding claim 10, the teachings addressed in the claim 1 analysis and rejection
are incorporated, and Nair teaches the device of claim 1, wherein
each MM component, of the plurality of MM components (Fig. 1 “101” co. 8 ln. 3-9; Fig. 2 “200” co. 9 ln. 48-53, 67; co. 10 ln. 1-15), further comprises a map data bus (Fig. 1 arrows connecting “103” to “107”; Fig. 2, arrows connecting “203” to “201”; co. 8 ln. 64-67, co. 9 ln. 1-3) configured to connect every VV component (Fig. 1 “111”, “121”, “131”, “141” co. 8 ln. 9-10, 17-21; Fig. 2 “211”, “221” co. 9 ln. 53-58; co. 10 ln. 5-7), included in that MM component, with every map memory component included in that MM component (Fig. 1 “111”, “121”, “131”, “141” included in “107” connected to “103” co. 8 ln. 9-10, 17-21; Fig. 2 “211”, “221” included in “201” connected to “203” co. 9 ln. 53-58; co. 10 ln. 5-7).
Nair discloses the claimed invention except for a plurality of MM components.
It would have been obvious to one having ordinary skill in the art at the time the invention was made to make a plurality of: MM components, since it has been held that mere duplication of the essential working parts of a device involves only routine skill in the art. St. Regis Paper Co. v. Bemis Co., 193 USPQ 8.
Claim 17 is directed to an apparatus that recites similar limitations to those recited in claim 1. The claim 1 analysis similarly applies. Additionally, claim 17 recites a system that includes a memory and a processor; and provide processed map data to at least one of the memory of the system. Nair is silent with disclosing these limitations.
However, Kaul discloses a system (Fig. 1 “100” [0024]) that includes a memory (Fig. 1 “124” [0024]) and a processor (Fig. 1 “160” [0024]); and provide processed map data to at least one of the memory of the system ([0024] dot product instruction).
It would have been obvious to one of ordinary skill in the art before the effective
filing date to modify Nair’s artificial intelligence circuitry with Kaul’s processor and memory circuitry because they are in the claimed invention’s same field of endeavor of machine learning accelerator architecture ([0001]). Modifying with Kaul’s processor and memory circuitry would have been obvious to try with predictable results as doing so provides greater support for data and instructions management ([0024]). Therefore, it would have been obvious to one of ordinary skill in the art to configure Nair’s artificial intelligence circuitry with Kaul’s processor and memory features as making the modification would lead to predictable results, programs stored in the memory and executed by the processor ([0075-0079]).
Claim 18 recites similar limitations to those recited in claim 1. The claim 1 analysis similarly applies.
Claim 19 recites similar limitations to those recited in claim 1. The claim 1 analysis similarly applies. Additionally, claim 19 recites receive load data from the memory of the system and load the load data. Nair is silent with disclosing these limitations.
However, Kaul discloses receive from the memory (Fig. 1 “124” [0024]) of the system (Fig. 1 “100” [0024]) load data and load the load data ([0024] dot product instruction indicating operands and corresponding addresses for processing).
The motivation to combine provided with respect to claim 17 similarly applies.
Claim 20 recites similar limitations to those recited in claim 2. The claim 2 analysis similarly applies.
Claims 6-8 are rejected under 35 U.S.C. 103 as being unpatentable over Nair in view of Kaul in view of Sanchez as applied to claim 1 above, and further in view of US 20180046900 A1 Dally et al. (hereinafter “Dally”) in view of US 20200134417 A1 Mohapatra et al. (hereinafter “Mohapatra”).
Regarding claim 6, the teachings addressed in the claim 5 analysis and rejection
are incorporated, and Nair teaches the device of claim 5, wherein
the plurality of data input ports (see claim 5 mapping) includes at least one of:
a load port configured to receive map data (Fig. 7B “703” co. 21 ln. 42-47; co. 8 ln. 1-2) from a memory that is external to the plurality of MM components (Fig. 1 “101” co. 8 ln. 3-9; Fig. 2 “200” co. 9 ln. 48-53, 67; co. 10 ln. 1-15),
a max pool port configured to receive max pool data generated based on a max pooling operation, or
one or more MM data input ports (Fig. 1 arrows to “103” and “105” co. 8 ln. 3-21; Fig. 2 arrows to “203” and “205” co. 10 ln. 14-50) configured to receive MM data based on output generated by an MM component of the plurality of MM components (Fig. 1 “101” co. 8 ln. 3-9; Fig. 2 “200” co. 9 ln. 48-53, 67; co. 10 ln. 1-15).
Nair discloses the claimed invention except for a plurality of MM components.
It would have been obvious to one having ordinary skill in the art at the time the invention was made to make a plurality of: MM components, since it has been held that mere duplication of the essential working parts of a device involves only routine skill in the art. St. Regis Paper Co. v. Bemis Co., 193 USPQ 8.
Further, Nair is silent with disclosing a load port configured to receive from memory that is external to the plurality of MM components; a max pool port configured to receive max pool data generated based on a max pooling operation, or one or more MM data input ports configured to receive MM data based on output generated by an MM component.
Kaul discloses a load port (Fig. 1 double arrow from “122” to “116” [0024]) configured to receive from a memory that external to (Fig. 1 “124” [0024]) the plurality of MM components.
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Nair’s artificial intelligence circuitry with Kaul’s load port and external memory features because they are in the claimed invention’s same field of endeavor of machine learning accelerator architecture ([0001]). Modifying with Kaul’s load port and external memory would be beneficial as doing so provides dedicated connectivity to load information and provides the option to retire instructions and write back results ([0024]). Therefore, it would have been obvious to one of ordinary skill in the art to configure Nair’s artificial intelligence circuitry with Kaul’s load port and external memory features as making the modification would lead to more configurability of loading data and effectively disposing instructions.
Kaul is silent with disclosing a max pool port configured to receive max pool data generated based on a max pooling operation, or one or more MM data input ports configured to receive MM data based on output generated by an MM component.
Nair in view of Kaul in view of Sanchez in view of Dally discloses, wherein Dally specifically discloses or one or more MM data input ports configured to receive MM data based on output generated by (Fig. 2A central “210” interconnections between border of “210” [0044], [0070]) an MM component.
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Nair in view of Kaul in view of Sanchez’s modified artificial intelligence circuitry with Dally’s receive features because they are in the claimed invention’s same field of endeavor of neural network accelerator architecture ([0002]). Modifying with Dally’s receiving feature would be beneficial as doing so provides more support for connectivity to send data between components ([0044]), and would result in reducing unnecessary reads and writes from memory as data can now be more easily shared between neighboring components ([0070]). Therefore, it would have been obvious to one of ordinary skill in the art to configure Nair in view of Kaul in view of Sanchez’s modified artificial intelligence circuitry with Dally’s receive features as making the modification would lead to more configurability of sharing data.
Dally is silent with disclosing a max pool port configured to receive max pool data generated based on a max pooling operation.
Nair in view of Kaul view of Sanchez in view of Dally in view of Mohapatra discloses, where Mohapatra discloses a max pool port (Fig. 6 ‘Maxpool’ arrow [0058]) configured to receive max pool data generated based on a max pooling operation (Fig. 1 “160” [0040]).
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Nair in view of Kaul in view of Sanchez in view of Dally’s modified artificial intelligence circuitry with Mohapatra’s max pool operation because they are in the claimed invention’s same field of endeavor of neural network accelerator architecture ([0001]). Mohapatra discloses that max pool operations are a common technique used in neural networks ([0070]). Modifying with Mohapatra’s max pool operation would have been obvious as the operation is a known technique in the art, and would also be beneficial since performing max pool operations prunes the size of feature maps ([0070]).
Regarding claim 7, the teachings addressed in the claim 1 analysis and rejection are incorporated, and Nair teaches the device of claim 1, further comprising
a coordination mode port configured to receive a value that indicates whether outputs from different MM components, of the plurality of MM components (Fig. 1 “101” co. 8 ln. 3-9; Fig. 2 “200” co. 9 ln. 48-53, 67; co. 10 ln. 1-15), are to be combined.
Nair discloses the claimed invention except for a plurality of MM components.
It would have been obvious to one having ordinary skill in the art at the time the invention was made to make a plurality of: MM components, since it has been held that mere duplication of the essential working parts of a device involves only routine skill in the art. St. Regis Paper Co. v. Bemis Co., 193 USPQ 8.
Nair is silent with disclosing a coordination mode port configured to receive a value that indicates whether outputs from different MM components, of the plurality of MM components, are to be combined.
Kaul is silent with disclosing a coordination mode port configured to receive a value that indicates whether outputs from different MM components, of the plurality of MM components are to be combined.
Nair in view of Kaul view of Sanchez in view of Dally discloses, where Dally discloses a coordination mode port (Fig. 3C “366” in the scatter accumulator which includes “335” and “368”, [0097]) configured to receive a value that indicates whether outputs from different MM components, of the plurality of MM components are to be combined ([0050] scatter accumulator; Fig. 3C output signals from “365” inputted to “366” [0097-0099]).
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Nair in view of Kaul in view of Sanchez’s modified artificial intelligence circuitry with Dally’s coordination mode features because they are in the claimed invention’s same field of endeavor of neural network accelerator architecture ([0002]). Modifying with Dally’s coordination mode feature would be beneficial as doing so provides more support for connectivity to send data between components ([0050]). Therefore, it would have been obvious to one of ordinary skill in the art to configure Nair in view of Kaul in view of Sanchez’s modified artificial intelligence circuitry with Dally’s receive features as making the modification would lead to more configurability of sharing data.
Regarding claim 8, the teachings addressed in the claim 7 analysis and rejection are incorporated, and Nair in view of Kaul in view of Sanchez in view of Dally teaches the device of claim 7, wherein the coordination mode port (see claim 7 mapping).
Dally further teaches the coordination mode port is a 1-bit port (Fig. 3C gr[i][j] [0099]).
The motivation to combine provided with respect to claim 7 similarly applies.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Nair in view of Kaul in view of Sanchez as applied to claim 1 above, and further in view of US 20210124794 A1 Nair et al. (hereinafter “Nair’794”).
Regarding claim 11, the teachings addressed in the claim 1 analysis and rejection are incorporated, and Nair teaches the device of claim 1, wherein
each MM component, of the plurality of MM components (Fig. 1 “101” co. 8 ln. 3-9; Fig. 2 “200” co. 9 ln. 48-53, 67; co. 10 ln. 1-15), further comprises a plurality of kernel data buses (Fig. 1 arrows connecting “105” to “107”; Fig. 2, arrows connecting “205” to “201”; co. 8 ln. 64-67, co. 9 ln. 1-3) each configured to connect an individual VV component (Fig. 1 “111”, “121”, “131”, “141” co. 8 ln. 9-10, 17-21; Fig. 2 “211”, “221” co. 9 ln. 53-58; co. 10 ln. 5-7), included in a particular MV component of the plurality of MV components (Fig. 1 “107” co. 8 ln. 9-10; Fig. 2 “201” co. 9 ln. 50-56), with a corresponding individual kernel memory component, of the plurality of kernel memory components, such that each individual VV component, included in the particular MV component, is connected to a different kernel memory component of the plurality of kernel memory components (Fig. 1 “105” co. 8 ln. 6-9; Fig. 2 “205” co. 9 ln. 50-53).
Nair discloses the claimed invention except for a plurality of MM components and a plurality of MV components.
It would have been obvious to one having ordinary skill in the art at the time the invention was made to make a plurality of: MM components and MV components, since it has been held that mere duplication of the essential working parts of a device involves only routine skill in the art. St. Regis Paper Co. v. Bemis Co., 193 USPQ 8.
Nair is silent with disclosing a corresponding individual kernel memory component where each individual VV component is connected to a different kernel memory component.
Further, Kaul is silent with disclosing a corresponding individual kernel memory component where each individual VV component is connected to a different kernel memory component.
Nair in view of Kaul in view of Sanchez in view of Nair’794 discloses, where Nair’794 teaches a corresponding individual kernel memory component (Fig. 2A “207” “209” [0028]) where each individual VV component is connected to a different (Fig. 2A “207” connected to “211” and “209” connected to “221” [0029]) kernel memory component.
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Nair in view of Kaul in view of Sanchez’s modified artificial intelligence circuitry with Nair’794 corresponding connection features because they are in the claimed invention’s same field of endeavor of artificial intelligence accelerator architecture ([0022]). Modifying with Nair’794’s corresponding connection feature would be beneficial as doing so provides more support for parallelization of components and computations ([0029]). Therefore, it would have been obvious to one of ordinary skill in the art to configure Nair in view of Kaul in view of Sanchez’s modified artificial intelligence circuitry with Nair’794’s corresponding connection features as making the modification would lead to more configurability of parallelization of operations and thus yield in more efficient computations.
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Nair in view of Kaul in view of Sanchez as applied to claim 1 above, and further in view of Vitez, Marko. “Micron AI Solutions”. Partner talk: Micron DLA. CERN openlab Technical Workshop. Jan 22-23, 2020. (hereinafter “Vitez”).
Regarding claim 12, the teachings addressed in the claim 1 analysis and rejection are incorporated, and Nair teaches the device of claim 1, wherein
the device includes four MM components, four map memory components per MM component, four kernel memory components per MM component, four MV components per MM component, and four VV components per MV component (see claim 1 mapping).
While Nair teaches the particular components of the device, they are silent with disclosing the particular quantities of each component based on the other components.
Kaul is silent with disclosing the particular quantities of each component based on the other components.
Nair in view of Kaul in view of Sanchez in view of Vitez discloses, where Vitez discloses four MM components (Pg. 24 4 MM), four map memory components per MM component (Pg. 22-23 Maps Bank 0-3), four kernel memory components per MM component (Pg. 22-23 Kernel Buffer [four square copies and line per square]), four MV components per MM component (Pg. 22-23 combination of VV Unit [four square copies and line per square] and Kernel Buffer [four square copies and line per square] as one MV unit is illustrated in Pg. 21), and four VV components per MV component (Pg. 21 four VV Unit).
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Nair in view of Kaul in view of Sanchez’s modified artificial intelligence circuitry with Vitez’s particular quantities features because they are in the claimed invention’s same field of endeavor of artificial intelligence accelerator architecture (Pg. 5). Modifying with Vitez’s particular quantities feature would be beneficial as doing so provides good performance per power, efficient use of memory bandwidth, and low latency (Pg. 7). Therefore, it would have been obvious to one of ordinary skill in the art to configure Nair in view of Kaul in view of Sanchez’s modified artificial intelligence circuitry with Vitez’s particular quantities features as making the modification would lead to the purported benefits.
Claims 13 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Nair in view of Kaul in view of Sanchez as applied to claim 1 above, and further in view of US 20210182024 A1 Mueller et al. (hereinafter “Mueller”) in view of US 20190339944 A1 Olsen (hereinafter “Olsen”).
Claim 13 is directed to a method that would be performed by the apparatus of claim 1 and 9. The claim 1 and 9 analysis similarly applies. In addition, claim 13 recites the following: an integrated circuit, an accumulation of products based on the input precision mode, generating, using the integrated circuit, a first rounded output, and generating, using the integrated circuit, a second rounded output based on the first rounded output and an activation function.
Nair in view of Kaul discloses an integrated circuit (Kaul, [0076]), and an accumulation of products (Nair, co. 7 ln. 60-67, co. 8 ln. 1-2; co. 9 ln. 10-18; co. 12, ln. 20-34) based on the input precision mode (Kaul, Fig. 2A mode1b at “234”, mode4b at “236”, mode8b at “238” [0026]; Fig. 3A mode1b at “334”, mode4b OR mode8b at “336”, “338” [0029], [0032]; Fig. 4A mode1b [0032]).
It would have been obvious to one of ordinary skill in the art before the effective
filing date to modify Nair’s artificial intelligence circuitry with Kaul’s basing features and integrated circuitry features because they are in the claimed invention’s same field of endeavor of machine learning accelerator architecture ([0001]). Modifying with Kaul’s basing features would be beneficial as doing so provides consistent sizing of bit widths prior to the accumulation ([0026]), and thus reducing possible inconsistencies with bit sizing. Therefore, it would have been obvious to one of ordinary skill in the art to configure Nair’s artificial intelligence circuitry with Kaul’s basing features as making the modification would lead to more configurability of consistent bit width sizing. Modifying with Kaul’s integrated circuitry would have been obvious to try with predictable results as doing so provides greater support for data and instructions management ([0076-0077]). Therefore, it would have been obvious to one of ordinary skill in the art to configure Nair’s artificial intelligence circuitry with Kaul’s integrated circuitry features as making the modification would lead to predictable results, executing in the processor ([0075-0079]).
Nair in view of Kaul are silent with disclosing generating, using the integrated circuit, a first rounded output, and generating, using the integrated circuit, a second rounded output based on the first rounded output and an activation function.
Nair in view of Kaul in view of Sanchez in view of Mueller discloses, where Mueller discloses generating, using the integrated circuit, a first rounded output (Fig. 1 “103” output [0029], [0032-0033]), and generating, using the integrated circuit, a second rounded output (Fig. 1 “104” output [0029], [0032-0033]) based on the first rounded output (Fig. 1 “103” output is input into “104” [0029], [0032-0033]) and an activation function.
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Nair in view of Kaul in view of Sanchez’s modified artificial intelligence circuitry with Mueller’s rounded features because they are in the claimed invention’s same field of endeavor of neural network accelerator architecture ([0005]). Modifying with Mueller’s rounded features would be beneficial as doing so yields at least improvements in throughput and latency ([0029]). Therefore, it would have been obvious to one of ordinary skill in the art to configure Nair in view of Kaul in view of Sanchez’s modified artificial intelligence circuitry with Mueller’s rounded features as making the modification would lead to the purported benefits.
Nair in view of Kaul in view of Sanchez in view of Mueller are silent with disclosing an activation function.
Olsen discloses an activation function ([0005-0006]).
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Nair in view of Kaul in view of Sanchez in view of Mueller’s modified artificial intelligence circuitry with Olsen’s activation function because they are in the claimed invention’s same field of endeavor of neural network accelerator architecture ([0095]). Olsen discloses that activation functions are a common technique used in neural networks ([0005-0006]). Modifying with Olsen’s activation function would have been obvious as activation functions are a known technique in the art, and would also be beneficial since performing activation functions assists with neural network training ([0006]).
Regarding claim 15, the teachings addressed in the claim 13 analysis and rejection are incorporated, and Nair in view of Kaul in view of Sanchez in view of Mueller teaches the device of claim 13, further comprising
formatting (Mueller, [0034-0035] IEEE format precisions) the second rounded output (Mueller, Fig. 1 “104” output [0029], [0032-0033]) based on a least one of the output precision mode (Kaul, Fig. 2B mode1b at “244” [0027]; Fig. 3B mode1b mux on lefthand side and mode1b, mode8b at “316” [0030-0031]; Fig. 4B mode [0032]) or a coordination mode that indicates whether the accumulation of products is to be combined with one or more other accumulations of products prior to rounding (NOTE: the logical OR in the claim limitation is interpreted to be fully disclosed by the prior art as at least one of the conditions is met, the output precision mode).
The motivation to combine provided with respect to claim 13 similarly applies.
Claims 14 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Nair in view of Kaul in view of Sanchez in view of Mueller in view of Olsen as applied to claim 13 above, and further in view of Dally.
Claim 14 is directed to a method that would be performed by the apparatus of claim 7. The claim 7 analysis similarly applies. In addition, claim 14 recites the following: combining prior to rounding; and wherein the first rounded output is generated based on the coordination mode. Nair in view of Kaul in view of Sanchez in view of Mueller in view of Olsen discloses combining prior to rounding (Mueller, [0029]). The motivation to combine provided with respect to claim 13 similarly applies.
Nair in view of Kaul in view of Sanchez in view of Mueller in view of Olsen in view of Dally discloses wherein the first rounded output is generated based on the coordination mode (Dally, Fig. 3C “366” in the scatter accumulator which includes “335” and “368”, [0097]).
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Nair in view of Kaul in view of Sanchez in view of Mueller in view of Olsen’s modified artificial intelligence circuitry with Dally’s coordination mode features because they are in the claimed invention’s same field of endeavor of neural network accelerator architecture ([0002]). Modifying with Dally’s coordination mode feature would be beneficial as doing so provides more support for connectivity to send data between components ([0050]). Therefore, it would have been obvious to one of ordinary skill in the art to configure Nair in view of Kaul in view of Sanchez in view of Mueller in view of Olsen’s modified artificial intelligence circuitry with Dally’s coordination mode features as making the modification would lead to more configurability of sharing data.
Claim 16 is directed to a method that would be performed by the apparatus of claims 1 and 9. The claims 1 and 9 analysis similarly applies. In addition, claim 16 recites the following: generating the processed map data based on the second rounded output; and routing the processed map data to a multiplexer, of a plurality of multiplexers, based on a coordination mode, and loaded based on selection by the multiplexer.
Nair in view of Kaul in view of Sanchez in view of Mueller in view of Olsen in view of Dally discloses generating the processed map data (Nair, Fig. 1 “151” co. 8 ln. 28-38; Fig. 2 “251” co. 10 ln. 1-5) based on the second rounded output (Mueller, Fig. 1 “104” output [0029], [0032-0033]); based on the coordination mode (Dally, Fig. 3C “366” in the scatter accumulator which includes “335” and “368”, [0097]). The motivation to combine provided with respect to claim 14 similarly applies.
Sanchez discloses routing the processed map data to a multiplexer, of the plurality of multiplexers (Fig. 4 “408”, “402” [0123], [0127]).
The motivation to combine provided with respect to claim 1 similarly applies.
Response to Arguments
Notice of References Cited. Examiner has included the references in the PTO-892.
Double Patenting. The rejections have been withdrawn based on the filing of the Terminal Disclaimers.
35 USC 112(b). The rejections have been withdrawn due to the amendment to the claims.
35 USC 103. Applicant’s arguments, see Remarks p. 12, filed 04/16/2026, with respect to the rejection(s) of claim(s) 1-20 under 35 USC 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Sanchez, as necessitated by the amendment.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/MARKUS ANTHONY VILLANUEVA/Examiner, Art Unit 2151
/James Trujillo/Supervisory Patent Examiner, Art Unit 2151
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