DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Regarding Applicant’s argument about the prior art rejections of Claims 1 – 12 & 14 – 24 on page 10 of the response filed on 9 December 2025, the Examiner has considered Applicant’s argument but said arguments are moot because they do not apply to the new grounds of rejection presented in this Office Action, necessitated by Applicant’s amendment.
Claims 13 & 25 remain withdrawn.
IDS
Applicant’s IDSs submitted on:
20 June 2022;
22 September 2023;
23 February 2024;
12 July 2024;
24 June 2025; and
19 January 2026
have been considered by the Examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 1 – 24 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding Claim 1:
Lin. 6, the limitation “the plurality of lower channel layers of the channels of the plurality of lower transistors” is cited, however “channels” has an insufficient antecedent basis. For the purposes of examination, this limitation will be interpreted as “the plurality of lower channel layers of the plurality of lower transistors”.
Lin. 8, the limitation “bottom transistors” is cited without a sufficient antecedent basis. For the purposes of examination, this limitation will be interpreted as “the plurality of lower transistors”.
Regarding Claims 2 – 13,
These claims are dependent upon Claim 1.
Regarding Claim 3,
Lin. 2 – 3, the limitation “plurality of channels of an upper transistor of the plurality of upper transistors” is cited without a sufficient antecedent basis. For the purposes of examination, this limitation will be interpreted as “the plurality of the upper channel layers of the upper transistor”.
Regarding Claims 4 – 8,
These claims are dependent upon Claim 3.
Regarding Claim 5,
Lin. 2, the limitation “the channels of the lower transistor” is cited without a sufficient antecedent basis. For the purposes of examination, this limitation will be interpreted as “the plurality of the lower channel layers of a lower transistor”.
Regarding Claims 6 – 8,
These claims are dependent upon Claim 5.
Regarding Claim 6,
Lin. 2, the limitation “the channels of the upper transistor” is cited without a sufficient antecedent basis. For the purposes of examination, this limitation will be interpreted as “the plurality of the upper channel layers of the upper transistor”.
Regarding Claims 7 – 8,
These claims are dependent upon Claim 6.
Regarding Claim 7,
Lin. 4, the limitation “the channels of the lower transistor” is cited without a sufficient antecedent basis. For the purposes of examination, this limitation will be interpreted as “the plurality of the lower channel layers of the lower transistor”.
Lin. 5, the limitation “the channels of the upper transistor” is cited without a sufficient antecedent basis. For the purposes of examination, this limitation will be interpreted as “the plurality of the upper channel layers of the upper transistor”.
Regarding Claim 14,
Lin. 5 – 6, the limitation “channels the plurality of lower channel layers of the plurality of lower transistors” is cited without a sufficient antecedent basis. For the purposes of examination, this limitation will be interpreted as “the plurality of the lower channel layers of the plurality of lower transistors”.
Lin. 8, the limitation “bottom transistors” is cited without a sufficient antecedent basis. For the purposes of examination, this limitation will be interpreted as “the plurality of the lower transistors”.
Lin. 10, the limitation “the channels” is cited without a sufficient antecedent basis. For the purposes of examination, this limitation will be interpreted as “the lower channel layers”.
Regarding Claims 15 – 21,
These claims are dependent upon Claim 14.
Regarding Claim 15,
Lin. 2, the limitation “the plurality of channels” is cited without a sufficient antecedent basis. For the purposes of examination, this limitation will be interpreted as “the plurality of upper channel layers”.
Regarding Claims 16 – 21,
These claims are dependent upon Claim 15.
Regarding Claim 16,
Lin. 2 – 3, the limitation “the plurality of channels of an upper transistor of the plurality of upper transistors” is cited without a sufficient antecedent basis. For the purposes of examination, this limitation will be interpreted as “the plurality of channel layers of the upper transistor”.
Regarding Claims 17 – 21,
These claims are dependent upon Claim 16.
Regarding Claim 21,
Lin. 2, the limitation “the channels” is cited without a sufficient antecedent basis. For the purposes of examination, this limitation will be interpreted as “the upper channel layers”.
Regarding Claim 22,
Lin. 7, the limitation “the channels” is cited without a sufficient antecedent basis. For the purposes of examination, this limitation will be interpreted as “the lower channel layers”.
Lin. 9, the limitation “the channels” is cited without a sufficient antecedent basis. For the purposes of examination, this limitation will be interpreted as “the upper channel layers”.
Lin. 15, the limitation “the channels of a second upper transistor” is cited without a sufficient antecedent basis. For the purposes of examination, this limitation will be interpreted as “the upper channel layers of the second upper transistor”.
Regarding Claim 23,
Lin. 12, the limitation “the channels” is cited without a sufficient antecedent basis. For the purposes of examination, this limitation will be interpreted as “the lower channel layers”.
Regarding Claim 24,
This claim is dependent upon Claim 23.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1 – 9 & 14 – 22 are rejected under 35 U.S.C. 102(a)(1) and 35 U.S.C. 102(a)(2) as being anticipated by SMITH (US 20190172828 A1).
Regarding Claim 1,
SMITH discloses:
A microelectronic structure (Fig. 4: 400; Par. 54) comprising:
a plurality of lower transistors (Fig. 4: 33/23 and 32/22; Par. 54 – 55) and a plurality of upper transistors (Fig. 4: 35/25 and 34/24; Par. 54 – 55),
wherein each of the plurality of upper transistors includes a plurality of upper channel layers (Fig. 4: 35/25 includes 25 and 34/24 includes 24),
wherein each of the plurality of lower transistors includes a plurality of lower channel layers (Fig. 4: 33/23 includes 23 and 32/22 includes 22),
wherein the plurality of upper channel layers of the plurality of upper transistors are staggered from the plurality of lower channel layers of the plurality of lower transistors;
(Fig. 4: 25 of 35/25 is staggered from 22 of 32/22 and 24 of 34/24 is staggered from 23 of 33/23. Therefore, 25 and 24 of 35/25 and 34/24 are staggered from 22 and 23 of 32/22 and 33/23.)
and a lower dielectric gate cut (Fig. 4: trench 1330 filled with dielectric 1410, hereinafter denoted LDGC; Par. 54) located beneath an upper transistor (Fig. 4: LDGC is—indirectly—beneath 35/25),
wherein the lower dielectric gate cut separates the plurality of lower transistors,
(Fig. 4: LDGC separates 33/23 and 32/22)
wherein the lower dielectric gate cut is vertically aligned with the plurality of upper channel layers of the upper transistor.
(Fig. 4: LDGC extends in the vertical direction. The stacking of 25 of 35/25 also extends in the vertical direction. Therefore, the LDGC is vertically aligned with 25 of 35/25.)
Regarding Claim 2,
SMITH discloses:
The microelectronic structure of claim 1, further comprising:
a bonding oxide (Fig. 4: the horizontal portion of 1410 between 2230(3) and 2230(2), which may be comprised of silicon oxide—Par. 85—and is hereinafter denoted BO) located between the plurality of the upper channel layers of the upper transistor and the lower dielectric gate cut.
(Fig. 4: BO is located between 25 of 35/25 and the LDGC.)
Regarding Claim 3,
SMITH discloses:
The microelectronic structure of claim 2, further comprising:
an upper dielectric gate cut (Fig. 4: trench 1720(3) filled with dielectric 1410, hereinafter denoted UDGC; Par. 54) located adjacent to the plurality of the upper channel layers of the upper transistor,
(Fig. 4: UDGC is located adjacent to 25 of 35/25 of 35/25 and 34/24.)
wherein the upper dielectric gate cut separates the each of the plurality of upper transistors.
(Fig. 4: the UDGC separates 35/25 and 34/24.)
Regarding Claim 4,
SMITH discloses:
The microelectronic structure of claim 3,
wherein a portion of the upper dielectric gate cut is adjacent to the bonding oxide.
(Fig. 4: the lower portion of the UDGC is adjacent to BO.)
Regarding Claim 5,
SMITH discloses:
The microelectronic structure of claim 4, further comprising:
a first gate (Fig. 4: 33; Par. 55) surrounds the plurality of lower channel layers of a lower transistor.
(Fig. 4: 33 surrounds 23 of 33/23.)
Regarding Claim 6,
SMITH discloses:
The microelectronic structure of claim 5, further comprising:
a second gate (Fig. 4: 35; Par. 55) surrounds the plurality of upper channel layers of the upper transistor.
(Fig. 4: 35 surrounds 25 of 35/25.)
Regarding Claim 7,
SMITH discloses:
The microelectronic structure of claim 6, further comprising:
a gate connection (Fig. 4: the capacitive coupling between 33 and 35 through 1410, hereinafter denoted GC) located adjacent to the bonding oxide,
(Fig. 4: GC includes portions of BO between 33 and 35, and GC is also is located adjacent to other portions of BO.)
wherein the gate connection is connected to the first gate and the second gate,
(Fig. 4: GC is connected to 33 and 35.)
wherein the combination of the first gate, the second gate, the gate connection forms a shared gate (Fig. 4: 33/GC/35) between the plurality of lower channel layers of the lower transistor and the plurality of upper channel layers of the upper transistor.
(Fig. 4: The combination of 33, 35, and GC forms 33/GC/35 between 23 of 33/23 and 25 of 35/25.)
Regarding Claim 8,
SMITH discloses:
The microelectronic structure of claim 6,
wherein the second gate is located between the upper channel layers of the upper transistor and the upper dielectric gate cut.
(Fig. 4: 35 is located between 25 of 35/25 and the UDGC.)
Regarding Claim 9,
SMITH discloses:
The microelectronic structure of claim 1, further comprising:
a bottom dielectric layer (Fig. 4: 14; Par. 62) located beneath a channel region (Fig. 4: 19(1); Par. 58) of the lower transistors.
(Fig. 4: 14 is located beneath 19(1) of 33/23 and 32/22.)
Regarding Claim 14,
SMITH discloses:
A microelectronic structure (Fig. 4: 400; Par. 54) comprising:
a plurality of lower transistors (Fig. 4: 33/23 and 32/22; Par. 54 – 55) and a plurality of upper transistors (Fig. 4: 35/25 and 34/24; Par. 54 – 55),
wherein each of the plurality of upper transistors includes a plurality of upper channel layers (Fig. 4: 35/25 includes 25 and 34/24 includes 24),
wherein each of the plurality of lower transistors includes a plurality of lower channel layers (Fig. 4: 33/23 includes 23 and 32/22 includes 22),
wherein the plurality of upper channel layers of the plurality of upper transistors are staggered from the plurality of lower channel layers of the plurality of lower transistors;
(Fig. 4: 25 of 35/25 is staggered from 22 of 32/22 and 24 of 34/24 is staggered from 23 of 33/23. Therefore, 25 and 24 of 35/25 and 34/24 are staggered from 22 and 23 of 32/22 and 33/23.)
a lower dielectric gate cut (Fig. 4: trench 1330 filled with dielectric 1410, hereinafter denoted LDGC; Par. 54) located beneath an upper transistor (Fig. 4: LDGC is—indirectly—beneath 35/25),
wherein the lower dielectric gate cut separates the plurality of lower transistors,
(Fig. 4: LDGC separates 33/23 and 32/22)
wherein the lower dielectric gate cut is vertically aligned with the plurality of upper channel layers of the upper transistor;
(Fig. 4: LDGC extends in the vertical direction. The stacking of 25 of 35/25 also extends in the vertical direction. Therefore, the LDGC is vertically aligned with 25 of 35/25.)
and an independent gate (Fig. 4: 33/2230(3), which is independent as it has only one associated routing track 2220(3)) surrounding the lower channel layers of a first lower transistor (Fig. 4: 33/23),
(Fig. 4: 33 of 33/2230(3) surrounds 23 of 33/23)
wherein the independent gate is isolated from the other lower transistors and upper transistors.
(Fig. 4: 33/2230(3) is isolated—via 1410—from 32/22, 35/25, and 34/24)
Regarding Claim 15,
SMITH discloses:
The microelectronic structure of claim 14, further comprising:
a bonding oxide (Fig. 4: the horizontal portion of 1410 between 2230(3) and 2230(2), which may be comprised of silicon oxide—Par. 85—and is hereinafter denoted BO) located between the plurality of upper channel layers of the upper transistor and the lower dielectric gate cut.
(Fig. 4: BO is located between 25 of 35/25 and the LDGC.)
Regarding Claim 16,
SMITH discloses:
The microelectronic structure of claim 15, further comprising:
an upper dielectric gate cut (Fig. 4: trench 1720(3) filled with dielectric 1410, hereinafter denoted UDGC; Par. 54) located adjacent to the plurality of channel layers of the upper transistor, wherein the upper dielectric gate cut separates the upper transistors.
(Fig. 4: UDGC is located adjacent to 25 of 35/25, wherein the UDGC separates 35/25 and 34/24.)
Regarding Claim 17,
SMITH discloses:
The microelectronic structure of claim 16,
wherein a first pair of upper dielectric gate cuts (Fig. 5: UDGC and the portion of 1410 to the left of 33/23 and 2230(3), where the latter is hereinafter denoted UDGC2 and the combination is hereinafter denoted UDGC/UDGC2) are located above the first lower transistor.
(Fig. 4: UDGC/UDGC2 is located above 33/23.)
Regarding Claim 18,
SMITH discloses:
The microelectronic structure of claim 17,
wherein the independent gate extends between the first pair of upper dielectric gate cuts.
(Fig. 5: 2230(3) of 33/2230(3) extends between UDGC/UDGC2.)
Regarding Claim 19,
SMITH discloses:
The microelectronic structure of claim 18,
wherein a portion of the upper dielectric gate cut is adjacent to the bonding oxide.
(Fig. 5: the lower portion of UDGC is adjacent to BO.)
Regarding Claim 20,
SMITH discloses:
The microelectronic structure of claim 19,
wherein a first upper transistor (Fig. 4: also 35/25) is located between a first upper dielectric gate cut (Fig. 4: also UDGC) and a second upper dielectric gate cut (Fig. 4: UDGC2),
(Fig. 4: 35/25 is located between UDGC and UDGC2)
wherein the first upper dielectric gate cut is one of the dielectric gate cuts included in the pair of upper dielectric gate cuts.
(Fig. 4: UDGC is one of the dielectric gate cuts included in UDGC/UDGC2.)
Regarding Claim 21,
SMITH discloses:
The microelectronic structure of claim 20, further comprising:
a second independent gate (Fig. 4: 35/2230(5), which is independent as it has only one associated routing track 2220(5)) surrounding the upper channel layers of the first upper transistor,
(Fig. 4: 35/2230(5) surrounds 25 of 35/25)
wherein the second independent gate is isolated from the other lower transistors and upper transistors.
(Fig. 4: 35/2230(5) is isolated—via 1410—from 33/23, 32/22, and 34/24)
Regarding Claim 22,
SMITH discloses:
A microelectronic structure (Fig. 4: 400; Par. 54) comprising:
a plurality of lower transistors (Fig. 4: 33/23 and 32/22; Par. 54 – 55) and a plurality of upper transistors (Fig. 4: 35/25 and 34/24; Par. 54 – 55),
wherein each of the plurality of upper transistors includes a plurality of upper channel layers (Fig. 4: 35/25 includes 25 and 34/24 includes 24),
wherein each of the plurality of lower transistors includes a plurality of lower channel layers (Fig. 4: 33/23 includes 23 and 32/22 includes 22),
wherein the plurality of upper channel layers of the plurality of upper transistors are staggered from the plurality of lower channel layers of the plurality of lower transistors;
(Fig. 4: 25 of 35/25 is staggered from 22 of 32/22 and 24 of 34/24 is staggered from 23 of 33/23. Therefore, 25 and 24 of 35/25 and 34/24 are staggered from 22 and 23 of 32/22 and 33/23.)
a first independent gate (Fig. 4: 33/2230(3), which is independent as it has only one associated routing track 2220(3)) surrounding the lower channel layers of a first lower transistor (Fig. 4: 33/23),
(Fig. 4: 33 of 33/2230(3) surrounds 23 of 33/23)
wherein the first independent gate is isolated from the other lower transistors and upper transistors;
(Fig. 4: 33/2230(3) is isolated—via 1410—from 32/22, 35/25, and 34/24)
a second independent gate (Fig. 4: 35/2230(5), which is independent as it has only one associated routing track 2220(5)) surrounding the upper channel layers of a first upper transistor (Fig. 4: 35/25),
(Fig. 4: 35/2230(5) surrounds 25 of 35/25)
wherein the second independent gate is isolated from the other lower transistor and the upper transistors;
(Fig. 4: 35/2230(5) is isolated—via 1410—from 32/22, 33/23, and 34/24)
and a shared gate (Fig. 4: 32/GC/34, similar to the shared gate of Claim 7) surrounding the plurality of lower channel layers of a second lower transistor (Fig. 4: 32/22) and the plurality of upper channel layers of a second upper transistor (Fig. 4: 34/24),
(Fig. 4: 32/GC/34 surrounds 22 of 32/22 and 24 of 34/24)
wherein the shared gate includes a gate connection (Fig. 4: the capacitive coupling between 32 and 34 through 1410, hereinafter denoted GC) that connects the shared gate located around the second lower transistor and the upper channel layers of the second upper transistor,
(Fig. 4: 32/GC/34 includes GC that connects 32/GC/34 located around 22 of 32/22 and 24 of 34/24.)
wherein the gate connection extends through a bonding oxide layer (Fig. 4: the horizontal portion of 1410 between 2230(3) and 2230(2), which may be comprised of silicon oxide—Par. 85—and is hereinafter denoted BO) and the gate connection is vertically aligned the plurality of lower channel layers of the second lower transistor.
(Fig. 4: GC extends through BO. Further, the portion of GC between the upper surface of 32 and the lower surface of 34 extends in the vertical direction, and the stacking of 22 of 32/22 also extends in the vertical direction. Therefore, this portion of GC is vertically aligned with 22 of 32/22)
For the sake of clarity, note that as “independent gates” have been interpreted herein to mean gates with a single associated routing track, and a “shared gate” has been interpreted herein to mean two gates that share a capacitive coupling, “independent gates” and “shared gates” are, thus, not interpreted herein to be mutually exclusive.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 10 – 12 & 23 – 24 are rejected under 35 U.S.C. 103 as being unpatentable over SMITH in view of LEE (US 20230361119 A1).
Regarding Claim 10,
SMITH discloses:
The microelectronic structure of claim 1, further comprising:
[source/drains];
(400 can include source/drains, Par. 59)
SMITH, however, does not disclose:
an upper source/drain associated with each of the plurality of upper transistors;
and a lower source/drain associated with each of the plurality of lower transistors.
LEE, though, discloses:
an upper source/drain (Fig. 5: SD2; Par. 44) associated with each of the plurality of upper transistors (Fig. 4E: GE2/CH2; Par. 56);
and a lower source/drain (Fig. 5: SD1; Par. 39) associated with each of the plurality of lower transistors (Fig. 4E: GE1/CH1; Par. 56).
Further, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of SMITH with those of LEE to enable an upper source/drain to be associated with each of the plurality of upper transistors; and a lower source/drain to be associated with each of the plurality of lower transistors in SMITH according to the teachings of LEE, as SMITH does not provide structural details for the upper source/drain and the lower/source drain. Therefore, a person having ordinary skill in the art would look to the prior art for structural details for the upper source/drain and the lower/source drain recognized for their suitability and intended purpose (MPEP 2144.07). Further still, the structural details for the upper source/drain and the lower/source drain of LEE meet these criteria, as the upper source/drain and lower source/drain of both SMITH and LEE are intended to accommodate a stacked transistor configuration (SMITH Fig. 4 & LEE Fig. 4D).
Regarding Claim 11,
SMITH does not disclose:
The microelectronic structure of claim 10, further comprising:
an upper contact that is connected to the upper source/drain.
LEE, though, discloses:
an upper contact (Fig. 5: AC2; Par. 45) that is connected to the upper source/drain.
(Fig. 5: AC2 is connected to SD2.)
Regarding Claim 12,
SMITH does not disclose:
The microelectronic structure of claim 10, further comprising:
a lower contact that is connected to a top surface of the lower source/drain, wherein the lower contact is adjacent to the upper source/drain.
LEE, though, discloses:
a lower contact (Fig. 5: AC1; Par. 45) that is connected to a top surface of the lower source/drain, wherein the lower contact is adjacent to the upper source/drain.
(Fig. 5: AC1 is connected to the top surface of SD1, wherein AC1 is adjacent to SD2.)
Regarding Claim 23,
SMITH discloses:
A microelectronic structure (Fig. 4: 400; Par. 54) comprising:
a plurality of lower transistors (Fig. 4: 33/23 and 32/22; Par. 54 – 55) and a plurality of upper transistors (Fig. 4: 35/25 and 34/24; Par. 54 – 55),
wherein each of the plurality of upper transistors includes a plurality of upper channel layers (Fig. 4: 35/25 includes 25 and 34/24 includes 24),
wherein each of the plurality of lower transistors includes a plurality of lower channel layers (Fig. 4: 33/23 includes 23 and 32/22 includes 22),
wherein the plurality of upper channel layers of the plurality of upper transistors are staggered from the plurality of lower channel layers of the plurality of lower transistors;
(Fig. 4: 25 of 35/25 is staggered from 22 of 32/22 and 24 of 34/24 is staggered from 23 of 33/23. Therefore, 25 and 24 of 35/25 and 34/24 are staggered from 22 and 23 of 32/22 and 33/23.)
[source/drains];
(400 can include source/drains, Par. 59)
a lower dielectric gate cut (Fig. 4: trench 1330 filled with dielectric 1410, hereinafter denoted LDGC; Par. 54) located beneath an upper transistor (Fig. 4: LDGC is located—indirectly—beneath 35/25),
wherein the lower dielectric gate cut separates lower transistors,
(Fig. 4: LDGC separates 33/23 and 32/22)
wherein the lower dielectric gate cut is vertically aligned with the plurality of upper channel layers of the upper transistor;
(Fig. 4: LDGC extends in the vertical direction. The stacking of 25 of 35/25 also extends in the vertical direction. Therefore, the LDGC is vertically aligned with 25 of 35/25.)
an independent gate (Fig. 4: 33/2230(3), which is independent as it has only one associated routing track 2220(3)) surrounding the lower channel layers of a first lower transistor (Fig. 4: 33/23),
(Fig. 4: 33/2230(3) surrounds 23 of 33/23)
wherein the independent gate is isolated from the other lower transistors and upper transistors.
(Fig. 4: 33/2230(3) is isolated—via 1410—from 32/22, 35/25, and 34/2)
SMITH, however, does not disclose:
an upper source/drain associated with each of the plurality of upper transistors
and a lower source/drain associated with each of the plurality of lower transistors;
LEE, though, discloses:
an upper source/drain (Fig. 5: SD2; Par. 44) associated with each of the plurality of upper transistors (Fig. 4E: GE2/CH2; Par. 56)
and a lower source/drain (Fig. 5: SD1; Par. 39) associated with each of the plurality of lower transistors (Fig. 4E: GE1/CH1; Par. 56);
Further, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of SMITH with those of LEE to enable an upper source/drain to be associated with each of the plurality of upper transistors; and a lower source/drain to be associated with each of the plurality of lower transistors in SMITH according to the teachings of LEE, as SMITH does not provide structural details for the upper source/drain and the lower/source drain. Therefore, a person having ordinary skill in the art would look to the prior art for structural details for the upper source/drain and the lower/source drain recognized for their suitability and intended purpose (MPEP 2144.07). Further still, the structural details for the upper source/drain and the lower/source drain of LEE meet these criteria, as the upper source/drain and lower source/drain of both SMITH and LEE are intended to accommodate a stacked transistor configuration (SMITH Fig. 4 & LEE Fig. 4D).
Regarding Claim 24,
SMITH does not disclose:
The microelectronic structure of claim 23, further comprising:
an upper contact that is connected to the upper source/drain;
and a lower contact that is connected to a top surface of the lower source/drain, wherein the lower contact is adjacent to the upper source/drain.
LEE, though, discloses:
an upper contact (Fig. 5: AC2; Par. 45) that is connected to the upper source/drain;
(Fig. 5: AC2 is connected to SD2)
and a lower contact (Fig. 5: AC1; Par. 45) that is connected to a top surface of the lower source/drain, wherein the lower contact is adjacent to the upper source/drain.
(Fig. 5: AC1 is connected to the top surface of SD1, wherein AC1 is adjacent to SD2)
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Kenneth S. Stephenson whose telephone number is (571)272-6686. The examiner can normally be reached Monday through Friday, 9 A.M. to 5 P.M. (EST)..
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio Maldonado can be reached at (571) 272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/K.S.S./Examiner, Art Unit 2898
/JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898